Abstract: The invention relates to a method of manufacturing implanted-base, double polysilicon bipolar transistors whose emitter, base and collector are all situated in a single active area. In accordance with the method, first the island isolation (3) defining the active area (4) in the silicon body (1) is provided, which active area forms the collector (5). A first polysilicon layer (6) is deposited on the surface. A first part (6a) of poly I is p-type doped, a second part is n-type doped. By etching, two separate parts are formed from the first poly layer, one part being p-type doped and forming a base terminal (8), the other part being n-type doped and forming a collector terminal (9), said two parts being separated by an intermediate region (16) where the surface of the active area is exposed. The edges of these poly terminals and the exposed parts of the active area are provided with spacers (13, 15) and spacers (14, 16), respectively.

Abstract: The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), and a photoresist layer positioned on the ARC defining patterns of a gate, are formed, respectively, on the semiconductor wafer. The method first involves an etching process to remove portions of both the ARC and the conductive layer uncovered by the photoresist layer to form the gate and a gate oxide layer. After the photoresist layer is stripped, an ion implantation process is performed using the gate covered by the ARC as hard mask and boron fluoride (BF2+) as the dopant to form lightly doped drains (LDD) in the substrate adjacent to the gate. Then, a spacer is formed around the gate after the ARC is removed. Finally, the method is completed with the formation of a source and a drain in the substrate adjacent to the spacer after the ARC is stripped.

Abstract: In the fabrication of a silicon bipolar transistor, a method for forming base regions and for opening an emitter window is provided. A silicon substrate is provided with suitable device isolation. A first base region is formed in or on top of the substrate. A thin layer of oxide is formed on the first base region. A layer of silicon is formed on top of the thin oxide layer, the silicon layer is to be a second base region. The silicon layer is ion implanted. A layer of a dielectric is formed on top of the silicon layer, the dielectric is to isolate base and emitter regions of the transistor. The obtained structure is patterned in order to define the emitter window. The structure inside the defined emitter window area is etched and through the dielectric and silicon layers, wherein the thin oxide layer is used as etch stop, thus forming the emitter window. The structure is subsequently heat treated and thus break up the oxide such that the first and second base regions will contact each other.

Abstract: A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

Abstract: A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the current conduction path of the lateral SCR device is removed and instead of a dummy gate. Thereby, the SCR device has a narrower anode-to-cathode spacing, and then the lateral SCR device can be turned on more quickly to protect the CMOS IC's in ESD events. Additionally, the silicon area of the substrate occupied by the lateral SCR device is also saved. This method for forming a lateral SCR device without shallow-trench-isolation regions in its current path can be fully process-compatible to general CMOS technologies by only changing layout patterns in the mask layers.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates.

Abstract: An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (Vt). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1−xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: A polymer-based field effect transistor photosensitive to incident light, which may enhance the transistor's characteristics and controlling parameters of the transistor state. The transistor is comprised of a metal-insulator-semiconductor structure with the insulating and semiconducting layers made of a polymeric media. The semiconducting polymer which also is photoconducting, forms the charge transport layer between the source and drain. The transistor exhibits large photosensitivity indicated by the sizable changes in the drain-source current, by a factor of 100-1000 even at low levels of light with illumination of approximately 1 mlux. The photosensitivity of the transistor is further enhanced with introduction of dilute quantity electron acceptor moieties in the semiconducting polymer matrix. Several applications of the light-responsive polymer-transistor are disclosed, such as use as a logic element and as a backbone of an image sensor.

Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: A bipolar transistor (10) in an IC includes a semiconductor wafer defining a collector area (14) with a first conductivity type, a base area (20) with a second conductivity type formed in the collector area (14), and an emitter formed in the base area. A field oxide is positioned on the surface of the semiconductor wafer surrounding the emitter (30) and substantially covering the base area (20) and an implant of the second conductivity type is positioned in the base area (20) between and spaced from the emitter (30) and the outer periphery of the base area (20). The implant further has a heavier concentration of the second conductivity type than the base area to compensate for loss of the second conductivity type under the field oxide and to separate the transistor current path from the breakdown path, which improves the collector to emitter breakdown voltage (BVCEO) while still maintaining a high beta.

Abstract: The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form of an island and is rectangular when view from above. The isolation area is formed of a dielectric material around the transistor area, and the base area is formed around the emitter area which forms the central area of the transistor area. A contact groove is formed at the inner interface of the isolation groove which faces the outer surface of the transistor area, and a part of the base electrode is buried in the contact groove and faces at least one of the upper surface of the transistor area and an inner surface of the contact groove.

Abstract: The present invention relates to a method of manufacturing the base and emitter regions of a bipolar transistor, including the steps of depositing a first heavily-doped P-type polysilicon layer; eliminating the first polysilicon layer in its central portion; growing a thermal oxide layer; performing a P-type implantation at a first dose; forming silicon nitride spacers at the internal periphery of the first layer; performing a second P-type implantation at a second dose; eliminating the central oxide layer; depositing a second N-type polysilicon layer; and performing a fast thermal anneal; the second dose being selected to optimize the characteristics of the base-emitter junction and the first dose being smaller than the second dose.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).

Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Abstract: A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 1014 cm−2 before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

Abstract: A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via multiple ion implantation procedures, performed through, and self-aligned to, an overlying emitter opening, in an oxide layer. The self-aligned collector regions, completely fill the space in the lighter doped collector region, located between the overlying base region, and the underlying subcollector region.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A semiconductor integrated circuit device comprises an active device and a resistance element formed monolithically on a common substrate wherein the resistance element includes a dummy pattern having a layered structure identical with a layered structure of the active device, and first and second electrodes are provided inside a mesa structure provided for the resistance element with a separation from a sidewall of the mesa structure, the first and second electrodes being formed in correspondence to openings formed in the dummy pattern.

Abstract: A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid collector emitter breakdown during operation. According to the method an integrated resistor is arranged along at least one side of a silicon bipolar transistor on a semiconductor die which constitutes a substrate for the silicon bipolar transistor. The integrated resistor is connected between the base and emitter terminals of the silicon bipolar transistor. The added integrated resistor is a diffused p+ resistor on said. semiconductor die or a polysilicon or NiCr resistor placed on top of the isolation layers. In an interdigitated transistor structure provided with integrated emitter ballast resistors the added resistor or resistors will be manufactured in a step simultaneously as producing the ballast resistors.

Abstract: Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by the use of an angled ion implant of collector impurities through the emitter opening. The resulting area of increased collector doping is larger than the emitter opening, which minimizes carrier injection from the emitter to the collector, but is smaller than the area of the base.

Abstract: A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ floating region passivates the silicon surface to reduce dark currents. Unlike a traditional pinned photodiode structure, the P+ region in the present invention is not connected to the Pwell or Psub regions, thus making the P+ region floating. This avoids the addition of extra capacitance to the cell. The photodiode may be included as part of an active pixel sensor cell, the layout of which is fully compatible with the standard CMOS fabrication process. This type of active pixel sensor cell includes the photodiode, and may be configured with a three transistor configuration for reading out the photodiode signals.

Abstract: In a method of manufacturing a semiconductor device, a first insulating film is formed on a semiconductor substrate, a first conductive film is formed on the first insulating film, and a second insulating film is formed on the first conductive film. An opening is formed to the semiconductor substrate through the second insulting film, the first conductive film and the first insulting film to expose a portion of a surface of the semiconductor substrate and a portion of a surface of the first conductive film. The exposed surface portion of the first conductive film is covered by a covering film. Thermal treatment is carried out to clean the exposed surface portion of the semiconductor substrate. A spacer film is formed in the opening on the exposed surface portion of the semiconductor substrate, and then the covering film is removed. Subsequently, an electrode film is formed on the spacer film.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A selective etching method in the fabrication of a semiconductor device is provided. The method involves the steps of: depositing an amorphous layer of semiconductor material on a monocrystalline substrate of the same semiconductor material; depositing at least one dielectric layer on the amorphous layer such as to prevent crystallization of said amorphous layer; patterning the resultant structure and thereafter etching away the dielectric layer and the amorphous semiconductor layer within a predetermined area or region; and heat-treating the resulting structure.

Abstract: A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method includes the following steps. First, a first oxide layer is formed on a p-type substrate, followed by developing a first photoresist pattern on the first oxide layer. A first, doped region is formed in the exposed substrate by a first implanting step. The first doped region comprises a n+ buried layer. Stripping of the first photoresist pattern, and annealing of the n+ buried layer follow. Removal of the first oxide layer to expose the n+ buried layer and a portion of the p-type substrate follows thereafter. These steps are followed by growing a first epitaxial layer on the n+ buried layer and a portion of the substrate, then a second epitaxial layer is formed on the first epitaxial layer. The first epitaxial layer is made of epitaxial n-type silicon, and the second epitaxial layer is made of in situ epitaxial p-type SiGe.

Abstract: A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks has a highly doped silicon n++ substrate forming the emitter. Also a low voltage high frequency silicon transistor chip presenting an epitaxial mesa technology silicon power device is presented. The silicon transistor layout presents a collector-up device with a number of single mesa collector structures. The transistor operates with its substrate as a down facing emitter, and base and collector areas together with bonding pads facing up, whereby the parasitic base-to-collector capacitance is almost entirely eliminated with the emitter as substrate. The reduced number of necessary fabrication process steps of this new structure is outlined.

Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.

Abstract: A monolithically integrated semiconductor device comprises: a hetero-junction bipolar transistor having at least an electrode contact layer which contacts directly with at least one of collector, base and emitter electrodes; and at least a passive device having at least a passive device electrode and at least a resistive layer, wherein the electrode contact layer and the resistive layer comprise the same compound semiconductor layer.

Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.

Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.

Abstract: A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material.

Abstract: A semiconductor device includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of the semiconductor layered structure so as to extend over a top surface of the support member. The interconnection layer is in contact with only a top surface of the mesa portion without being in contact with a bottom surface of the mesa portion. The top surface of the support member has a smoothed profile, and the top surface of the mesa portion and the smoothed top surface of the support member are in substantially the same plane.

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

Abstract: A semiconductor device, such as a BICMOS, includes a bipolar transistor having at least an emitter region. An emitter electrode is formed on the emitter region. Further, a wiring pattern is formed over the emitter region. A plurality of contact plugs are formed to electrically connect the emitter electrode with the wiring pattern. The contact plugs are partially embedded in the emitter electrode in order to prevent of reduction of the current amplification factor of the bipolar transistor.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor device. This semiconductor device is provided with a first n-type well and a second n-type well formed at substantially the same depths in a semiconductor substrate, an NPN bipolar transistor formed within the first n-type well which uses the n-type well as its collector, a p-type well formed within the second n-type well, and a PNP bipolar transistor formed within the p-type well which uses the p-type well as its collector.