Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract: There is provided a solid-state image sensor including a first region in which light is converted into electricity, and a second region composed of silicide. The second region at least partially forms a boarder area of the first region at a surface of the first region. The solid-state image sensor prevents occurrence of smear.

Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

Abstract: The semiconductor device comprises a p type Si substrate 10; a SiGe buffer layer 12 formed on the p type Si substrate 10 and having element isolation grooves 16 formed in the surface, which define an active region 18; a SiGe regrown buffer layer 20 formed on the SiGe buffer layer 12; a strained Si channel layer 22 formed on the side walls of the element isolation grooves 16 and on the SiGe regrown buffer layer 20 in the active region; a SiN film 24 formed on the strained Si channel layer 22 on the side walls of the element isolation grooves 16; and an element isolation insulation film 26 buried in the element isolation grooves.

Abstract: In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.

Abstract: A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially formed semiconductor device. The method further includes doping at least a portion of the at least one amorphous region to form at least one junction within the at least partially formed semiconductor device. The method also includes performing solid phase epitaxial re-growth to activate the doped portion of the at least one amorphous region of the at least partially formed semiconductor device.

Abstract: The present invention relates to a photoreceiver and method of manufacturing the same. For the purpose of a selective detection of a specific wavelength, if a waveguide type photodetector using a multiple quantum-well layer having a quantum confined stark effect as an optical absorption layer, the wavelength that is absorbed by the stark effect by which the transition energy edge of the optical absorption band is varied depending on the intensity of an electric field applied to the multiple quantum-well layer is varied. Thus, a wavelength selective detection characteristic can be varied simply implemented. The waveguide type photodetector of this structure is integrated on a semi-insulating InP substrate with a heterogeneous bipolar transistor having an n+InP/p+InGaAs/n−InGaAs/n+InGaAsP high-gain amplification characteristic.

Abstract: A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example, the epitaxial emitter may be N-type single-crystal silicon. The heterojunction bipolar transistor further comprises an etch stop layer situated on the top surface of the base, where the etch stop layer is in contact with the epitaxial emitter. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the etch stop layer, where the epitaxial emitter is situated between the first and second spacer. The first spacer and the second spacer, for example, may be LPCVD silicon nitride. The heterojunction bipolar transistor further comprises a dielectric layer deposited on the first and second spacers.

Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.

Abstract: A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: Supermolecular structures and devices made from same. Semiconductor materials and devices are manufactured and provided which use controlled, discrete distribution of and positioning of single impurity atoms or molecules within a host matrix to take advantage of single charge effects. Single-dopant pn junctions and single-dopant bipolar cells are created. Each bipolar cell can function as a bistable device or an oscillator, depending on operating temperature. The cells can be used alone or in an array to make useful devices by adding an insulating substrate and contact electrodes.

Abstract: Methods of forming an electronic structure can include forming an interlayer insulating layer on a substrate, and forming a storage node comprising a base and sidewalls extending away from the base. The interlayer insulating layer can have a contact hole therein exposing a portion of the substrate. Moreover, the storage node base can be in the contact hole and the sidewalls can extend away from the base and away from the substrate with portions of the sidewalls being within the contact hole and with portions of the sidewalls extending outside the contact hole beyond the interlayer insulating layer away from the substrate. Related structures are also discussed.

Abstract: A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.

Abstract: The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate 1 to form a bipolar transistor having a large current capacity.

Abstract: A vertical bipolar transistor includes a semiconductor substrate, an extrinsic collector layer in the semiconductor substrate, an intrinsic collector on the extrinsic collector, a lateral isolating region surrounding an upper part of the intrinsic collector, an offset extrinsic collector well, a base including a semiconductor region above the intrinsic collector and above the lateral isolating region including at least one silicon layer, and a doped emitter surrounded by the base. The doped emitter may include first and second parts. The first part may be formed from single-crystal silicon and in direct contact with the upper surface of the semiconductor region in a predetermined window in the upper surface above the intrinsic collector. The second part may be formed from polycrystalline silicon. The two parts of the emitter may be separated by a separating oxide layer spaced apart from the emitter-base junction of the transistor.

Abstract: A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Abstract: A first aspect of the invention is to realize a power amplifier having high power adding efficiency and high power gain at low cost. For that purpose, in a semiconductor device using an emitter top heterojunction bipolar transistor formed above a semiconductor substrate and having a planar shape in a ring-like shape, a structure is provided in which a base electrode is present only on an inner side of a ring-like emitter-base junction region. In this way, as a result of enabling to reduce base/collector junction capacitance per unit emitter area without using a collector top structure having complicated fabricating steps, a semiconductor device having high power adding efficiency and high-power gain and suitable for a power amplifier can be realized.

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: The invention concerns an integrated circuit, comprising a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a Vcc power supply terminal, an input point (in) and an output point (out). At least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means comprise two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate.

Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

Abstract: A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q11) are not directly connected to the drain of an MOS transistor (Q4) but are connected to the base of a bipolar transistor (Q12). The second field transistor (Q11) has its source connected to the collector of the bipolar transistor (Q12) and the MOS transistor (Q4) has its drain connected to the emitter of the bipolar transistor (Q12). When the current amplification factor of the bipolar transistor (Q12) is taken as &bgr;, then the current of the output (SO) can be increased approximately &bgr; times.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. Additionally, the gate and body of the transistors are biased to modify the threshold voltage of the transistor (Vt). The conductive sidewall member configuration conserves surface space and achieves a higher density of surface structures per chip. The structures offer performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: A multiplicity of components form a photodiode array on a substrate. Each of the components consists of a transistor of the p-n-p type with the outermost p-doped layer being transformed into an optical filter by control of the anodic etching operation utilizing transistor characteristics of the respective transistor. The result can provide red, blue and green filters in a color camera.

Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Abstract: An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.

Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.

Abstract: A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Bread down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Abstract: An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein the insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the single crystal layer, wherein the emitter diffusion has an emitter diffusion junction depth.

Abstract: The invention relates to a method for producing bipolar transistors with the aid of selective epitaxy for producing a collector and base. The inventive method is advantageous in that the area of the base is widened by the isotropic etching of the conductive layer or by the oxidation of the conductive layer and by the subsequent removal of the oxide layer. This widening of the area of the base prevents the occurrence of short-circuits between the emitter and the collector during the subsequent production of the base.

Abstract: A heterojunction bipolar transistor has a stack comprised of a base layer, an emitter layer and a ballast layer made of AlGaAs. The emitter layer is comprised of a single layer or a multiplicity of layers, and at least one of which is comprised of a material that prevents hole injection from the base layer into the ballast layer. Thus, the hole injection from the base layer into the emitter layer is prevented. Accordingly, it is able to prevent the conductivity modulation of the ballast layer that is the cause of a deterioration in temperature characteristics.

Abstract: A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has an extrinsic base region of the first conductivity type and an emitter region of the second conductivity type, both of which extend from the substrate's upper surface into the base region. The bipolar transistor structure also includes a single patterned polysilicon layer with a first polysilicon portion of the first conductivity type in contact with the extrinsic base region and a second polysilicon portion of the second conductivity type in contact with the emitter region. The bipolar transistor structure is compact since contact to the extrinsic base region is made by the first polysilicon portion, which can be formed to a minimum dimension and self-aligned to the extrinsic base region.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: An emitter of a heterojunction bipolar transistor has a double-layer protrusion formed of a first emitter layer and a second emitter layer and protruded outside an external base region. The protrusion of 50 nm in total thickness is enough to prevent damage during formation of the protrusion by etching or during later fabricating processes. Penetration of moisture through damaged places is eliminated. A base ohmic electrode is continuously formed on the first and second emitter layers on the external base region up to the protrusion. Thus, the protrusion is reinforced so as to be further hard to damage. By ensuring a large area for the base ohmic electrode, an alignment margin can be taken during formation of a base lead electrode.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-gernaniuim base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicongermanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic.

Abstract: In the fabrication of a transistor device, particularly a low-voltage high-frequency transistor for use in mobile telecommunications, a method for improving the transistor performance and the high-frequency characteristics of the device is described. The method includes providing a semiconductor substrate (1) with an n-doped collector layer (5) surrounded by isolation areas (4), implanting antimony ions into the collector layer such that a thin highly n-doped layer (18) is formed in the uppermost portion of the collector layer, and forming a base on top of said thin highly n-doped layer (18).

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

Abstract: In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer, the point of the highest impurity concentration is located closer to the n-type base layer than the junction with the emitter layer. In other words, the pinch-off of the channel is generated in the position closer to the n-type base layer than to the junction between the p-type base layer and the n-type emitter layer.

Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.

Abstract: The present invention relates to a method for reducing low-frequency noise in a cooled circuit wherein low-frequency noise in a cryogenic semiconductor device is reduced by carrying out thermal cure. The semiconductor device is turned on at a first temperature, and the temperature of the semiconductor device is temporarily raised, while flowing current in the semiconductor device, to a second temperature that is higher than the first temperature, and then cooling the temperature of the semiconductor device from the second temperature to a cryogenic temperature, at which the semiconductor device can operate.

Abstract: A III-N compound semiconductor bipolar transistor structure and method of manufacture. An epitaxial layer structure is formed over a substrate. The epitaxial layer structure includes a nucleation layer, a buffer layer, an emitter layer containing first type dopants (conductive type) and a base layer containing second type dopants (conductive type). Ion implantation is conducted to form a first conductive region within the base layer for forming a collector terminal. A portion of the emitter layer is etched for forming an emitter terminal. In addition, two ion-implantation regions may form inside the base layer. The ion-implantation regions serve separately as the collector terminal and the emitter terminal of the bipolar transistor, respectively, so that a more planar transistor structure is formed.

Abstract: A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. After an etching process removes the sacrificial mesa and the SiGe layer is exposed, an oppositely doped material is applied over top of the SiGe layer to form an emitter. This makes it possible to realize a thin layer of silicon germanium to serve as the transistor base. This method prevents the base layer SiGe from being affected, as it otherwise would be using a conventional double-poly process.

Abstract: The present invention relates to an integrated circuit having a sealed nitride layer. In one embodiment, a method of forming a sealing nitride layer overlaying a silicon oxide layer in a contact opening of an integrated circuit is disclosed. The method comprises, forming a second layer of nitride overlaying a first layer of nitride to form the sealing nitride layer. The second layer of nitride further overlays an exposed portion of a surface of a substrate in the contact opening and sidewalls of the contact opening. Using reactive ion etching (RIE etch) without a mask to remove a portion of the second nitride layer adjacent the surface of the substrate in the contact opening to expose a portion of the surface of the substrate in the contact opening without removing portions of the second nitride layer covering the sidewalls of the contact opening.

Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33).