Abstract: A flexible polymer or elastomer coated RF return strap to be used in a plasma chamber to protect the RF strap from plasma generated radicals such as fluorine and oxygen radicals, and a method of processing a semiconductor substrate with reduced particle contamination in a plasma processing apparatus. The coated RF strap minimizes particle generation and exhibits lower erosion rates than an uncoated base component. Such a coated member having a flexible coating on a conductive flexible base component provides an RF ground return configured to allow movement of one or more electrodes in an adjustable gap capacitively coupled plasma reactor chamber.

Abstract: A method of etching or removing an organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the organic hardmask with the plasma, with the organic hardmask being at a temperature in excess of 200° C., to remove the organic hardmask without substantially harming the underlying substrate.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: The present invention provides a plasma processing apparatus having a radio frequency power supply supplying time-modulated radio frequency power which is controllable widely with high precision, and a plasma processing method using the plasma processing apparatus. The plasma processing apparatus includes: a vacuum chamber; a first radio frequency power supply for generating plasma in the vacuum chamber; a sample holder disposed in the vacuum chamber, on which a sample is placed; and a second radio frequency power supply supplying radio frequency power to the sample holder, wherein at least one of the first radio frequency power supply and the second radio frequency power supply supplies time-modulated radio frequency power, one of parameters of controlling the time-modulation has two or more different control ranges, and one of the control ranges is a control range for a high-precision control.

Abstract: Methods of silicon etch for trench sidewall smoothing are described. In one embodiment, a method involves smoothing a sidewall of a trench formed in a semiconductor wafer via plasma etching. The method includes directionally etching the semiconductor wafer with plasma generated from a fluorine gas to smooth the sidewall of the trench, the trench having a protective layer formed by plasma generated by a second process gas such as oxygen or a polymerization gas. In another embodiment, a method involves etching a semiconductor wafer to generate a trench having a smooth sidewall. The method includes plasma etching the semiconductor wafer with one or more first process gases including a fluorine gas, simultaneously performing deposition and plasma etching the semiconductor wafer with one or more second process gases including a fluorine gas and a polymerization gas mix, and performing deposition with one or more third process gases including a polymerization gas.

Abstract: A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described. Semiconductor device structures are also described.

Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.

Abstract: The present invention aims to prevent decreases in etching rate due to adhesion of an etched film to a substrate holder. A method of manufacturing a magnetic recording medium includes: forming a first film on a substrate holder not yet having a substrate mounted thereon; mounting a substrate on the substrate holder having the first film formed thereon, the substrate having a resist layer formed on a multilayer film including a magnetic film layer, the resist layer having a predetermined pattern; and processing the magnetic film layer into a shape based on the predetermined pattern by performing dry etching on the substrate. The first film is a film that is not etched as easily as the films in the multilayer film to be removed by the dry etching.

Abstract: Techniques for minimizing or eliminating pattern deformation during lithographic pattern transfer to inorganic substrates are provided. In one aspect, a method for pattern transfer into an inorganic substrate is provided. The method includes the following steps. The inorganic substrate is provided. An organic planarizing layer is spin-coated on the inorganic substrate. The organic planarizing layer is baked. A hardmask is deposited onto the organic planarizing layer. A photoresist layer is spin-coated onto the hardmask. The photoresist layer is patterned. The hardmask is etched through the patterned photoresist layer using reactive ion etching (RIE). The organic planarizing layer is etched through the etched hardmask using RIE. A high-temperature anneal is performed in the absence of oxygen. The inorganic substrate is etched through the etched organic planarizing layer using reactive ion etching.

Abstract: A plasma processing apparatus includes a baffle ring which separates an internal space of a vacuum chamber into a plasma space and an exhaust space. Plasma is generated in the plasma space by exciting a process gas using an energy source. The process gas is then exhausted out of the plasma space through the plasma baffle ring which surrounds an outer periphery of a substrate support. The plasma baffle ring comprises an inner support ring, an outer support ring, and vertically spaced apart circumferentially overlapping rectangular blades extending between the inner ring and the outer ring. Each blade has a major surface used to block a line of sight from the plasma space to the exhaust space, wherein the major surfaces of the blades are configured to capture nonvolatile by-products, such as plasma etch by-products, before the by-products evacuate the plasma space.

Abstract: A movable symmetric chamber liner in a plasma reaction chamber, for protecting the plasma reaction chamber, enhancing the plasma density and uniformity, and reducing process gas consumption, comprising a cylindrical wall, a bottom wall with a plurality of openings, a raised inner rim with an embedded heater, heater contacts, and RF ground return contacts. The chamber liner is moved by actuators between an upper position at which substrates can be transferred into and out of the chamber, and a lower position at which substrate are processed in the chamber. The actuators also provide electrical connection to the heater and RF ground return contacts.

Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

Abstract: A method for the selective removal of material from a substrate surface for forming a deepening includes the steps of applying a mask onto the substrate surface in accordance with the desired selective removal and dry-etching the substrate, a metal, preferably aluminum, being used as the masking material. Power may be coupled inductively to a plasma.

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Abstract: An exemplary method is directed to powering heaters in a substrate support assembly on which a semiconductor substrate is supported. The support assembly has an array of heaters powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to a power supply and at least two of the heaters and each power return line is connected to at least two of the heaters, and a switching device which independently connects each one of the heaters to one of the power supply lines and one of the power return lines so as to provide time-averaged power to each of the heaters by time divisional multiplexing of switches of the switching device. The method includes supplying power to each of the heaters sequentially using a time-domain multiplexing scheme.

Abstract: Methods of patterning low-k dielectric films are described.

Abstract: A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer. Then, a dielectric layer is formed over the first hard mask layer and filled into an opening of the trench pattern. Then, a second hard mask layer with a via opening pattern is formed over the first hard mask layer and the dielectric layer. Then, a first etching process is performed, so that a via opening is at least formed in the dielectric layer. After the second hard mask layer is removed, a second etching process is performed. Consequently, a trench opening is formed in the material layer and the via opening is further extended into the material layer, wherein the via opening is located within the trench opening.

Abstract: The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column direction over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. An etch mask film is formed over the semiconductor substrate including the auxiliary film. An etch process is performed in order to form second etch mask patterns having the second pitch in such a manner that the etch mask film, the auxiliary film, and the first etch mask patterns are isolated from one another in a row direction and the etch mask film remains between the first etch mask patterns. The auxiliary film between the first and second etch mask patterns is removed.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.

Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.

Abstract: There is provided a plasma processing apparatus capable of optimizing a plasma process in response to various requirements of a micro processing by effectively controlling a RF bias function. In this plasma processing apparatus, a high frequency power RFH suitable for generating plasma of a capacitively coupling type is applied to an upper electrode 48 (or lower electrode 16) from a third high frequency power supply 66, and two high frequency powers RFL1 (0.8 MHz) and RFL2 (13 MHz) suitable for attracting ions are applied to the susceptor 16 from first and second high frequency power supplies 36 and 38, respectively, in order to control energy of ions incident onto a semiconductor wafer W from the plasma. A control unit 88 controls a total power and a power ratio of the first and second high frequency powers RFL1 and RFL2 depending on specifications, conditions or recipes of an etching process.

Abstract: A plasma etching method for forming a hole in an etching target film by a plasma processing apparatus is provided. The apparatus includes an RF power supply for applying RF power for plasma generation to at least one of upper and lower electrodes, and a DC power supply for applying minus DC voltage to the upper electrode. A first condition that plasma is generated by turning on the RF power supply and minus DC voltage is applied to the upper electrode and a second condition that the plasma is extinguished by turning off the RF power supply and minus DC voltage is applied to the upper electrode are alternately repeated. Etching is performed by positive ions in the plasma under the first condition and negative ions are supplied into the hole by the DC voltage to neutralize positive ions in the hole under the second condition.

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.

Abstract: In one embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines. In another embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure, etching the multi-layer structure to expose the conductive metal, sputter etching conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines, forming a liner that surrounds the conductive lines, subsequent to the sputter etching, and depositing a dielectric layer on the multi-layer structure.

Abstract: A plasma etching apparatus performs plasma etching on a substrate having a resist pattern formed thereon and an outer edge portion where the substrate surface is exposed. The plasma etching apparatus includes a support part that supports the substrate, a cover member that covers the outer edge portion of the substrate and prevents plasma from coming around the outer edge portion, and a control unit that generates plasma by controlling high frequency power application and supply of a processing gas for etching, and uses the generated plasma to etch the substrate that is supported by the support part and has the outer edge portion covered by the cover member. After etching the substrate, the control unit generates plasma by controlling high frequency power application and supply of a processing gas for ashing, and uses the generated plasma to perform ashing on the resist pattern on the etched substrate.

Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.

Abstract: A plasma etching method capable of forming a tapering etching structure having a smooth surface is provided. A fluorine-containing gas and a nitrogen gas are used and plasma is generated from these gases simultaneously, and a silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma and then a fluorine-containing gas and an oxygen-containing gas are used and plasma is generated from these gases simultaneously, and the silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma generated from the oxygen-containing gas, thereby forming a tapering etching structure H having a wide top opening width and a narrow bottom width.

Abstract: Provided is a substrate dechucking system of a plasma processing chamber adapted to remove a substrate from an ESC with reduction in voltage potential spike during dechucking of the substrate.

Abstract: A plasma treatment system for treating a workpiece with a downstream-type plasma. The processing chamber of the plasma treatment system includes a chamber lid having a plasma cavity disposed generally between a powered electrode and a grounded plate, a processing space separated from the plasma cavity by the grounded plate, and a substrate support in the processing space for holding the workpiece. A direct plasma is generated in the plasma cavity. The grounded plate is adapted with openings that remove electrons and ions from the plasma admitted from the plasma cavity into the processing space to provide a downstream-type plasma of free radicals. The openings may also eliminate line-of-sight paths for light between the plasma cavity and processing space. In another aspect, the volume of the processing chamber may be adjusted by removing or inserting at least one removable sidewall section from the chamber lid.

Abstract: Provided is a plasma processing apparatus which includes a plurality of upstream-side expansion valves and a plurality of downstream-side expansion valves connected to respective refrigerant inlets and respective refrigerant outlets to adjust a flow rate or a pressure of a refrigerant flowing into the respective refrigerant inlets and a flow rate or a pressure of a refrigerant flowing out from the respective refrigerant outlets. Openings of the upstream-side expansion valves and openings of the downstream-side expansion valves are adjusted so that no change in flow rate of the refrigerant occurs in a plurality of refrigerant channels between the plurality of upstream-side expansion valves and the plurality of downstream-side expansion valves via the plurality of refrigerant channels in a refrigeration cycle allowing the refrigerant to flow therein.

Abstract: Substrate processing systems and methods for etching an atomic layer are disclosed. The methods and systems are configured to introducing a first gas into the chamber, the gas being an etchant gas suitable for etching the layer and allowing the first gas to be present in the chamber for a period of time sufficient to cause adsorption of at least some of the first gas into the layer. The first gas is substantially replaced in the chamber with an inert gas, and metastables are then generated from the inert gas to etch the layer with the metastables while substantially preventing the plasma charged species from etching the layer.

Abstract: There is provided a semiconductor device manufacturing apparatus capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing apparatus includes: an etching processing mechanism for performing an etching process that etches a low dielectric insulating film formed on a substrate; a CO2 plasma processing mechanism for performing a CO2 plasma process that exposes the substrate to CO2 plasma after the etching process; a polarization reducing mechanism for performing a polarization reducing process that reduces polarization in the low dielectric insulating film after the CO2 plasma process; and a transfer mechanism for transferring the substrate.

Abstract: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: In a plasma etching method, a substrate, on which an oxide film as a target layer to be etched, a hard mask layer, and a patterned photoresist are sequentially formed, is loaded into the processing chamber and mounted on a lower electrode. A processing gas containing CxFy (x is 3 or less and y is 8 or less), C4F8, a rare gas and O2 is supplied and a plasma of the processing gas is generated by applying a high frequency power to an upper or a lower electrode. Further, a high frequency power for bias is applied to the lower electrode, and a DC voltage is applied to the upper electrode.

Abstract: A plasma etching method is provided to perform a plasma etching on a silicon oxide film or a silicon nitride film formed below an amorphous carbon film by using a pattern of the amorphous carbon film as a final mask in a multilayer mask including a photoresist layer having a predetermined pattern, an organic bottom anti-reflection coating (BARC) film formed below the photoresist layer, an SiON film formed below the BARC film, and the amorphous carbon film formed below the SiON film. An initial mask used at the time when the plasma etching of the silicon oxide film or the silicon nitride film is started is under a state in which the SiON film remains on the amorphous carbon film and a ratio of a film thickness of the amorphous carbon film to a film thickness of the residual SiON film is smaller than or equal to about 14.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A method for etching a metal layer, comprising plurality of cycles is provided. In each cycle, an etch gas comprising PF3, CO and NO, or COF2 is flowed into a process chamber. In each cycle, the etch gas is formed into a plasma. In each cycle, the flow of the etch gas is stopped.

Abstract: Provided is a seal member according to embodiments. The seal member is disposed between an upper electrode and a backing plate in an etching apparatus to seal a gap between the upper electrode and the backing plate. In addition, the seal member is configured to include a high heat conductivity member having a heat conductivity higher than that of a first member formed by using siloxane bond and a low resistance member having a resistivity lower than that of the first member.

Abstract: A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

Abstract: Methods for forming microlenses on a semiconductor substrate are provided. An inductively coupled plasma etch process using a process gas that includes a mixture of CF4 and CHF3 can be used to modify the lens shape of a plurality of microlens objects located on a semiconductor substrate to meet microlens specifications in terms of curvature, height, length, shape, and/or distance between adjacent microlens objects on the substrate. The inductively coupled plasma process can be performed in an inductively coupled plasma processing apparatus that includes a grounded Faraday shield to prevent any capacitive coupling during the plasma etching process to reduce sputtering of the microlens surface.

Abstract: A method for etching a metal layer, comprising plurality of cycles is provided. In each cycle, an etch gas comprising PF3, CO and NO, or COF2 is flowed into a process chamber. In each cycle, the etch gas is formed into a plasma. In each cycle, the flow of the etch gas is stopped.

Abstract: A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support aim is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber.

Abstract: The invention provides a method of forming a concavo-convex pattern by partly removing a magnetic layer and a carbon protective layer in an intermediate product of a magnetic recording medium having at least the magnetic layer and the protective layer formed on a substrate surface, wherein the magnetic layer is partly removed to form the concavo-convex pattern by a dry etching method using a etching gas of a mixture gas of argon and a deposition gas containing one or more types of carbon compounds. Also disclosed is a method of manufacturing a patterned medium type magnetic recording medium employing the method of forming a concavo-convex pattern. As a result a concavo-convex pattern free of after-corrosion and exhibiting good productivity is provided.

Abstract: This invention relates to a method and apparatus by integrating semiconductor manufacturing processes of stress free electrochemical copper polishing (SFP), removal of the Tantalum oxide or Titanium oxide formed during SFP process and XeF2 gas phase etching barrier layer Ta/TaN or Ti/TiN process. Firstly, at least portion of plated copper film is polished by SFP. Secondly the barrier metal oxide film formed during SFP process is etched away by etchant. Finally, the barrier layer Ta/TaN or Ta/TiN is removed with XeF2 gas phase etching. The apparatus accordingly consists of three sub systems: stress free copper electropolishing system, barrier layer oxide film removal system and barrier layer Ta/TaN or Ti/TiN gas phase etching system.

Abstract: A method for etching features in a plurality of silicon based bilayers forming a stack on a wafer in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a plasma, while providing a first pressure. A wafer temperature of less than 20° C. is maintained. The pressure is ramped to a second pressure less than the first pressure as the plasma etches through a plurality of the plurality of silicon based bilayers. The flow of the main etch gas is stopped after a first plurality of the plurality of bilayers is etched.

Abstract: A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained.