Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.

Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.

Abstract: A production system for producing products from raw materials by a production process with several steps has a number of production facilities that perform the steps and a control device. The control device determines a control target value by referring to information about group combinations specified in accordance with the relative merits of the manufacturing condition routes followed by respective lots during the production process. The routes are respectively set for a number of groups that are classified on the basis of raw material properties formed of a combination of property items of one or more types of raw materials. The relative merits of the routes are determined on the basis of quality items of the lots, classified for inter-step combinations of groups, which are classified on the basis of manufacturing conditions at the steps.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Abstract: A production system for producing products from raw materials by a production process with several steps has a number of production facilities that perform the steps and a control device. The control device determines a control target value by referring to information about group combinations specified in accordance with the relative merits of the manufacturing condition routes followed by respective lots during the production process. The relative merits are determined on the basis of quality items of the lots, classified for inter-step combinations of groups, which are classified on the basis of manufacturing conditions at the steps.

Abstract: Examples relate to determining a sampling threshold of a receiver (e.g., SERDES receiver). In particular, the examples relate to determining an updated sampling threshold of the receiver based on a reference sampling threshold of the receiver. A controller may determine the reference sampling threshold based on the training sequence and determine an upper voltage level and a lower voltage level of a voltage range based on the reference sampling threshold of the receiver. The controller then narrows the voltage range based on upper voltage accumulated hit rate and a lower voltage accumulated hit rate to determine the updated sampling threshold of the receiver.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: A method and system for capturing and annotating measurement data includes communicatively connecting a mobile computing device to one or more measurement devices, and receiving measurement data from the one or more measurement devices. The mobile computing device stores the received measurement data and annotates the stored measurement data with metadata. The metadata includes group identifying information that associates the stored measurement data with other data having similar group identifying information. In at least one embodiment, measurement data is automatically associated with the group identifying information based on the measurement data being captured within a predetermined amount of time of each other or within a predetermined distance of each other as determined by a positioning system.

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

Abstract: A clock self-testing method and circuit. The clock self-testing method includes introducing a first clock signal and a second clock signal, counting cycles of the first clock signal and the second clock signal respectively beginning at the same moment, and if one of the number of cycles of the first clock signal being counted and the number of cycles of the second clock signal being counted is equal to N, determining whether the remained number of cycles is in a count range from M to N. If the remained number of cycles is out of the count range from M to N, the first clock signal and the second clock signal have errors.

Abstract: For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.

Abstract: A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: A method for operating a communication system, in which multiple communication units exchange data via a communication medium, the method including the following steps: shifting the communication system at least temporarily into a diagnostic operating mode, in which data exchanged by multiple, in particular, by all of the communication units via the communication medium are available on at least one of the multiple communication units and/or on at least one component of the communication medium.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: A manufacturing process monitoring apparatus capable of determining a manufacturing process is anomaly, without requiring any threshold value for determining the as anomaly is provided.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: A transceiver system includes a transmitter including a first driving signal output unit and a second driving signal output unit and a receiver including a first sensing signal input unit and a second sensing signal input unit. A first channel includes a first input/output line and a second input/output line that connect the first driving signal output unit and the first sensing signal input unit, and are configured to transfer signals having different phases; a second channel including a third input/output line and a fourth input/output line that connect the second driving signal output unit and the second sensing signal input unit, and are configured to transfer signals having different phases; and a first compensation capacitor including a first electrode electrically connected to the second input/output line and a second electrode electrically connected to the third input/output line.

Abstract: A signal analysis method of analyzing a performance of a device under test is described. A digitized input signal is obtained, wherein the digitized input signal is associated with the device under test. At least one characteristic quantity is determined via an artificial intelligence circuit. The artificial intelligence circuit includes at least one computing parameter. The at least one characteristic quantity is determined based on the digitized input signal and based on the at least one computing parameter. The at least one characteristic quantity is indicative of at least one performance property of the device under test. Further, a test system for analyzing a performance of a device under test as well as a computer program or program product are described.

Abstract: A driving method of a display panel is provided. The driving method of the display panel includes: within one frame, in a charging period of sub-pixels electrically connected to an ith scan line, each multiplexing circuit charging N data lines electrically connected to the multiplexing circuit in a charging sequence of a first preset sequence; in a charging period of sub-pixels electrically connected to a jth scan line, each multiplexing circuit charging the N data lines electrically connected to the multiplexing circuit in a charging sequence of a second preset sequence; the second preset sequence is different from the first preset sequence, and charging rankings of each data line electrically connected to each multiplexing circuit in at least two charging sequences are different, where N is an integer and N?2, and i and j are positive integers and j?i.

Abstract: A demarcating system for indicating the boundary of an area to an object (for example a robot, such as a robotic lawnmower), which has a receiver for receiving electromagnetic signals. The system includes a control system, a wire loop, a signal generator, and current sensing circuitry. The wire loop can be arranged by a user along a path, so as to indicate the path to the object as part of a boundary of the area. The signal generator is electrically connected to the wire loop in order to apply voltage signals thereto, such signals causing the emission of corresponding electromagnetic boundary indicating signals from the wire loop that may be received by the receiver of the object. The signal generator is under the control of the control system with the voltage signals applied by the signal generator to the wire loop being controlled by the control system. The current sensing circuitry senses current signals present within the wire loop and the processors of the control system analyse such current signals.

Abstract: In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.

Abstract: A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Abstract: The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Abstract: A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

Abstract: A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

Abstract: A system for accelerating testing of a software program includes a virtual computer and a test execution control computer. The virtual computer imitates a microcomputer equipped with a software program to be tested. The test execution control computer divides a plurality of test scenarios into common phases; to create and store a tree structure mapping out the plurality of test scenarios, the tree structure where the common phase is followed by a non-common phase, the common phase branched out into the non-common phases. The virtual computer executes the common phase in accordance with the tree structure, and stores as a snapshot a state of the virtual computer. The virtual computer to uses the snapshot to reproduce the state of the virtual computer that has executed the common and non-common phases, when the test execution control computer causes the virtual computer to execute a second test scenario.

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

Abstract: Provided are a method of providing a communication channel for secure management between a uniway data transmitting device and a uniway data receiving device which are physically separated from each other in a uniway security gateway system, and a uniway data transceiving device for providing two uniway communication channels therefor. The uniway security gateway system includes a uniway data transmitting device located in a secure area and a uniway data receiving device located in a control area, wherein the uniway data transmitting device and the uniway data receiving device provide a first communication channel for transmitting and receiving data in one direction from the secure area to the control area and a second communication channel for transmitting and receiving management data in one direction from the control area to the secure area.

Abstract: A circuit for controlling an input current, the circuit includes a first input port configured to receive the input current. A current detector detects an input current value of the input current and generates a control signal indicative of the input current value. A first output port outputs an output current to a load. A second output port receives the output current from the load. A control circuit provides a low-impedance path in parallel with the load in response to the control signal indicating the input current value is below a threshold value.

Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

Abstract: An automated test equipment (ATE) system comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor. The tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports an arbitrary sector size, and wherein software layers on the tester processor perform computations to be able control data flow between the tester processor and sectors of arbitrary size in the DUT.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: An example memory device includes an array of memory cells, a plurality of boundary cells, mixed pads connected to the memory cells, high speed pads connected to the boundary cells, a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive at least first and second input signals, and the three state multiplexer block is connected to the mixed pads. The example memory device further includes an enabling circuit connected to a mixed pad and configured to receive an external enabling signal and provide the three state MUX with an internal enabling signal, and comprising: a tester presence detector circuit connected to the mixed pad and configured to provide a presence signal to a logical gate, the logical gate having input terminals connected to the tester presence detector circuit and configured to provide the internal enabling signal.

Abstract: An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

Abstract: A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

Abstract: An object is to provide a propagation property analyzing apparatus that can alleviate the influence of an error caused by crosstalk, and accurately evaluate a few-mode optical fiber that multiplexes a plurality of modes, in a distributional and non-destructive manner.

Abstract: Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

Abstract: A magnetic field sensor comprises a signal conditioning IC and a magnetic field sensor IC, the magnetic field sensor IC being mounted on and connected to the signal conditioning IC. The magnetic field sensor IC comprises a semi-conductor substrate with a sensor active layer disposed an outer facing side of the magnetic field sensor opposite the signal conditioning IC. The sensor active layer is connected to conductive vias that extend through the semi-conductor substrate from said outer facing side to an underside facing the signal conditioning IC, an underside of the conductive via being electrically interconnected to a connection pad on the signal conditioning IC via a chip-on-chip interconnection comprising a conductive bead connection and a solder connection.

Abstract: Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.

Abstract: This application is related to a measuring system and method for performing various measurement tasks. The measuring system comprises a test-setup configured to measure the characteristics of a device-under-test and an input-device of the test-setup configured to receive a test-case. The measuring system further comprises several measurement-hardware devices configured to perform the measurements according to the test-case. A computer unit of the measuring system is configured to determine at least one required hardware device on the basis of the test-case and to select the additional measurement-hardware devices. The computer unit is further configured to identify an adding of the selected additional measurement-hardware.

Abstract: An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.

Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.

Abstract: Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.

Abstract: Techniques to determine whether the design of integrated circuit (IC) has been tampered with during wafer manufacturing by using an enhanced library and layout methodology. The enhanced library may include location sensitive cells networked together in a mesh architecture where paths through the mesh can be used to detect relative position of location sensitive cells. The techniques further include algorithms that fill any unused space on an IC with additional elements from the enhanced library to minimize the opportunity to modify the IC by including additional circuit function or manipulating the layout. By physically locking down the circuit placement such that there is no available area and gives improved ability to detect changes in the physical location behavior of the circuit, therefore reduces the risk that unauthorized circuit manipulation will go undetected.

Abstract: A waveform data acquisition module acquires the waveforms of electrical signals for multiple channels. A memory controller continuously writes a digital signal S3 to one from among a first memory unit and a second memory unit. When a given memory unit has become full, the memory controller notifies an external higher-level controller that the corresponding memory unit is full and switches the wiring target to the other memory unit.

Abstract: A system on a chip (SoC) for smoke detection includes power regulator circuits coupled to respective pins and analog sensor amplifier circuits that are each coupled to a respective pin of the pins coupled to the power regulator circuits. A first analog sensor amplifier circuit of the analog sensor amplifier circuits has a photoelectric amplifier circuit, a first LED driver and a second LED driver. The SoC also has a digital core that includes a digital logic circuit, register bits, and an MCU communication circuit. The MCU communication circuit is coupled to a data pin, the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written to by an MCU.