Abstract: A method, system and computer program product for performing error correction are disclosed. The method includes performing on source code a selected compilation operation from among a set of compilation operations and, responsive to encountering an error in the selected compilation operation, running an error handler to isolate the error utilizing data logged for the compilation operation. Responsive to determining that the error handler has not sufficiently isolated the error, a source code modifier is run to modify a portion of the source code selected by reference to the data logged for the compilation operation.

Abstract: Certain aspects of a method and system for interlocking data integrity for network adapters are disclosed. Aspects of one method may include executing a plurality of interlocking checks within a network adapter. Each interlocking check may comprise receiving a plurality of input check values associated with a plurality of input data packets corresponding to a first protocol. A plurality of check values may be generated which are associated with the plurality of input data packets and a plurality of output data packets corresponding to a second protocol. The data integrity of the plurality of input data packets and the plurality of output data packets may be validated based on one or more comparisons between one or more of the generated plurality of check values and one or more of the received plurality of input check values.

Abstract: A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

Abstract: There is provided a time-division duplex transmit-receive apparatus in which the respective amplitude and phase characteristics of N sets of transmitting unit-receiving unit pair connected with N antenna elements are corrected all together and at the same time. At the time of reception, the reference signal from reference signal generator is branched into N reference signals. The branched reference signal is applied to the reception system through the transmit-receive switching switch. The reception-side error detector detects the error between the output signal of the reception-side amplitude-phase correction circuit and the reference signal to control the reception-side amplitude-phase correction circuit so that the error becomes zero. At the time of transmission, a part of transmitting signal is applied to the reception system through the antenna path.

Abstract: A decoding device includes a decoding unit that decodes control data to generate decode data, the control data indicating a state of a radio propagation channel; a reliability calculating unit that calculates a reliability indicator indicating a reliability of the decode data; and an outputting unit that outputs decode data whose reliability indicator is larger than a specified threshold; wherein the reliability calculating unit calculates the reliability indicator of decode data to be decoded, based on a similarity indicator indicating a similarity between the decode data to be decoded and previous decode data whose reliability indicator is larger than the threshold.

Abstract: An apparatus and method for Automatic Repeat reQuest (ARQ) feedback polling in a wireless communication system are provided. The method for ARQ feedback polling includes transmitting at least one ARQ block to a receive end, polling ARQ feedback to the receive end using an extended header, determining if ARQ feedback information is received from the receive end within a lifetime of ARQ feedback, determining success or failure of transmission of the at least one ARQ block through the ARQ feedback information if it is determined that the ARQ feedback information is received within the lifetime of ARQ feedback, and polling ARQ feedback again to the receive end if it is determined that the ARQ feedback information is not received within the lifetime of ARQ feedback.

Abstract: A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer comprises a root port for detecting a failure on a PCIe path, and then for issuing a SMI (System Maintenance Interrupt) to a CPU; and the CPU for, on the receipt of the SMI, executing BIOS to issue, through the root port, a PCIe reset to the PCIe path on which the failure has occurred.

Abstract: An estimating unit includes: an error detecting unit which detects an error among a plurality of frames received from an interface unit of a transmission device; a request sending unit which produces a first frame including a data collection request for requesting data collection upon the error detecting unit detecting the error, and which sends the first frame to the interface unit; an extracting unit which extracts, from the plurality of frames received from the interface unit, a second frame including the error detected by the error detecting unit and a third frame including a reply of the interface unit to the data collection request; and a saving unit in which the second frame extracted by the extracting unit is saved.

Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

Abstract: It is possible to save storage resources. A loss compensation device for compensating a loss in periodical signals when the loss occurs in an arbitrary section of the periodical signals which are divided into predetermined sections and received in time series, includes: a periodical signal storage which stores one or more sections of newly received periodical signals for a predetermined period of time; a loss detector which detects a loss of each section of the periodical signals; and an element periodical signal generator which generates a plurality of element periodical signals for interpolation having different waveforms, in accordance with the periodical signals stored in the periodical signal storage, at time of detection of the loss if the loss is detected by the loss detector. The plurality of element periodical signals generated by the element periodical signal generator are synthesized, and a result of the synthesizing is arranged at the section where the loss in the periodical signals has occurred.

Abstract: In an error control apparatus on a receiving side using a hybrid ARQ which combines an error correcting encoding method and an automatic repeat request method, a buffer stores hard decision result data or soft output data instead of soft decision information in order to reduce a memory capacity of the buffer, and re-encodes the data stored to be provided to a combiner. Alternatively, the number of bits of the data stored in the buffer is restricted or a memory included in a decoder is used as an HARQ buffer.

Abstract: Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries is provided. The method may include one or more of the following steps: attaching a framing header of a frame to a data payload to form a packet, the framing header being placed immediately after the byte stream transport protocol header, the framing header comprising a length field comprising a length of a framing protocol data unit (PDU); and inserting a marker in the packet, the marker pointing backwards to the framing header and being inserted at a preset interval.

Abstract: A method and device include a power pin, a ground pin, and a communications pin. A communications module receives power from the power pin and utilizes an edge counting communication protocol over the communication pin.

Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.

Abstract: A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: An exemplary memory device has at least one memory chip that stores data and error correcting information. An error detecting circuit in the memory chip performs a calculation on the data and error correcting information to obtain error detection information indicating the locations of bit errors in the data. The uncorrected data and the error detection information are output from the memory chip. The uncorrected data and error detection information may also be output from the memory device, or the memory device may include a memory controller chip with an error correcting circuit that uses the error detection information to correct the bit errors and outputs corrected data from the memory device.

Abstract: Methods and apparatuses for using interpolation to associate timestamp values to data received in a data capture and analysis system. An analysis processor receives data representing data transferred in a communications link. The analysis processor also receives timestamp signals. The analysis processor performs an interpolation between at least two timestamp values received and associates results of the interpolation with the data. The analysis processor analyzes the data. A logic device can be coupled to the analysis processor to interleave timestamp signal values with the data and transmit the interleaved data and timestamp signals to the analysis processor.

Abstract: The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first latch means for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch means for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch means for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Thus, a simple and fast detection circuitry can be achieved based on a digital implementation. Furthermore, the charge pump circuit comprises a differential input circuit and control means for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

Abstract: The present invention relates to communication technologies, and provides a decompression method for communication network, in which such fields as an SN are compressed by using an ROHC scheme, so that the compression efficiency is increased. The ROHC uses a WLSB algorithm to compress some fields which change regularly, and decodes by using the decompressor's context through transmitting the low significant bits in these fields. In order to avoid using the inefficient ergodic method and the incorrect direct replacing method in low bits, the present invention selects, based on the mathematical characteristics of the definition of interpretation intervals, to decode by using the method that the low bits is determined by the received k significant bits while the high bits is determined jointly by the local storage information and these k significant bits. Its decoding method can be used for decompression of an SN, a TS and an IP-ID in an ROHC compression.

Abstract: A signal processing apparatus is provided. The signal processing apparatus includes an inner-code decoder, an outer-code decoder, and an error detection unit. The inner-code decoder decodes an input data stream to generate a first output data stream, wherein the input data stream is coded using a concatenated coding scheme including an outer coding and an inner coding. The outer-code decoder decodes the first output data stream to generate a second output data stream. The error detection unit performs an error detection upon the second output data stream to generate an error detection result. The decision logic sets error indication information of the second output data stream according to at least the error detection result.

Abstract: A solid state disk device includes at least one nonvolatile memory and a controller reporting an error code to a host for requesting a previously received data and a command corresponding to the data when a program fail occurs in the nonvolatile memory. The error code is one of a plurality of error codes defined in an interface supported by the controller or a data transmission protocol supported by the nonvolatile memory.

Abstract: To identify data losses in a video sequence transmitted between a server and at least one client over a communication network, the sequence comprising a plurality of video data containers coded using scalable video coding employing a predetermined number of hierarchical levels, the video data containers being transmitted over the network via a series of data transport packets: a process (311) is carried out of detecting losses and of locating the video data affected by those losses, without decoding the video data, by combining information coming from transport packets and information coming from video data container headers. Application for improving decoding on receiving a video sequence.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: An apparatus and method are provided including a point-to-point cluster link configured to receive a data packet and determines a cyclic redundancy code check for the data packet. The point-to-point cluster link is configured to add a cyclic redundancy code check bit to the data packet transmitted to the point-to-point inter-cluster link, to clear the cyclic redundancy code check bit when the data packet is received, and to sample a cyclic redundancy code window to identify a corrupted data packet.

Abstract: A transmitting apparatus included in a communication system that performs message communication using an error detection code with a receiving apparatus, the transmitting apparatus includes a transmission interval determining means that, based on a parameter related to a transmission error non-detection probability of a message per time, a data length of the message, and a code length of the error detection code used for the message, determines a transmission interval for transmitting the message, so that the transmission error non-detection probability of the message satisfies a condition related to a transmission error non-detection probability included in the parameter, wherein the message is transmitted to the receiving apparatus, based on the transmission interval determined by the transmission interval determining means.

Abstract: An automated method for facilitating management of a data processing environment is disclosed. In various embodiments, the method may include facilitating creation of a first memorialization, in digital form, of one or more changes detected on a data processing device of the data processing environment. In various embodiments, the method may further included facilitating comparison of the first memorialization to a second memorialization of one or more in-band changes that should have been made to the data processing device to facilitate detection of one or more out-of-band changes to the data processing device. Other embodiments of the present invention may include, but are not limited to, apparatus adapted to facilitate practice of the above-described method.

Abstract: A method, apparatus and system for improving block error rate performance of a receiver having an iterative decoder in a communication system, the method, apparatus and system includes receiving an encoded frame of data, the encoded frame of data includes a quantity of code blocks where each code block has a corresponding code block size, determining a first maximum number of iterations for each of the code blocks of the encoded frame of data iteratively performing a decoding operation on a first code block until the occurrence of one of (a) the first maximum number of iterations has been reached and (b) the first code block has converged, and determining a second maximum number of iterations for the remaining code blocks of the encoded frame of data based on the number of actual iterations used to decode the first code block.

Abstract: The present invention relates to a method for writing data blocks on a block addressable storage medium, preferably an optical storage medium, using defect management. The invention also relates to the apparatus for writing data blocks on a block addressable storage medium, preferably an optical storage medium, using defect management, with a host unit and a target unit.

Abstract: A wireless device decodes Direct Sequence Spread Spectrum (DSSS) encoded data and identifies data that can not be successfully DSSS decoded (invalid data). A checksum operation uses successfully decoded DSSS data (valid data) to correct the identified invalid corrupted data. The improved error correction leverages the valid and invalid bit information normally provided in DSSS systems to more effectively correct corrupted data bits. The improved error correction increases the processing gain of wireless devices thus increasing the effective wireless range without having to increase transmit power.

Abstract: Method and apparatus for writing data to be stored to a predetermined memory area, the method comprising: reading stored data from the predetermined memory area, the stored data comprising a stored data block and an associated stored error detection value, manipulating, after reading the stored data, at least one of the stored data block and the associated stored error detection value in the predetermined memory area, and writing, after manipulating, the data to be stored to the predetermined memory area.

Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.

Abstract: A method of constructing a puncture sequence includes providing a seed puncture sequence including a plurality of elements. The elements of the seed puncture sequence are based upon non-zero elements of a plurality of columns of a parity-check matrix having a column dimension and a row dimension. In this regard, the parity-check matrix defines an error correction code, and has been constructed based upon a seed parity-check matrix derived from an edge ensemble. After providing the seed puncture sequence, a variable node-puncture sequence can be constructed based thereupon. The variable node-puncture sequence, then, corresponds to a puncture sequence configured for processing an error correction code.

Abstract: A communication apparatus complying with the ITU-T Recommendations v.34 and control method thereof are disclosed. The communication apparatus predicts a timing at which reception of image data in an amount of the error frames sent from another communication device is terminated, based on the number of error frames which are not normally received when receiving image data from the another communication device through a primary channel. The communication apparatus controls to shift from the primary channel to a control channel in accordance with the predicted timing when the image data is received in an amount of the error frames on the primary channel from the another communication device.

Abstract: A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: A decoder for decoding low-density parity-check codes includes a first calculator that calculates ??rRml, for each parity check equation, at iteration i?1. A second calculator calculates ??rQ?m, for each parity check equation, at iteration i. ??rQ?m represents information from bit node I to equation node m, one for each connection. ??rRml represents information from equation node m to bit node I, one for each connection. The first calculator is responsive to the second calculator.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures.

Abstract: A method and system for detecting radio link (RL) failures between a wireless transmit/receive unit (WTRU) and a Node-B are disclosed. When signaling radio bearers (SRBs) are supported by high speed uplink packet access (HSUPA), an RL failure is recognized based on detection of improper operation of at least one of an absolute grant channel (AGCH), a relative grant channel (RGCH), a hybrid-automatic repeat request (H-ARQ) information channel (HICH), an enhanced uplink dedicated physical control channel (E-DPCCH) and an enhanced uplink dedicated physical data channel (E-DPDCH). When SRBs are supported by high speed downlink packet access (HSDPA), an RL failure is recognized based on detection of improper operation of at least one of a high speed shared control channel (HS-SCCH), a high speed physical downlink shared channel (HS-PDSCH) and a high speed dedicated physical control channel (HS-DPCCH).

Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Abstract: A method and apparatus for Convolutional Turbo Coding (CTC), and an apparatus for a turbo encoder are provided. The method for CTC includes the steps of encoding information bits A and B using a constituent encoder, and outputting parity sequences Y1 and W1, interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y2 and W2, interleaving the information bits A and B, the parity sequences Y1 and W1 and the parity sequences Y2 and W2, respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y1and W1, and a bit group constituted of the sequences Y2 and W2 are alternately mapped to bits of constellation points with high reliability and low reliability and puncturing the interleaving result to obtain the encoded bit sequences.

Abstract: Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: In a wireless communications network, a wireless device may examine the received signal to determine the strength of the received signal, and also determine the level of interference and noise. If a retransmission is needed due to a message being incorrectly received, these factors may then be processed to estimate whether the probable cause of poor reception is interference from a neighboring network. If such interference is the likely cause, the retransmission may be changed to a different time and/or to different frequencies in a subsequent frame, so that the interference from the neighboring network is less likely to reoccur.

Abstract: A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.

Abstract: An error detection system and methodology where the undesirable consequence of encapsulation (additional latency or delay) for virtualization applications such as i-PCI or iSCSI is minimized for the vast majority of data transactions. Cyclic Redundancy Checks (CRCs) and checksums are executed simultaneously in parallel, immediately on reception of a data packet regardless of the relative processing order in relation to the OSI model.

Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

Abstract: In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

Abstract: Method and apparatus to provide media content are presented. In a particular embodiment, a method of providing content includes receiving a request of particular content at a computing device, where the request is addressed to a unicast source, and determining whether the particular content is available, at least in part, via at least one multicast group accessible by the computing device. The method also includes, when the particular content is available, at least in part, via the at least one multicast group, sending a group join request from the computing device to a network element of a multicast network to join the at least one multicast group.

Abstract: Content information is multicast via a data network to a plurality of receivers, using data packets in a transport stream. The content information is encapsulated according to a container format standard that allows an optional field in a packet header. Each data packet forms a payload of a datagram in a connectionless communication protocol. The optional field in each data packet is used to carry an identifier for identifying the data packet in a pre-determined sequence of the data packets. The use of the optional field enables packet loss detection at the receiver.