Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: Various embodiments of the present invention provide systems and methods for LDPC encoding and decoding. For example, a system for performing LDPC encoding and decoding is disclosed that includes a joint LDPC encoder/decoder. The joint LDPC encoder/decoder includes both an LDPC decoder and an LDPC encoder that each utilize a common LDPC decoder circuit to perform the respective functions of encoding and decoding.

Abstract: A signal processing circuit includes a plurality of processing-circuit modules and a logic control circuit. The plurality of processing-circuit modules is configured to process an electrical signal. The plurality of processing-circuit modules has at least one processing parameter that is adaptively adjusted based on the electrical signal. The logic control circuit is configured to receive signals from the plurality of processing-circuit modules, validate the processing based on the received signals, and control a storage circuit to sample and store a value of the processing parameter when the processing is validated. Further, the logic control circuit is configured to control the storage circuit to maintain the value of processing parameter when the processing fails validation, and to control the storage circuit to recover the processing parameter in the plurality of processing-circuit modules to the stored value when the plurality of processing-circuit modules is disturbed by a defect.

Abstract: A layout error detection method includes the following steps, reading a layout file, in which the layout file includes a plurality of elements and a plurality of coordinates, and each element is corresponding to one coordinate; reading a record table, in which the record table includes an identification column, a coordinate column, and a flag column; scanning the layout file to obtain an error detection result, in which the error detection result is corresponding to an identification data and a coordinate data; searching the identification column of the record table to judge whether the identification column has the same identifier according to the identification data, and when a judgment result is false, writing the identification data and the coordinate data of the error detection result, setting a flag value to logic 0, and marking the error detection result; and scanning the layout file repeatedly until all the elements are scanned.

Abstract: A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique data word bid and an adjacent data word bit to provide a first output bit and a second logic circuit connected to receive the first output bit and a different adjacent bit of the data word to provide a second output bit representing a corrected value of the unique bit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples.

Abstract: Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.

Abstract: Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and systems for simplified error recovery in a SAS device. A SAS device (e.g., a SAS/SSP target device such as a storage device) enhanced in accordance with features and aspects hereof NAKs a received frame that has an error and then NAKS all subsequently received frames, regardless of whether received with or without error, until the connection is closed. The second SAS device (e.g., a SAS/SSP initiator) then performs required error recovery by re-establishing a connection and re-transmitting all previously NAKed frames. The enhanced SAS thereby simplifies logic for error recovery.

Abstract: A novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system.

Abstract: A new and useful method is provided, of organizing and automating a hardware independent disk imaging deployment process, e.g. for Windows PC and other Server operating systems, that uses a server that both has a database of computer PC hardware data that can be electronically analyzed. a. electronically analyzing the database of computers, and grouping the computers into Compatibility Classes, each compatibility class having like model systems that also have been analyzed to have exactly and only the same hardware in common, thus accounting for hardware variance within model groups, b. electronically identifying candidate computers that will serve as collection targets for gathering (remote collection performed over the network) of device drivers for each compatibility class group, c. electronically extracting device drivers and other hardware related data from a selected candidate computer, and d. electronically configuring deployment jobs that will first perform a disk image of the computer.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A coding circuit that includes a buffer manager and a coding block is provided for generating product codes for parity checks as error correction code and adding the product codes to digital data to be recorded in a record medium.

Abstract: A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a judging unit that judges whether length of the candidate path is longer than a predetermined length; and a determining unit that determines whether to determine the candidate path as a target path to be subjected to a fault simulation based on a result of judgment.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived from a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.

Abstract: A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.

Abstract: Aspects of a method and system for feedback of decoded data characteristics to decoder in stored data access and decoding operations to assist in additional decoding operations are presented. Aspects of the system may include a decoder that enables decoding of a portion of encoded data. A processor may enable generation of at least one hypothesis based on the decoded portion of encoded data and/or redundancy information associated with at least the decoded portion of the encoded data. The decoder may enable generation of one or more subsequent portions of decoded data based on the generated at least one hypothesis.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(v)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A determination unit of a portable radiographic image conversion device determines, when image information has been generated by an electronic circuit, whether or not a state of connection between a connection terminal and a communication cable is abnormal. Then, when it has been determined by the determination unit that the state of connection is not abnormal, a control unit causes the image information that has been generated to be transmitted by a communication unit, and, when it has been determined by the determination unit that the state of connection is abnormal, the control unit causes the image information that has been generated to be stored in a memory.

Abstract: Systems and methods for measuring the effectiveness of a workload predictor operative on a mobile device are disclosed. A load manager includes a workload predictor, a sensor, an error generator and a controller. The workload predictor generates an estimate of the workload on a processor core operative on the mobile device. The sensor generates a measure of the actual workload on the processor core. The error generator receives the estimate of the workload and the measure of the actual workload on the processor core and generates an error signal. The controller receives the error signal and determines the effectiveness of the workload predictor as a function of the error signal over time.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plurality of ways, each with one or more information fields. Cache memory control circuitry has a control register for controlling allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information. The cache memory control circuitry further individually controls a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register.

Abstract: An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.

Abstract: An exemplary method includes switching, by a media content access subsystem, from a program stream to an advertisement stream in response to a switching instruction received by the media content access subsystem, detecting, by the media content access subsystem, a predetermined number of markers included within the advertisement stream, the predetermined number of markers indicative of an error associated with the advertisement stream, and switching, by the media content access subsystem, from the advertisement stream to another media content stream in response to the detecting of the predetermined number of markers. Corresponding methods and systems are also disclosed.

Abstract: A method and system for autonomic Information Management System (IMS) mainframe database pointer error diagnostic data extraction. A receiving module may receive a database name and an error detection time. An error detection module may locate database pointer errors on the failed IMS database. A list module may generate an Image Copy (IC) list corresponding to the failed database. A code generation module may generate Job Control Language (JCL) code for the selected entries in the IC list. An execution module executes the JCL code which operates a pointer checker utility on each clean IC. A log list module locates log data sets recorded in the time between the error and when the error was detected and an extraction module extracts an evaluation log list which comprises evaluation log data sets.

Abstract: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication partner device, and a checker configured to compare the check value with the verification value and to provide a fault indication signal as a function of the comparison.

Abstract: A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the contoller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.

Abstract: Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and impulse noise protection parameters are adjusted according to the monitored impulse noise without interrupting communication service.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: A client device or other processing device separates a file into blocks and distributes the blocks across multiple servers for storage. In one aspect, subsets of the blocks are allocated to respective primary servers, a code of a first type is applied to the subsets of the blocks to expand the subsets by generating one or more additional blocks for each subset, and the expanded subsets of the blocks are stored on the respective primary servers. A code of a second type is applied to groups of blocks each including one block from each of the expanded subsets to expand the groups by generating one or more additional blocks for each group, and the one or more additional blocks for each expanded group are stored on respective secondary servers. The first and second codes are advantageously configured to provide security against an adversary that is able to corrupt all of the servers over multiple periods of time but fewer than all of the servers within any particular one of the periods of time.

Abstract: Various methods for implementing delta data storage, for example, within a hybrid automatic repeat request (HARQ) buffer, are provided. One example method includes receiving a redundancy version including a plurality of redundancy version bits and soft combining the redundancy version bits with corresponding buffered bits to generate corresponding soft combined bits. The example method further includes comparing the soft combined bits with the corresponding buffered bits to identify changed bits and unchanged bits, storing the changed bits in a buffer to thereby replace the buffered bits that correspond to the changed bits. Similar example apparatuses are also provided.

Abstract: A memory system including a primary memory storage partition, a secondary memory storage partition, and a memory controller that is connected to read and write to the primary memory storage partition and detect a permanent bit error at an address associated with the primary memory storage partition. In response to a detected permanent bit error, the memory controller stores data from the address associated with the permanent bit error to an address associated with the secondary memory storage partition.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.

Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: Methods and apparatus for encoding data in a communication network. In an aspect, a method is provided for coding data. The method includes generating one or more permutations of the data, determining weights associated with each permutation, calculating one or more code packets from each permutation based on the associated weights, and multiplexing the data and the one or more code packets into a code packet stream. In an aspect, an apparatus is provided for coding data. The apparatus includes permutation logic configured to generate one or more permutations of the data, and weight logic configured to determine weights associated with each permutation. The apparatus also includes processing logic configured to calculate one or more code packets from each permutation based on the associated weights, and a multiplexer configured to multiplex the data and the one or more code packets into a code packet stream.

Abstract: The invention relates to a method of designing a system. The system includes an application having software components and an architecture having hardware components on which the application is run. The system has to satisfy at least one functional and one non-functional requirement. The functional analysis step (11) obtains a breakdown of the functional need relating to the application. A step defines the architecture (12). A step for designs hardware components (13) according to the architecture. A step design software components (14) based on the breakdown of the functional need. A step for integrates the software components in the hardware components (15). A step validates the functional requirements of the system (16). A step validates the non-functional requirement of the system (17). An upstream step (21) validates the non-functional requirement of the system, preceding the steps for designing hardware components (13) and software components (14).

Abstract: A vital-signs device in a patient monitoring system is disclosed. The patch includes a housing configured to be attached to the skin of a patient. The housing contain monitoring circuitry configured to acquire and store measurements of vital signs of the patient, a wireless transmitter configured to transmit signals to another device, a wireless receiver configured to receive signals from the other device; and a processor operably connected to the monitoring circuitry, transmitter, and receiver. Upon receipt of an upload signal from the other device, the processor is configured to send a message to the other device via the transmitter. The message packet structure includes a data payload of variable size, a header containing transmit and route information and data payload length, and a data integrity check value.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

Abstract: According to one embodiment, a fail analysis system performs mesh division of a physical fail bit map and stores fail bit map image data of a part bit fail region in a first image data storage region while classifying the fail bit map image data in each contraction ratio, in each chip, and in each layer. The fail analysis system also stores the fail bit map image data in a second image data storage region while classifying the fail bit map image data in each kind of a fail mode, in each contraction ratio, in each chip, and in each layer. Further, based on an instruction of a display format and/or a display region from a user, the fail analysis system extracts the pieces of fail bit map image data from the first image data storage region or second image data storage region to combine the pieces of fail bit map image data, and displays the combined fail bit map image data on a display unit.

Abstract: In an encoded stream decoding device, a storage amount checking circuit confirms that a sufficient amount of stream has been stored in a buffer circuit. Thereafter, a control circuit starts repeatedly outputting a control signal to a decoding circuit to instruct the decoding circuit to perform a variable-length decoding process. If, by iterating the decoding process, the total amount of a consumed stream in the buffer circuit 11 is caused to be higher than or equal to a threshold set in a threshold setting circuit, a disabling circuit generates a decoding disable signal having a value of “1,” and outputs the decoding disable signal to the control circuit. When receiving the decoding disable signal, the control circuit outputs, to the decoding circuit, a control signal for instructing to stop the decoding process, so that the decoding circuit stops the decoding process.

Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.