Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: The invention provides methods and systems for terminating an iterative decoding process of a Forward Error Correction block (FEC). The iterative decoding process of the FEC block is terminated upon determining that the FEC block cannot be decoded successfully. A method comprises calculating a metric based on one or more Log Likelihood Ratios (LLRs) corresponding to a first number of iterations of the iterative decoding process of the FEC block. The method further comprises, formulating one or more stopping criteria for the iterative decoding process based on a variation pattern of the metric over a second predetermined number of iterations of the iterative decoding process. The second predetermined number of iterations is a subset of the first number of iterations. Moreover, the method comprises terminating the iterative decoding process of the FEC block based on the one or more stopping criteria.

Abstract: An encoding circuit comprising: a memory unit; an EDC generating circuit, a scrambler, a header generator, an EDC correcting circuit and an decoder. The EDC generating circuit is used for generating a first EDC according to at least one main data, and for storing the first EDC to the memory unit. The scrambler is used for generating a scrambled main data according to the main data, and for storing the scrambled main data to the memory unit. The header generator is used for generating a header according to header information. The EDC correcting circuit is used for reading the first EDC from the memory unit and for correcting the first EDC according to the header to generate a second EDC. The encoder is used for encoding optical data according to the second EDC and the scrambled main data.

Abstract: An error detection device includes a control unit configured to identify two links that connects a relay communication device to two communication devices as a link pair, identify, from pluralities of inspection devices under the respective two links, a number of inspection devices corresponding to the number N of links where communication errors simultaneously occur (N is an integer of 1 or more) plus 1, determine (N+1) number of inspection flows between the (N+1) number of inspection device pairs, and generate inspection coverage information that includes the determined inspection flows. The error detection device includes a storage unit that stores the inspection coverage information, and a communication unit that sends the inspection coverage information to one device of the inspection device pairs.

Abstract: Apparatuses, computer program products, and methods for authenticating digital signals are provided in which copies of a watermark are extracted from a digital signal with at least some of the copies potentially having distorted values. The original values of the watermark may be reconstructed exclusively based on the extracted copies of the watermark. The method includes estimating one or more bit error rates without training or reference information. The bit error rates are modeled as being equivalent to transmitting the copies through binary symmetric channels. The estimated bit error rates and the distorted values are combined to reconstruct the original values of the watermark. The reconstructed watermark may be compared to an original watermark for authenticating the received digital signal. Also, the estimated bit error rates may be compared to a random sequence of bits for verifying the presence of the watermark without knowing the original values of the watermark.

Abstract: Disclosed are exemplary remote programming systems, software and methods for use in remotely programming field devices, such as engines, power generators, controllers, and data sensors, and the like. A (wired or wireless) communications link interconnects a processor and a remotely located server. The processor comprises a program memory and firmware that is loaded into the program memory. The processor is coupled to a nonvolatile memory device and apparatus for communicating over the communications link. The remotely located server contains a source code file comprising updated firmware for the processor. Software or a method is provided that initiates a process wherein the updated firmware is transferred from the server to the processor and the updated firmware is stored in the nonvolatile memory.

Abstract: Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: An improved error correction apparatus and method for a digital device are provided. An error correction apparatus includes at least one client module outputting an error detection signal, if an error is detected; and a controller for analyzing the error and controlling the client module to correct the error, if an error detection signal is received. An error correction apparatus and method of the present invention is provided with shadow registers or CRC registers for quickly detecting errors of status registers of a client module, whereby an error of the client module can be quickly detected and corrected.

Abstract: To perform erasure detection for an intermittently active transport channel with unknown format, a receiver determines an energy metric and a symbol error rate (SER) for a received block with CRC failure. The receiver computes uncorrelated random variables u and v for the received block based on the energy metric and SER, the estimated means and standard deviations of the energy metric and SER, and a correlation coefficient indicative of the correlation between the energy metric and SER. The receiver then evaluates the uncorrelated random variables u and v based on at least one decision criterion and declares the received block to be an erased block or a DTX block based on the result of the evaluation. The decision criterion may be defined based on a target probability of false alarm and adjusted based on another metric, such as a zero state bit, for the received block.

Abstract: Embodiments of methods and apparatus for reducing electromagnetic interference of a received signal are disclosed. One method includes receiving a signal over at least two conductors, extracting a common-mode signal from the at least two conductors, processing the common-mode signal, and reducing electromagnetic interference of the received signal by summing the processed common-mode signal with the received signal.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: In a method for transmitting data of various traffic types an xDSL modem is utilized. Detectors are used to detect the traffic types of the data which are to be transmitted and the detected traffic types are taken as a basis for dynamically adjusting a data transmission rate for the xDSL modem.

Abstract: Methods for detecting and correcting data errors in an RF data link include identifying valid data frames and corrupted data frames by measuring a data corruption level for each transmitted data frame, comparing the measured data corruption level for each corrupted data frame to a data corruption threshold, reconstructing the corrupted data frames having a data corruption level below the data corruption threshold, reconstructing the data block using data from valid and reconstructed data frames, and/or verifying the data in the reconstructed data block.

Abstract: Subject matter disclosed herein relates to a memory device and a method of operating same.

Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.

Abstract: Provided are methods and systems of selectively decoding optical data read from an optical storage medium based on a checksum algorithm technique. In one embodiment, optical data is converted into a data stream and buffered, and the checksum algorithm is applied to the data stream. If the calculated checksum matches an encoded checksum of the data stream, the data stream may be output without requiring further decoding. If the calculated checksum does not match the encoded checksum, the buffered data stream may be decoded to produce a corrected data stream, and the checksum algorithm may be applied to the corrected data stream. In some embodiments, the optical data may be re-read if the corrected data stream does not pass the checksum test, and the data stream obtained from the re-reading may be combined with the buffered data stream for further decoding.

Abstract: A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

Abstract: The present invention discloses a method for recovering a lost data unit, the method including: partitioning data to be transmitted into one or more data units, sorting the data units according to importance levels of the data units, and determining a check rule for the one or more data units, performing, by a transmitting end, a calculation on the sorted data units according to a predetermined algorithm depending on the check rule, to generate one or more corresponding check units; transmitting, by the transmitting end, the one or more data units to a receiving end in a sorted order, and transmitting the corresponding check units to the receiving end; recovering, by the receiving end, a lost data unit according to the receiving data units and check units as well as the check rule. With the method, the loss-preventative capability of the data units may be improved.

Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal.

Abstract: A communication device configured for transmission of Acknowledgement and Negative Acknowledgement (ACK/NACK) is described. The communication device includes a processor and instructions stored in memory. The communication device determines one or more thresholds based on a size of one or more code words and generates a compressed ACK/NACK sequence. The compressed ACK/NACK sequence identifies one or more correctly received code words and one or more incorrectly received code words if the number of incorrectly received code words is less than the threshold. If the number of incorrectly received code words is greater than the threshold, the compressed ACK/NACK sequence indicates that all of the one or more code words were incorrectly received.

Abstract: According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting each IIR filter to actual noise conditions: a variance hank storing a plurality of prediction error variance values; and a data-dependent prediction error variance computation unit which updates the plurality of prediction error variance values. The maximum-likelihood sequence detector includes a metric computation unit that employs the plurality of IIR filters in the filter bank and the plurality of prediction error variances in the variance bank to adaptively compute detector branch metrics.

Abstract: In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Abstract: A device (1) for safe data transmission to railway beacons has a first and a second circuit section (1a, 1b) independent of and galvanically separate from each other, and each having: a microprocessor (6a, 6b) selection stage (2a, 2b) receiving information signals relative to the status of a portion of a railway line, and generating at least one telegram for transmission to a beacon; and a control stage (3a, 3b) comparing the telegrams generated by the first and second circuit section (1a, 1b) for enabling/disabling data transmission to the beacon. The first circuit section (1a) also has a transmission enabling stage (4, 5, 17), which allows transmission to the beacon of the telegram generated by the first circuit section (1a), in the event the comparison performed by the control stage (3a, 3b) is successful.

Abstract: A transmitting apparatus generates a first bit stream from a second bit stream by encoding at least a portion of the bits from the second bit stream, generates a code for the second bit stream, and attaches the code to the first bit stream for transmission to a receiving apparatus. A receiving apparatus receive from a transmitting apparatus a first bit stream with a code, generates a second bit stream from the first bit stream by decoding at least a portion of the bits from the first bit stream, computes the code for the second bit stream, and compares the computed code with the code from the first bit stream.

Abstract: An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).

Abstract: A control circuit of a chip 61 includes a data reception circuit unit 611 that receives data transmitted by a data transmission circuit of another chip, an error information extraction unit 613 that detects error information of the received data, and a data transmission circuit unit 617 that attaches, when the error information extraction unit 613 detected error information, the detected error information to the received data, and transmits the data to which the error information is attached, to a data reception circuit of another chip.

Abstract: A regenerative relay method includes the steps of: i) calculating an error rate of a transmission path between the first half apparatus and a main apparatus; ii) calculating an error rate of a transmission path between the main apparatus and the latter apparatus; iii) adding the error rates; iv) selecting the error correction code and data before the error is corrected in the main apparatus so as to be supplied to the latter apparatus if the added error rates are lower than a designated error correction threshold; and v) selecting data after the error is corrected in the main apparatus and the other error correction code generated from the data so as to be supplied to the latter apparatus if the added error rates are higher than the designated error correction threshold.

Abstract: A bit adding part acquires RSSI as measured by an RSSI measuring part, and adds “1” to each bit of protected audio data of an audio vocoder, if the acquired RSSI is smaller than a predetermined threshold value. If the acquired RSSI is equal to or greater than the predetermined threshold value, the bit adding part adds the bits of additional data to the respective bits of the protected data of the audio vocoder. A frame recovery part separates upper and lower order bits of deinterleaved data, and determines, based on CRC, whether eight data parts as obtained by combining the lower order bits as separated are valid. If so, the frame recovery part combines the eight data parts as the additional data to recovery additional information. In this way, additional data can be efficiently transmitted, while error correction being performed in accordance with communication environment.

Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.

Abstract: A communication system that provides fast and reliable communications. The system is suitable for use in connection with wireless computing devices in which transmission errors may occur because of channel conditions, such as interference. Channel conditions causing transmission errors may be bursty and transient such that the errors temporarily overwhelm an error control code. By combining data received for multiple transmission attempts of a packet that fail error checking or that pass error checking with low reliability, a reliable representation of the packet may be quickly constructed. Though, combining may be omitted when a transmission attempt is received that passes error checking with high reliability.

Abstract: A communicating unit used in an X-ray image pickup apparatus in this invention has an error detecting function to detect communication errors, and an FIFO for temporarily storing data received from a control and image processing apparatus, which is an external apparatus, by a receiving function of a communication control unit. Only when no error is detected within a predetermined period before and after receipt of data, by the receiving function of the communication control unit, from the control and image processing apparatus, a transmitting function of the communication control unit performs controls to transmit and write the data received and temporarily stored in the FIFO to an external portion. Thus, when a cable is plugged or unplugged or the control and image processing apparatus which is an external apparatus is rebooted, the error detecting function detects this as a communication error. In such cases also, an inadvertent writing of the data can be prevented.

Abstract: Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors even when those errors are not confined to a single block. Disclosed techniques permit a reduction in the amount of forward error correction used. For example, in general, to correct t errors, a linear cyclic error correction code requires a Hamming distance of at least 1+(2t)[wt(s(x))]. Embodiments of the invention allow correcting the multiplied errors with a Hamming distance of only 1+(t)(1+wt(s(x))) over the block size n, wherein wt(s(x)) is the weight of the scrambler polynomial s(x).

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: A system for decoding coded data printed in ink on a surface is provided. The coded data has a registration structure which has at least two clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track. The two alignment lines are indicative of the position of the respective clock track. The system has a decoder for determining, using an alignment phase-locked loop (PLL), a position of the alignment lines for a respective clock track, determining, using the position of the alignment lines, the position of each respective track, and updating the alignment PLL.

Abstract: Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A digital broadcasting transmission system processes dual transport stream (TS) including multi turbo streams. The digital broadcasting transmission system includes a turbo processor to detect a turbo stream from a dual transport stream (TS) which includes a multiplexed normal stream and a turbo stream, encoding the detected turbo stream and stuffing the encoded turbo stream into the dual TS; and a transmitter to trellis-encode the processed dual TS, and to output the resultant stream, wherein the turbo processor encodes the turbo stream using a plurality of turbo processors. Accordingly, a plurality of turbo streams may be processed in parallel.

Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.

Abstract: An approach is provided for efficient retransmissions by allocating a transmission resource for transmitting data and allocating a retransmission resource for retransmitting the data according to a transmission scheme that specifies relationship between the transmitted data and the retransmitted data for providing communication over a radio network.

Abstract: A system and method for providing fault detection capability is provided which comprises a first node (2). The first node (2) comprises a first processing subsystem (5) generating data (14) to be transmitted. The first node (2) has a fault supervisor unit (13) adapted to gather and process fault indications arising in the first node (2). The first processing subsystem (5) and the fault supervisor unit are both integrated in the first node (2). The first node (2) is structured such that, when no fault indications are detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a first key (15) as a validity key, and, when at least one fault indication is detected by the fault supervisor unit (13), the fault supervisor unit (13) provides a second key (16) as the validity key, and the data (14) to be transmitted are encrypted by overlaying the respective validity key (15; 16) on the data.

Abstract: When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data.

Abstract: An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.

Abstract: A transmitter includes a plurality of encoders configured to receive source bit streams from m information sources, each of the plurality encoders including identical (n,k) low-density parity check (LDPC) codes of code rate r=k/n, where k is a number of information bits and n is codeword length. An interleaver is configured to collect m row-wise codewords from the plurality of encoders, and a mapper is configured to receive m bits at a time column-wise from the interleaver and to determine an M-ary signal constellation point. A modulator is configured to modulate a light source in accordance with the output of the mapper at a transmission rate Rs/r (Rs—the symbol rate, r—-the code rate). A receiver and transmission and receiving methods are also disclosed.

Abstract: An electronic device is described which receives data from a transmitting device via a communications channel. The electronic device comprises digital processing circuitry arranged to process the data received via the communications channel to generate output data, error detection circuitry arranged to detect errors in the output data, and monitoring circuitry arranged to monitor the quality of digital processing conducted by the digital processing circuitry and generate digital performance data indicative of the monitored quality of digital processing. The electronic device also comprises control circuitry responsive to error information comprising errors detected by the error detection circuitry and the performance data generated by the monitoring circuitry to modify the operation of one or both of the transmitting device and the electronic device.

Abstract: A solution for managing one or more problems in a software component is provided. The solution includes generating an identifier for each problem based on a call stack for the execution of the software component when the problem occurs. The identifier and a text message for the problem can be displayed to a user. The user can use the identifier to obtain information on the problem and/or one or more updates that address the problem. In one embodiment, the identifier comprises a hash value of the call stack, which is likely to result in a unique value for each possible call stack. In this manner, the identifier will likely provide a unique identifier for each problem.

Abstract: A method and system of wireless communication is provided which involves inputting information bits, wherein certain bits have higher importance level than other bits, and applying unequal protection to the bits at different importance levels. As such, important bits are provided with more protection for transmission and error recovery. Applying unequal protection involves using skewed constellations such that more important bits are provided with more error recovery protection.