Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of performing the contention-free memory mapping is provided to ensure that any one turbo decoder (of a group of parallel arranged turbo decoders) accesses only memory (of a group of parallel arranged memories) at any given time. In doing so, access conflicts between the turbo decoders and the memories are avoided.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.

Abstract: When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.

Abstract: Elements of a coding table which are error-free are found at S2. At S3, corresponding elements in an erasure information table are completed, indicating that the elements in the coding array are correct. A counter is initialized at Nmax, which is the maximum number of errors that can be corrected, at S4. At S5, the row of the erasure information table is scanned beginning from the first parity column for empty elements. Each empty parity date element of the erasure information table row is marked as incorrect at S7 For each such element, the counter is decremented at S8. At S9, the elements of the erasure information table are scanned from the first column of the application data and zero padding section for empty elements. At step S11, an empty element is marked as incorrect. At step S12, the counter is then decremented. It is determined at step S13 whether or not the counter is equal to zero.

Abstract: A semiconductor memory apparatus capable of detecting an error in data input/output includes a memory cell block including a plurality of memory cells. A data input unit receives data from outside the semiconductor memory apparatus and performs predetermined signal processing to record the received data in the memory cell block. A first global data line is connected between the data input unit and the memory cell block. A data output unit receives data from the memory cell block and performs predetermined signal processing to output the received data to the outside of the semiconductor memory apparatus. A second global data line is connected between the memory cell block and the data output unit. A multiplexer selectively outputs data from the first or second global data line in response to a control signal.

Abstract: A system, method, and apparatus for data communication including a transmitter and first processor for data transmission in at least two states of operation, a receiver, memory device, and second processor providing at least two states of operation for processing the data. In a ready state, received data is ready for processing upon reception. In an active state, received data is converted into a different format prior to processing. The transmitter transmits first data associated with the ready state, a first transition command associated with transitioning from the ready state to the active state, second data associated with the active state, and a second transition command associated with transitioning from the active state to the ready state. The second processor processes the first data in the ready state, transitions to the active state, processes the second data in the active state, and transitions to the ready state.

Abstract: A user interface component receives an input error message. A query enhancer component derives error messages from the input error messages using error pattern(s) representative of the input error message and error sub-pattern(s) of the error pattern(s). A result aggregator component inputs each error message to search engines, receives search results, aggregates the search results, and provides the search results to the user interface. The enhancer component may include a pattern composer component to locate error patterns representative of the input error message, and a sub-pattern generator component to derive error sub-patterns from the error patterns. The aggregator component may determine whether the search results are in agreement with a predetermined criterion. If not, the aggregator component may request the enhancer component to provide additional error messages to input to the search engines.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.

Abstract: A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.

Abstract: A method and apparatus are capable of masking a signal loss condition. According to an exemplary embodiment, the method includes steps of receiving a signal, detecting a period of loss of the signal, and enabling a received portion of the signal to be reproduced continuously and causing a portion of the signal lost during the period to be skipped.

Abstract: A Semiconductor memory apparatus includes: a data latch driving unit configured to latch and drive data and to transfer the driven data via a first data bus, based on a detection start signal and a detection stop signal; a data masking latch driving unit configured to latch and drive a data masking signal and to transfer the driven data masking signal via a second data bus, based on the detection start signal and the detection stop signal; an error detection unit configured to perform an error detection operation on the data and the data masking signal to generate an error detection signal, based on the detection start signal and the detection stop signal; an error detection driving unit configured to drive the error detection signal and to transfer the driven error detection signal via a third data bus; a write control unit configured to generate a write control signal based on the data masking signal transferred via the second data bus and the error detection signal transferred via the third data bus; and a

Abstract: An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer (502) is disclosed for verifying a CRC value (506) and a sequence number (508) received within the packet. A transaction layer (504) is disclosed for receiving the packet from the data link layer and for processing thereof. The transaction layer (504) processes (512) at least some of the packet data in parallel to the data link layer (502).

Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_OK primitive (reception with no error primitive) and sets a error flag to report to the application layer of the receiver to eliminate the interference.

Abstract: An efficient method and system for detecting frame slip in an inband signalling block in pulse code modulation. The effect of frame slip on the inband signalling block is that the bits following the frame slip are transferred from the signalling block into an adjacent block. The octet slip is detected by searching an error bit in a signalling block by comparing it to a sample block. If an error bit is found, an error count for the adjacent block starting from the error bit is calculated. If the error count is more than one, a second error bit of the signalling block is searched (26) and bits of the adjacent block after second error bit are verified (27). If bits of the adjacent block after the second error bit are not correct, the octet slip cannot be assumed (29). Otherwise the octet slip can be assumed by analyzing error count and error bits.

Abstract: A method of transmits a data block of a type from a transmitting device (for example a transmitting network node) to a receiving device (for example a receiving network node), in particular during a temporary block flow. A transmitting device is capable of receiving at least two different types of positive/negative acknowledgements for data blocks of said type from said receiving device and the reaction of the transmitting device to the positive/negative acknowledgements depends on the type of the said received positive/negative acknowledgement.

Abstract: Provided is a method for retransmission in a mobile communication system; and, more particularly, to an integrated operation method of Automatic Retransmission Request (ARQ) and Hybrid Automatic Retransmission Request (HARQ) in a mobile communication system. The method includes the steps of: a) shifting to a 2nd layer waiting status upon receipt of 1st layer reception failure information in a sending status that a fragment block of 2nd layer transmission data is transmitted to the a receiver according to the predetermined retransmission number; b) shifting to a 1st layer receiving status upon receipt of 1st layer reception success information in the sending status; and c) shifting to the transmission completion status upon receipt of the 2nd layer reception success information in the sending status.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: The invention provides a receiver associated with a body, e.g., located inside or within close proximity to a body, configured to receive and decode a signal from an in vivo transmitter which located inside the body. Signal receivers of the invention provide for accurate signal decoding of a low-level signal, even in the presence of significant noise, using a small-scale chip, e.g., where the chip consumes very low power. Also provided are systems that include the receivers, as well as methods of using the same.

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

Abstract: A data protection method of a storage device, applied in a computer having a storage device, is provided. The storage device is consisted of a plurality of blocks. The method includes the following steps. When a data containing a plurality of bit data is stored in the storage device in the computer, the stored bit data is checked bit by bit. If an incorrect bit data is checked, the data in the block containing the incorrect bit data is backed up to a reserved block. Therefore, the memory capacity of the storage device is not occupied while backing up data, so as to improve the reliability of the computer.

Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

Abstract: A system for transmission of signals between modules wherein, for example, it is possible to transmit reliably, between modules, information relating to, for example, the actuation of safety devices. A transmission module for transmitting a pulse signal of a specific period, which indicates the existence of information, generates, in time division, pulse signals by a plurality of signal generating units that are provided in parallel, and then combines these pulse signals into a single time series pulse signal. Then an attempt is made to output this pulse signal towards a receiving-side module through a relay for controlling the output, and the signals appearing at a normally-open terminal and at a normally-closed terminal of the relay are monitored to determine whether or not there is a failure, where the generation of the pulse signal is stopped when a failure is detected.

Abstract: The invention relates to a method of processing bit errors in a bit frame emanating from a digital audio coder, comprising a step of receiving a current bit frame liable to comprise bit errors. According to the invention, the bit frame comprises sensitive bits to be protected which are catalogued in at least one category according to the type of parameter that they code and the method furthermore comprises the steps of receiving protection bits, of reading the sensitive bits received in the current bit frame, the number of sensitive bits being lower than the number of bits of the bit frame, of detecting bit errors as a function of said protection bits received and of said sensitive bits received and in the event of detecting at least one erroneous bit in said bit frame, of modifying the current bit frame before decoding, as a function of the category in which the erroneous bit is catalogued.

Abstract: A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. The error correction code verifies whether this initial comparison is correct and provides a confirmed cache hit or miss signal. The tag data is compared with the request tag to determine a provisional cache hit or miss, and in parallel, the error correction code is evaluated. If the error code evaluation indicates errors in the tag data, a provisional cache hit is converted into a cache miss if errors are responsible for a false match. If the error code evaluation identifies the locations of errors, a provisional cache miss is converted into a cache hit if the errors are responsible for the mismatch.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: A method for transmitting a data transfer block, the data transfer block comprising at least one data segment having a predetermined number of one or more data units, to be identified using validity information, and a header segment, the method including the following steps: a) writing a data unit into a first area of an output register predetermined for the data segment, from which the buffered data transfer block is transmitted via a bus system at a predetermined transmission instant with the aid of a time multiplexing method; b) writing a validity datum, implemented as a toggle bit or as an N-bit counter, into a second area of the output register predetermined for the header segment, the particular validity datum specifying the validity of the corresponding written data unit; c) enabling the data transfer block buffered in the output register for transmission, after the particular data unit and the corresponding validity datum are written into the output register; d) repeating steps (a) through (c) until t

Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.

Abstract: A data transfer method is utilized for saving memory for storing packet in USB protocol. When a transmitter is to send a payload, the protocol layer of the transmitter writes the payload into a shared payload memory. The protocol layer generates a corresponding header according to the payload, and writes the corresponding header into a shared header memory. The data-link layer of the transmitter generates a packet by means of directly combining the payload saving in the shared payload memory and the header saving in the shared header memory, and sends the packet. Hence, when the transmitter is to send the payload, the transmitter only requires a memory of which the size is equal to a packet. In this way, the memory can be saved, reducing the cost.

Abstract: A data tree is generated in memory by parsing a first XML file. Default setting requests and validation requests are read from a second XML file. Default data values for nodes in the data tree are generated by executing default data generation code from locations specified in the default setting requests and recorded in the data tree. The content of data stored in nodes of the data tree is then validated by executing validation code from locations specified in the validation requests. The data tree is then searched by getting a nodepath, parsing the nodepath into a plurality of path pieces, searching the data tree based on each of the path pieces, and returning one or more nodes of the data tree based on the search that satisfy the path pieces. A data value of one or more nodes or child nodes may be specified to narrow the search.

Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract: A method is described which includes allocating transmission resources for transmitting data packets. The allocation of transmission resources includes a periodic allocation of the transmission resources that is applicable to a plurality of frames. The allocation of transmission resources includes an allocation of transmission resources for a first transmission of each HARQ process during the plurality of frames. The method includes receiving an indication of an allocation of transmission resources for data packets in a plurality of frames. Receiving and/or transmitting packets during the plurality of frames using the allocation of transmission resources is also included in the method. The frames in the plurality of frames may include a compressed MAC header. Apparatus and computer programs are also described.

Abstract: The error rate characteristic in a wireless communication apparatus for relaying communications between a mobile station and a base station is improved. For the modulation level of the resource for network coding, the modulation level from a relay station to the mobile station or the modulation level from the relay station to the base station, whichever is lower, is selected and thus the modulation level becomes QPSK. The relay station preferentially assigns S1 of a systematic bit of high importance, of S1+P1 to the network coding resource. The signal of S1+P1 not assigned to the network coding resource is assigned to the resource for the base station from the relay station. In the example, S1 is assigned to the resource for network coding and P1 is assigned to the resource for the base station from the relay station.

Abstract: A method implemented in a digital subscriber line (DSL) system is described for minimizing a misdetection probability at a far-end coded message receiver during transmission of a coded message. The method comprises jointly determining, at the far-end coded message receiver, a P matrix and a modulation scheme. The method further comprises encoding a message into a coded message with a systematic linear block code, the systematic linear block code having a generator matrix [I P], where I represents a linear block code component identity matrix and P represents the determined P matrix. The method also comprises modulating the encoded message to one or more tones forming a discrete multi-tone (DMT) symbol according to the determined modulation scheme.

Abstract: A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.

Abstract: A system for detecting errors in a channel includes a signal detector to detect a first sequence from the channel, the first sequence comprising a plurality of symbols. A decoder determines a total number of symbols in error in the first sequence. A decoder asserts a failure indication when the total number of symbols in error in the first sequence is greater than a predetermined threshold. A controller causes the signal detector to detect a second sequence from the channel in response to the decoder asserting the failure indication. The decoder identifies corresponding symbols in the first sequence and the second detected sequence that differ.

Abstract: A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.

Abstract: In a method for improved turbo decoding in a wireless communication system, jointly allocating (S1O) a predetermined maximum number of decoding iterations to a batch of received decoding jobs; and consecutively performing decoding iterations (S20) adaptively for each job in the batch until a convergence criteria is reached for each job in the batch, or until the predetermined maximum number of iterations for the batch is reached.

Abstract: A file switching method of a Basic Input/Output System (BIOS) file is disclosed. Upon a received read instruction, a timer for a predetermined timing is initiated, and a first data page having a requested data is read from a first BIOS file. An error correction check on the first data page is performed to check if any error in the first data page. If an error is occurred in the error correction check, repeating the step “reading the first data page”. If number of times of the repeating step exceeds a predetermined number, or if the predetermined timing is expired, a second data page having the requested data is read from a second BIOS file according to the read instruction.

Abstract: A user interface component receives an input error message. A query enhancer component derives error messages from the input error messages using error pattern(s) representative of the input error message and error sub-pattern(s) of the error pattern(s). A result aggregator component inputs each error message to search engines, receives search results, aggregates the search results, and provides the search results to the user interface. The enhancer component may include a pattern composer component to locate error patterns representative of the input error message, and a sub-pattern generator component to derive error sub-patterns from the error patterns. The aggregator component may determine whether the search results are in agreement with a predetermined criterion. If not, the aggregator component may request the enhancer component to provide additional error messages to input to the search engines.

Abstract: A method for facilitating management of a data processing environment is disclosed. In various embodiments, the method may include facilitating homogeneous monitoring of a plurality of heterogeneous data processing nodes of the data processing environment, the homogeneous monitoring including facilitating detecting one or more changes of one or more elements of the plurality of heterogeneous data processing nodes. In various embodiments, the method may further include facilitating performing one or more actions in response to detecting the one or more changes. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.

Abstract: Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.

Abstract: A computing system securely stores data to a dispersed data storage system. The computing system includes a processing module and a plurality of storage units. The processing module includes an encryptor and error encoder to encrypt and encode the data for dispersal utilizing a write command to the storage units. The storage units store the encrypted and encoded data when receiving the write command and the encrypted and encoded data.

Abstract: A data processing system is programmed to provide a method for enabling user-level one-to-all message/messaging (OTAM) broadcast within a distributed parallel computing environment in which multiple threads of a single job execute on different processing nodes across a network. The method comprises: generating one or more messages for transmission to at least one other processing node accessible via a network, where the messages are generated by/for a first thread executing at the data processing system (first processing node) and the other processing node executes one or more second threads of a same parallel job as the first thread. An OTAM broadcast is transmitting via a host fabric interface (HFI) of the data processing system as a one-to-all broadcast on the network, whereby the messages are transmitted to a cluster of processing nodes across the network that execute threads of the same parallel job as the first thread.

Abstract: According to one exemplary embodiment, a computer implemented method for detecting multiple failure modes in a set of electromigration failure data points includes sorting the data points by time to failure and dividing the data points to form first and second groups of data points to determine a first combination of first and second seed groups of data points providing an initial highest weighted R-square. The method further includes defining an intermediate group of data points shared between the first and second seed groups of data points and grouping the intermediate group of data points with the first and second seed groups of data points to determine a second combination of the first and second seed groups of data points providing a final highest weighted R-square. The initial highest weighted R-square is then compared to the final highest weighted R-square.

Abstract: In at least some embodiments, a method includes receiving a transport block transmission having a plurality of code words and decoding the code words. The method also includes testing each decoded code word to identify each code word as a good code word or a bad code word. During a subsequent retransmission of the transport block, the method includes repeating the decoding and the testing for previously identified bad code words, but not for previously identified good code words.

Abstract: A memory includes a nonvolatile memory cell array, and a memory control circuit which carries out writing of data to and reading of data from the memory cell array in access units of N bits where N is an integer equal to 2 or greater. The memory cell array includes a rewritable area in which both writing of data and reading of data are permissible, and a read-only area in which writing of data is prohibited and reading of data is permissible. The rewritable area is configured so that the N bits constituting one access unit contain both actual data and an error detection code. The read-only area is divided between an actual data area in which the N bits constituting one access unit contain actual data, and an error detection code area in which the N bits constituting one access unit contain error detection codes.

Abstract: A method, system and computer program product for performing error correction are disclosed. The method includes performing on source code a selected compilation operation from among a set of compilation operations and, responsive to encountering an error in the selected compilation operation, running an error handler to isolate the error utilizing data logged for the compilation operation. Responsive to determining that the error handler has not sufficiently isolated the error, a source code modifier is run to modify a portion of the source code selected by reference to the data logged for the compilation operation.