Abstract: The Invention pertains to the field of broadcasting digital services to terminals for transmitting said services, and concerns the problem of the smooth transfer between two versions of a same stream upstream from a transmitter within transmission networks on a single modulation frequency. The invention relates to a device for the fine synchronization of different versions of a data stream received with a certain offset or various jitters. In order to do so, the device includes different paths for detecting errors (ETR) and synchronising the stream (SNF).

Abstract: Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, sending a notification to an automated fault manager which (1) analyzes the number of CRC errors, (2) determines a cause of the CRC errors, and (3) takes appropriate corrective action based on the analysis. The method can further include storing CRC error measurements in a log organized by date and time, analyzing stored CRC error measurements to anticipate future CRC errors, and taking preventive action in advance of anticipated future CRC errors. The automated fault manager can be a rule-based fault/performance management system. The notification can be a Simple Network Management Protocol (SNMP) trap. The data stream analyzer can be an MPEG transport stream analyzer.

Abstract: A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.

Abstract: A wireless communication apparatus and an error detection result feedback method wherein unnecessary retransmissions are avoided to improve the system throughput. At a base station (200), a decoding unit (205) decodes code words, which have been mapped to a TTI bundle, for the respective TTIs in the TTI bundle. An error detecting unit (206) detects errors in the decoding results. A control information generating unit (209) sequentially transmits, in accordance with detection timings, error detection result information related to the code word transmitted in the tail TTI in the TTI bundle, as well as error detection result information related to the code word transmitted in at least one of the other TTIs. In this way, an apparatus that transmits the code words can use the result of error detection in the tail TTI as a reference used for deciding the execution of a retransmission, so that unnecessary retransmissions can be avoided.

Abstract: A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

Abstract: Disclosed is a novel cooperative communication strategy jointly using symbol-level random network coding and hierarchical modulation in order to effectively minimize packet error rate in error prone wireless networks. The source (or sender) broadcasts random network coded symbols with hierarchical modulation to the relays and the destination (or receiver). In following time slots, the relays, which have successfully decoded the original packet, transmit additional random network coded symbols to the destination. By applying the present disclosure into a multi-hop relay consumer device network, which comprises a set of consumer devices, error free transmission with high efficiency can be achieved.

Abstract: A system detects an error in a network device that receives data via a group of data streams. The system receives a data unit, where the data unit is associated with at least one of the streams and a sequence number for each of the associated streams. The system determines whether each sequence number associated with the data unit is a next sequence number for the corresponding stream, and detects an error for a particular stream when the sequence number for that stream is not a next sequence number.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein the sequence of control signal words has at least one control signal word, having: a controller designed to provide the input word at a first time and the input word at a second time for reading out the command memory, wherein the second time is delayed with respect to the first time, to effect a readout of the sequence of control signal words at a first time and a readout of the sequence of control signal words at a second time; and a comparator designed to receive and compare the associated sequences of control signal words read out at the first and second times, and to output a signal indicating an error if the associated sequences of control signal words read out at the first and second times are different.

Abstract: Various embodiments are described for back channel communication. One embodiment is a method that comprises receiving data at customer premises equipment (CPE), determining at least one error in the received data, formatting the determined error for communication to a central office (CO), and sending the formatted error to the CO via a back channel, wherein the formatted error is sent between sync frames of a discrete multitone (DMT) superframe.

Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: A method for detecting disturb phenomena between neighboring blocks in non-volatile memory includes, sequentially erasing and writing test data (pattern) to each block of a plurality of blocks under test in the non-volatile memory at a first time point, dividing the plurality of blocks under test into a first block group and a second block group based on ordinal number included in each block of the plurality of blocks under test, reading data from each block of the first block group at a second time point, and comparing the data with the test data written at the first time point to generate a first detecting result, and determining applicability of each block of the first block group based on the first detecting result.

Abstract: In one embodiment, an authentication module includes: a memory module that a plurality of data elements of an input interleaved signal are written to and read from; and a memory access controller configured to write the data elements of the input interleaved signal to the memory module sequentially in accordance with address information in a specific writing order commonly set between different signal formats of interleaved signals, and read the data elements written to the memory module from the memory module sequentially in accordance with address information in a specific reading order commonly set between the different signal formats, and output the read data elements as a restore signal.

Abstract: A storage apparatus includes: a host control unit for sending/receiving data to/from a host server; a drive control unit for sending/receiving the data to/from a storage device; a cache memory for temporarily storing the data sent and received between the host control unit and the drive control unit; a switch for switching between a transfer source and a transfer destination when transferring the data by selecting the transfer source and the transfer destination from among the host control unit, the cache memory, and the drive control unit; and a controller for controlling the host control unit, the drive control unit, and the switch; wherein processing for generating an error check code for the data and error check processing using the error check code are executed by the switch or are distributed among and executed by the host control unit, the drive control unit, the switch, and the controller.

Abstract: Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination.

Abstract: In a method and apparatus to conceal an error in an audio signal, when the current frame has no error and a past frame input prior to the current frame has an error, a parameter for the past frame is generated using a parameter for the current frame and a parameter of a frame out of frames input prior to the past frame and a previously stored parameter is updated with the generated parameter, thereby concealing an error of an audio signal without additional delay and preventing degradation in sound quality in a frame that is input after a frame having an error.

Abstract: Recording and replaying computer programs includes state synchronization and thread management techniques that facilitate accurately replaying the recorded execution of a multithreaded application program. State synchronization comprises, during execution of an application program in a computer system, detecting an operation of the application program to write a memory; preventing the operation to write the memory; storing a representation of the memory; permitting the operation to write the memory, resulting in written memory; comparing the written memory to the stored representation; and in response to determining that the written memory is different than the stored representation, generating a notification that a memory state synchronization exception occurred.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A recording apparatus includes a first operation unit that calculates an EDC intermediate value from first data in a first region at least including data to be read after an EDC when reading data in a second sequence in a first sector from a data buffer that stores a block, a data memory that stores at least part of the first data used for operation by the first operation unit, a second operation unit that reads data excluding the first data from the block as second data from the data buffer and calculates the EDC based on the second data and the EDC intermediate value, and an integration unit that integrates the first data, the second data and the EDC, wherein the integration unit receives the EDC and the second data from the second operation unit, receives the first data from the data memory, and integrates and outputs them.

Abstract: An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has e an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread.

Abstract: A system for and method of validating a VoIP telephone number order is presented. The described systems and methods may allow for corrupt telephone numbers to be discovered and placed in a corrupt telephone number pool. To this end, data may be mined from class 5 switches and VoIP routers and then compared to the telephone numbers in the order. If a telephone number is found to be corrupt, it may be removed from the order and stored in the corrupt telephone number repository for later review. The ordering process for any other requested telephone numbers may then continue on without interruption to the processing of the entire order.

Abstract: In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Abstract: A block-code-based structure that allows cross-packet coding of data using a sliding window. In this structure, each transmitted packet contains both information symbols and parity symbols generated by the information in previous packets. This code structure allows a receiver to recover lost packets without additional transmissions. If enough packets have been lost so that the receiver cannot recover one or more of them, new parity symbols can be generated and transmitted as additional packets. The parity symbols in these additional packets may be used by multiple receivers. Thus, the sliding window block code reduces retransmission overhead, particularly for multicast applications. Furthermore, the sliding window structure does not produce an encoding delay between the arrival of data and its transmission and reduces the decoding delay between the loss of a packet and its recovery.

Abstract: A technique for exchanging messages in a computer network using a public data template and a message transfer protocol with interdependent request and confirmation messages is described. A request message includes a first data structure obtained by packing application data that requires confirmation in the public data template. A network component receiving the request message unpacks the application data and provides the unpacked application data to a confirmation process. At the same time, the unpacked application data provided to the confirmation process is repacked in the public data template to generate a second data structure. The second data structure is sent with a confirmation message via the computer network to the sender of the request message. By comparing the content of the first data structure with the content of the second data structure, inconsistencies degrading the accuracy and trustworthiness of the confirmation process may be detected.

Abstract: A receiver with a time diversity combining component recovers a digital data signal transmitted over a voice channel of a digital wireless telecommunications network. A feature extraction module receives an audio frequency waveform encoding the digital data signal and generates a feature vector representing the digital data signal. A bit sequence estimation module analyzes the feature vector and generates an estimated bit sequence corresponding to the digital data signal. A memory stores the feature vector if the estimated bit sequence contains errors. A time diversity combining component generates a second estimated bit sequence by analyzing the first feature vector in combination with one or more feature vectors stored in the memory.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A user terminal for receiving a plurality of data pieces for a plurality of processes that are simultaneously operated. Each of the data pieces has an indicator indicating whether the data piece is new data and is transmitted from a network apparatus that changes an indicator value on a process-by-process basis. The user terminal includes a data receiving unit for receiving the data piece having the indicator, a response transmitting unit for transmitting a response indicating an acknowledgement or a negative acknowledgement for the received data piece, and an indicator determination unit for determining whether the indicator of the received data piece is the same as the indicator of a previous data piece received immediately previously for the same process as the process of the received data piece and whether the response for the previous data piece indicates the acknowledgement to discard the received data piece.

Abstract: A blade center is provided with an additional video output system which includes additional video output capabilities to allow a user to point to another blade within the blade center to work locally on a blade that does not include media tray access. The local access is granted via a control (e.g., a button) on the control panel of the blades or a control on the chassis or management module that allows the user to specify which blade to use for the second video output connection to a KVM console or direct host connect. This video output system advantageously allows more than one blade to be interactively utilized in a graphic environment at any time. Other blades executing local applications can be accessed and/or modified while another blade is accessing the media tray for installations and using one of the video output controls.

Abstract: A method and system to increase the throughput of a HARQ protocol in a wireless network. When a station receives a downlink HARQ sub-burst that has an incorrect cyclic redundancy check, it determines if there is an overflow event of its buffer. If so, the station reduces the size of the HARQ sub-burst to be stored in the buffer and stores the resized HARQ sub-burst in the buffer. When the station transmits an uplink HARQ sub-burst, the station can reduce the size of the transmitted HARQ sub-burst if it exceeds the size of the buffer. The amount of buffer required in the station can also be reduced by representing each log likelihood ratio (LLR) value of each of one or more bits of each symbol of a HARQ burst with a number of quantization bits based on a metric sensitivity to noise of each bit of each symbol.

Abstract: Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.

Abstract: A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.

Abstract: According to one embodiment, a system is provided that allows a receiver to determine that an initial error message (such as a NAK message) was not correctly received by a transmitter, and to cause the transmitter to continue transmitting information corresponding to data that has not yet been successfully decoded by the receiver. In accordance with another embodiment, the receiver can generate a message (e.g., a continue previous packet message) to correct the transmitter and initiate full recovery at the physical layer.

Abstract: A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A communication system includes a receiver configured to receive a packet that contains plural codewords, and a codeword failure detector cooperatively operable with the receiver. The codeword failure detector can be configured to detect a codeword failure in at least one codeword of the plural codewords as it is being received by the receiver, and to terminate reception at the receiver, when the codeword failure is detected before the end of the packet, to put the receiver into a power save mode for a duration of a remainder of the packet that contains the at least one codeword.

Abstract: Embodiments relate systems and methods for detecting machine faults in a network using acoustic monitoring. In embodiments, one or more servers, clients, or other machines in a managed network can have a microphone or other acoustic sensor integrated into motherboard or other hardware. The sensor can sample acoustic signals from inside or near the machine, and can digitize that data. The resulting set of acoustic data can be transmitted to a management server or other destination for analysis of the operating sounds related to that machine. For instance, the acoustic data can be analyzed to detect indications of a failed or failing hard drive, for instance by detecting spindle whine or head movement noises, or a failed or failing power supply based on other sounds. The management server can respond to potential fault events for instance by issuing configuration commands, such as instructions to power down the malfunctioning component.

Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Abstract: One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e.g., where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.

Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Abstract: A network scanning method and device are provided that allow an image scanning device to scan documents and transmit the scan data to a server. The image scanning device checks a connection between the image scanning device and a server, generates scan data by scanning documents, stores the generated scan data in a storage unit if a connection error exists between the image scanning device and the server, and checks whether the connection error between the image scanning device and the server is corrected. The image scanning device transmits the scan data stored in the storage unit to the server when the connection error has been corrected. Transmission of scan data is delayed until the connection error to the server is corrected, thereby reducing inconvenience in having to reset network settings after waiting until the connection error to the server has been corrected.

Abstract: According to the invention, a method for authenticating download of a number of digital content files ordered from a web site is disclosed. In one step, a selection of the digital content files is received with the web site. Download manager software, media information, the digital content files, and first codes for each of the digital content files are sent to the client computer. The media information indicates a location of each of the number of digital content files. A first code is calculated for each of the digital content files. If the client computer determines that the first code doesn't match a second code for a particular digital content file, it is resent.

Abstract: A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.

Abstract: An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs a node processing operation using information stored in at least one of the node memory and the edge memory, stores a check node value generated by performing the node processing operation in the node memory, and stores a message generated by performing the node processing operation in the edge memory. A switch switches outputs of the node memory and the node processor through a permutation operation. A parity check verifier parity-checks an output from the node memory. A controller provides a control signal for controlling the node processor.

Abstract: An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.