Abstract: Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.

Abstract: A method of processing a stream of coded data before decoding comprises a step of detecting missing or erroneous data in the stream of coded data. It comprises a step of generating a series of data ready for decoding formed from the stream of coded data, and a series of additional data supplying information representing the position of the missing or erroneous data detected.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm? elements sorted in said ascending or descending order, nm? being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations.

Abstract: Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a quality threshold; and setting the RRO flaw flag when the counted number of samples that that do not satisfy the quality threshold exceeds a specified flaw threshold. If the RRO flaw flag is set, the RRO data can be discarded, and/or an error recovery mechanism can be implemented to obtain the RRO data.

Abstract: The present inventions are related to systems and methods for information divergence based data processing.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession until all N sectors are decoded, wherein upon determination of successful completion of iterative decoding corresponding to a current sector of the N sectors, immediately initiating iterative decoding a next sector of the N sectors.

Abstract: A method for transmitting data packets from a data source to a data sink with highest possible security in an energy efficient manner is obtained by at least two data packets are sent from the at least one data source to the at least one data sink, at least one of the at least two transmitted data packets being free of a single test value, the at least two data packets being sent from the at least one data source to the at least one data sink such that each of the at least two data packets received by the at least one data sink can be processed thereby essentially immediately after the reception of each data packet, and an overall test value for verifying integrity of a pre-defined number of associated data packets being transmitted to the at least one data sink from the at least one data source.

Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.

Abstract: A method for access or starting verification for a vehicle using a mobile identification encoder and at least two antennas located in or on the vehicle at different locations includes: the antennas emitting electromagnetic signals at alterable times, wherein the electromagnetic signals are emitted in transmission blocks having alterable specific properties and wherein a plurality of transmission blocks are strung together to form a communication message in which each transmission block adopts an alterable position in time, the identification encoder receiving the electromagnetic signals emitted by the antennas and processing them to generate a response signal, and altering at least one of the times at which the individual antennas are actuated, the specific properties of the individual transmission blocks, and the position of the individual transmission blocks in time in the communication message in accordance with a cryptographical method.

Abstract: A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.

Abstract: One preferred embodiment of the present invention provides systems and methods for analyzing the delivery performance of newsgroup services. Briefly described, in architecture, one embodiment, among others, includes a newsgroup evaluation system configured to determine a delivery rate for a newsgroup server. In other embodiments, methods and systems are provided for analyzing completion and retention for newsgroup services.

Abstract: A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations.

Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination.

Abstract: Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.

Abstract: A data protection method is provided that includes determining a compressibility score of one or more lines of data stored in a memory. The memory includes a first area characterized by a first reliability level and a second area characterized by a second reliability level. Lines of data with a first compressibility score are migrated to the first area of the memory. Lines of data with a second compressibility score are migrated to the second area of the memory.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract: A method, control module and system of a vehicle including at least a first and a second control computer each containing a number of local Digital Control Modules and at least one Actuator Control Module wherein the Actuator Control Module of each control computer is operatively connected to all local Digital Control Modules of the same control computer, wherein the Actuator Control Module of each control computer is further operatively connected to all Digital Control Modules of the electrical system in a manner that enables each Actuator Control Module of the system to receive internal data of each Digital Control Module of the electrical system.

Abstract: An embodiment of the invention provides a telecommunications method performed by a second telecommunications device. According to the embodiment, the second telecommunications device first tries to use a received part of a data block to decode the data block, wherein the received part is received from a first telecommunications device. Next, the second telecommunications device determines whether a code metric derived based on the received part indicates that the data block is decodable. If the code metric indicates that the data block is decodable, the second telecommunications device further determines whether a set of confirmation criteria is satisfied.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: The disclosure is related to systems and methods for checking the integrity of a data transfer to or from a buffer or other data storage medium. Check values can be added to a data object in a data object based file system. From the check values, a device receiving the data object may determine an integrity or validity of the received data object based on the check values. In a particular embodiment, a hash value may be determined based on the check values. The hash value may be stored in the metadata of the transferred data object. The receiving device may re-calculate the hash value from the check values and compare it to the stored hash value to determine an integrity of the received data object.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOVA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract: An exemplary method includes switching, by a media content access subsystem, from a program stream to an advertisement stream in response to a switching instruction received by the media content access subsystem, detecting, by the media content access subsystem, a predetermined number of markers included within the advertisement stream, the predetermined number of markers indicative of an error associated with the advertisement stream, and switching, by the media content access subsystem, from the advertisement stream to another media content stream in response to the detecting of the predetermined number of markers. Corresponding methods and systems are also disclosed.

Abstract: A method and device for segmenting, CRC encoding and turbo encoding a CRC attached transport block.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: The present invention is related to systems and methods for maintaining additional processing information during extended delay processing.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: In one embodiment, a tape drive system includes a soft detector for executing a first forward loop of a detection algorithm on a first block of signal samples during a first time interval; and logic for executing forward and reverse loops during several time intervals; and logic adapted for outputting a first decoded block of signal samples based on the executing the decoding algorithm on the first block during a sixth time interval, wherein a sum of second, third, fourth, fifth, and sixth time intervals are about equal in duration to the first time interval.

Abstract: In one embodiment, a method includes executing a first forward loop of a detection algorithm on a block of signal samples during a first time interval, executing a first reverse loop of the detection algorithm on the block during a second time interval to produce first soft information, executing a decoding algorithm on the block during a third time interval using the first soft information to produce second soft information, executing a second forward loop of the detection algorithm on the block during a fourth time interval using the second soft information, executing a second reverse loop of the detection algorithm on the block during a fifth time interval to produce third soft information, executing the decoding algorithm on the block during a sixth time interval using the third soft information to produce a decoded block of signal samples, and outputting the decoded block of signal samples.

Abstract: Techniques are described for detecting faults in media content based on the behavior of users viewing the media content. Embodiments stream a first instance of media content to one or more users. The behavior of the one or more users is monitored while the users are viewing the streaming first instance of media content. Embodiments then determine whether the first instance of media content is faulty, based on the monitored behavior of the one or more users.

Abstract: A command control circuit includes a command decoder configured to decode a command and generate an internal command, an error check unit configured to detect an error in the command and an address by using check data and generate an error check signal in response to the detection, and a blocking unit configured to block or pass the internal command in response to first and second states of the error check signal.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: Methods and systems for validating positions reported in AIS message signals by fitting suitably chosen functions to signal characteristic data, such as timing and Doppler shift data, derived from a plurality of AIS message signals. Ships whose reported positions deviate from the fitted function may be flagged as suspect.

Abstract: A method of handling packet error for a communication device in a wireless communication system is disclosed. The method comprises the steps of: obtaining a payload from a received protocol data unit (PDU) and verifying the payload according to a predetermined payload format.

Abstract: A method begins by a processing module receiving a write request that includes a batch of encoded data slices and a corresponding batch of slice names, wherein the batch of encoded data slices includes encoded data slices that have slices names that have a common data object storage name, a common slice storage name, and a different data segment storage name. The method continues with the processing module determining whether a storage file exists based on the common data object storage name. The method continues with the processing module creating the storage file based on the common data object storage name when the storage file does not exist. The method continues with the processing module storing the batch of encoded data slices in the storage file based on the corresponding batch of slice names.

Abstract: In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.

Abstract: A system and method for error tolerant content delivery is provided. A data file for transmission including metadata and data is received. The metadata includes mandatory portions and optional portions. The file is parsed into packets and transmitted as a data stream to a plurality of receiver devices, which may look for transmission errors in the control data of the data stream. Data streams comprising errors are discarded; otherwise, the receiver device converts the data stream into the native file format and stores it. The system may bifurcate each data file into the common encrypted content and the uniquely encrypted portion. The commonly encrypted portion of the file may be transmitted to a plurality of receiver devices using a multicast transmission medium, and the relatively small uniquely encrypted portions may be transmitted using a unicast method to each receiver individually. The receiver device may then reconstitute the DRM data file.

Abstract: A method includes, after data is stored at a data area of a memory device and error correction code (ECC) data corresponding to the data is stored at an ECC area corresponding to the data area, detecting a triggering condition. In response to detecting the triggering condition, the method also includes storing second ECC data in the ECC area, where the second ECC data includes redundant information for a first portion of the data area and storing third ECC data at the memory device. The third ECC data includes redundant information for a second portion of the data area.