Abstract: A device and method of detecting and correcting errors in data having a control unit, a coefficient computation unit, an error computation unit, and an error detection and correction unit, where errors such as garbled data, missing data, and added data are either detected and corrected or just detected.

Abstract: A signal error is determined by obtaining a known property of an expected signal. A signal is received and a signal error is determined based at least in part on the received signal and the known property of the expected signal.

Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to error detection or correction of stored signals in memory devices.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: The various embodiments herein provide a method and system for providing protection switching at a client layer on squelching of clients by a server layer protection controller in a nested protection system. The method comprises of marking a plurality of alarms of a pre-defined pattern and disabling a hold-off period for the plurality of marked alarms on receiving a squelch operation indication. The system comprises of one or more hold-off timers pre-configured with a hold off period and an alarm filter and hold-off processor (AFHP) for disabling the hold-off timer to invalidate the hold-off period for the plurality of marked alarms, wherein the plurality of marked alarms is an AIS generated due to squelching.

Abstract: A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided.

Abstract: A bill identification apparatus accurately identifying an authenticity with a folding line formed in a watermark. The bill identification apparatus includes: bill reading means; a converter which converts the watermarked image read by the bill reading means for each pixel containing color information having brightness; a image correction processing part which calculates an average density value for each pixel array in one direction, an average density value for each pixel array in the other direction, and an average density value of an entire watermarked image and corrects density values of respective pixels so as to approximate or match the average density value of the entire watermarked image; a reference data storage part which stores a reference watermarked image; an identification processing part which compares the corrected image by the image correction processing part with the reference watermarked image and identifies an authenticity.

Abstract: An integrated circuit precharges a node 6 to a precharge voltage using precharging circuitry 4. During a discharge phase discharging circuitry 8 selectively discharges that node 6 is to represent a data/signal value. Sensing circuitry 10 detects a discharge characteristic to identify the data/signal value being represented. During the subsequent precharging operation of the node 6 back to the precharge voltage, validating circuitry 12 detects a precharge characteristic, such as the precharge current, the charge transferred, changes in the node voltage or a like, and compares this to the detected discharge characteristic corresponding to the data/signal value sensed by the sensing circuitry. If there is a mismatch, then an operation error signal is generated. The operation error signal may be used to adjust operation parameter, such as the operating voltage/frequency, the timing of the operation of a portion of the integrated circuit or another parameter.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.

Abstract: Methods and apparatus enabling a wireless network to implement efficient and robust paging channel operation. In one aspect, the invention permits recovery of a paging channel after a virtual connection failure. A virtually connected UMTS cellular phone that misses a paging notification will no longer be synchronized with its serving radio network, and the resultant loss of synchronization causes a service “blackout” until the devices are resynchronized. Accordingly, in one embodiment, a virtually connected cellular device continuously monitors for fallback messaging, greatly expediting detection and correction of a virtual connection failure. In another embodiment, a virtually connected base station which is unable to page a cellular device in a virtually connected mode continues paging in both virtual connection and fallback modes, thereby provoking an immediate response from the cellular device.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.

Abstract: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

Abstract: An embodiment of the invention provides a backup method for a portable device to back up a first data to a backup server. The backup method includes steps of determining whether the backup server can be accessed; when the backup server can be accessed, establishing a first data transmission path that the first data would be backed up to the backup server via a third party, a second data transmission path that the first data would be backed up to the backup server via a router, and a third data transmission path that the first data would directly backed up to the backup server; selecting one data transmission path among the first, second and third data transmission paths; and backing up the first data via the selected data transmission path.

Abstract: Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

Abstract: An apparatus, system, and method are disclosed for reconfiguring an array of solid-state storage elements. The method includes determining that one or more storage elements are unavailable to store data. The storage elements are configured in an array of N storage elements that each store a portion of a first ECC chunk and P storage elements that store first parity data corresponding to the first ECC chunk. The method includes generating a second ECC chunk comprising at least a portion of the data of the first ECC chunk. The method includes storing the second ECC chunk and associated second parity data across (N+P)?Z storage elements where 1?Z?P.

Abstract: A read method in a flash memory system containing a flash memory and a memory controller includes updating a selected one of indexes of a selected one of blocks of the flash memory, in a wear-out table for indexing each of the blocks of the flash memory, and setting a start read level to start read retry on the selected block by referring to a read retry table corresponding to a wear-out degree included in the selected index when a current request of read retry on the selected block is received.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Provided is a radio communication device for performing radio communication with another radio communication device includes a control unit that controls to prepare for data loss during radio communication of transmission data and a transmission unit that transmits the transmission data by radio according to the control of the control unit. One of the radio communication device and the other radio communication device estimates a distance from the other based on a field intensity of a radio signal which is judged to satisfy a certain requirement regarding noise component among received radio signals received from the other of the radio communication device and the other radio communication device. The control unit performs a control of a content according to the distance estimation result.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other.

Abstract: Various embodiments of a semiconductor memory apparatus and a related data read method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a global data bus, an error detection unit, a first data output unit, and a second data output unit. The global data bus transfers first data and second data. The error detection unit performs an error bit detection operation on the first data and the second data and generates a first error detection bit and a second error detection bit. The first data output unit combines the first data and the first error detection bit in series and outputs the combined bits. The second data output unit combines the second data and the second error detection bit in series and outputs the combined bits.

Abstract: The subject disclosure is directed towards a technology by which the accuracy of context-based information provided by at least one data source for received context data is increased. Correctness information received in association with usage of looked up context-based information is logged. The correctness information may be processed to increase the overall accuracy by correcting a data source, and/or by creating a blended data source that includes the most likely accurate portions (segments) from among multiple data sources as determined via the correctness information.

Abstract: Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Abstract: A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Abstract: Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Abstract: A filtering method, system, and equipment applied in digital communication technologies are disclosed in the embodiments of the present invention. The filtering method of the present embodiments includes: acquiring filtering coefficients of a part of all subcarriers according to data transmission errors; acquiring filtering coefficients of remaining subcarriers through an interpolation algorithm according to the filtering coefficients of the part of subcarriers; and finally, filtering the data corresponding to the multiple subcarriers according to the filtering coefficients of the part of subcarriers and the filtering coefficients of the remaining subcarriers. The part of subcarriers may be selected at a regular interval, or may be subcarriers which are located at a motion value away from the part of subcarriers selected in the previous update of the filtering coefficients. The method of the present embodiments reduces the amount of operation and hardware expenditure, and saves the cost.

Abstract: The embodiments herein relate to Low Density Parity Check (LDPC) codes, their corresponding matrices, and with an LDPC decoder architecture used to decode those codes. Embodiments herein relate to methods to generate a set of LDPC codes (typically of different rates) that share their wires as much as possible and therefore reduce the silicon area and ease the routing.

Abstract: An apparatus, program product, and method that run an algorithm on a hardware based processor, generate a hardware error as a result of running the algorithm, generate an algorithm output for the algorithm, compare the algorithm output to another output for the algorithm, and detect the hardware error from the comparison. The algorithm is designed to cause the hardware based processor to heat to a degree that increases the likelihood of hardware errors to manifest, and the hardware error is observable in the algorithm output. As such, electronic components may be sufficiently heated and/or sufficiently stressed to create better conditions for generating hardware errors, and the output of the algorithm may be compared at the end of the run to detect a hardware error that occurred anywhere during the run that may otherwise not be detected by traditional methodologies (e.g., due to cooling, insufficient heat and/or stress, etc.).

Abstract: A layout error detection method includes the following steps, reading a layout file, in which the layout file includes a plurality of elements and a plurality of coordinates, and each element is corresponding to one coordinate; reading a record table, in which the record table includes an identification column, a coordinate column, and a flag column; scanning the layout file to obtain an error detection result, in which the error detection result is corresponding to an identification data and a coordinate data; searching the identification column of the record table to judge whether the identification column has the same identifier according to the identification data, and when a judgment result is false, writing the identification data and the coordinate data of the error detection result, setting a flag value to logic 0, and marking the error detection result; and scanning the layout file repeatedly until all the elements are scanned.

Abstract: A method of communicating information includes receiving a data stream from the host computer, the data stream including a plurality of bytes, one or more bytes of the plurality of bytes being associated with obtaining medical related information, and parsing one or more bytes in the data stream at the sensor device. As a result of parsing the one or more bytes, the method includes identifying a type of medical related information, obtaining the medical related information from the sensor device, and sending the medical related information to the host computer. The parsing of the one or more bytes in the data stream is performed using a single pass through the data stream, one or more data validity checks being performed during the single pass, the medical related information being obtained after the data stream is parsed in the single pass through the data stream.

Abstract: A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Abstract: The packet interleaving method includes selecting successive input sets of consecutive input packets (X1 . . . XNin) received from a forward correction module (14), each input packet (Xj) being a vector of constellation points of a predetermined constellation diagram. For each input set, it further includes generating an output set of output packets (O1 . . . ONout), each output packet (Om) being a vector of constellation points, by distributing the constellation points of each input packet (Xj) of the input set, and sending the output packets (O1 . . . ONout) of the output set to a modulator (18). The input set including Nin input packets (X1 . . . XNin) and each of the Nin input packets (X1 . . . XNin) including a same number Lin of constellation points, the number Nout of output packets in the output set is related to Lin by the relation Lin=A×Nout, where A is a fixed whole number.

Abstract: A computer-readable medium storing a data management program makes a computer manage data redundantly stored in storage devices having storage areas split into slices for data management. The data management program realizes the following functions in the computer. A first function receives irregularity information indicating that each of one or more of the storage devices may be possibly faulty, and stores the irregularity information in a storage; and a second function determines, by reference to the irregularity information, whether or not a first storage device containing a slice to be accessed is possibly faulty, on receipt of access information indicating occurrence of a request to access the slice. When yes is determined, the second function instructs an external device to recover data stored in the slice, where the external device controls a second storage device storing redundant data identical to the data stored in the slice.

Abstract: Various example embodiments are disclosed herein. In an example embodiment, a method of transmitting data via a wireless transmission path that may include a user equipment as a first end point, a base station as second end point, and at least one relay station as an intermediate point(s). The method may include receiving a data transmission from a prior point in the transmission path. Substantially simultaneously: forwarding the received data to the next point in the transmission path, and determining if the received data is corrupt. Transmitting a transmission message to the next point in the transmission path indicating whether or not the received data was corrupt. And, if the data is not corrupt, transmitting a receipt message to the prior point indicating that the data was uncorrupt when received.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m-1 is received. A code word with length N=2m-1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract: Provided are methods and systems of selectively decoding optical data read from an optical storage medium based on a checksum algorithm technique. In one embodiment, optical data is converted into a data stream and buffered, and the checksum algorithm is applied to the data stream. If the calculated checksum matches an encoded checksum of the data stream, the data stream may be output without requiring further decoding. If the calculated checksum does not match the encoded checksum, the buffered data stream may be decoded to produce a corrected data stream, and the checksum algorithm may be applied to the corrected data stream. In some embodiments, the optical data may be re-read if the corrected data stream does not pass the checksum test, and the data stream obtained from the re-reading may be combined with the buffered data stream for further decoding.

Abstract: Obscuring information in messages to be exchanged over a communications network. In one aspect, the information comprises path name information and parameters for use in a Uniform Resource Locator (“URL”). In another aspect, the information comprises links and parameters used in forms, where hidden parameters are removed from a form and used as URL parameters. A compression dictionary is used to create a compressed form of the information. An identifier of the dictionary and an error detection code (such as a checksum) computed over the compressed information are concatenated with the compressed information, and this is encoded for sending on an outbound message. The original information is then recovered from an inbound message which contains the obscured information by reversing the processing used for the obscuring.

Abstract: Techniques for determining similarity between error reports received by an error reporting service. An error report may be compared to other previously-received error reports to determine similarity and facilitate diagnosing and resolving an error that generated the error report. In some implementations, the similarity may be determined by comparing frames included in a callstack of an error report to frames included in callstacks in other error reports to determine an edit distance between the callstacks, which may be based on the number and type of frame differences between callstacks. Each type of change may be weighted differently when determining the edit distance. Additionally or alternatively, the comparison may be performed by comparing a type of error, process names, and/or exception codes for the errors contained in the error reports. The similarity may be expressed as a probability that two error reports were generated as a result of a same error.

Abstract: Obscuring information in messages to be exchanged over a communications network. In one aspect, the information comprises path name information and parameters for use in a Uniform Resource Locator (“URL”). In another aspect, the information comprises links and parameters used in forms, where hidden parameters are removed from a form and used as URL parameters. A compression dictionary is used to create a compressed form of the information. An identifier of the dictionary and an error detection code (such as a checksum) computed over the compressed information are concatenated with the compressed information, and this is encoded for sending on an outbound message. The original information is then recovered from an inbound message which contains the obscured information by reversing the processing used for the obscuring.

Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

Abstract: The present disclosure provides video transmission systems and methods with video data flows transmitted over a Carrier Ethernet Network at Layer 2 with redundancy in order to provide hitless protection switching and uninterrupted video service delivery, such as during periods of asymmetric congestion or hard network failures. In an exemplary embodiment, the video transmission systems and methods provide the redundancy in a manner similar to 1+1 linear protection with hit-less protection switching. In another exemplary embodiment, the video transmission systems and methods provide encapsulated video signals over Ethernet using standardized Carrier Ethernet frames with additional sequencing information. Optionally, the video transmission systems and methods may also include packet-based forward error correction information for additional resiliency.

Abstract: A digital lighting control network protocol with forward and backward frames, each of the frames including an error check code. A no-acknowledgment (NAK) signal is sent from a receiving node to a transmitting node responsive to the error check code. An interface circuit of the receiving node may include an energy storage section to store at least some energy from the network while receiving digital signals, and an output section to transmit digital signals to the network using the stored energy. The interface circuit may also include a high voltage buffer circuit. The transmitting node may send forward frames to receiving nodes based on device type.

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).

Abstract: Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes the following steps: (a) the nodes are divided according to a parity-check matrix into check nodes for a parity-check message and variable nodes for a bit message; (b) the check nodes are divided into a predetermined number of subsets; (c) the LDPC codeword of each subset for all the check nodes is sequentially decoded; (d) an output message is generated for verifying validity of the decoding result; and (e) the steps (b), (c), and (d) are iteratively performed by a predetermined number of iterations.