Abstract: A method for correcting read data error of a nonvolatile memory device, the error correction method including performing a first read operation of applying a first non-selection read voltage to a plurality of unselected memory cells to read a plurality of selected memory cells, performing a second read operation of applying a second non-selection read voltage less than the first non-selection read voltage to the unselected memory cells to read the selected memory cells, and comparing data sensed in the first and second read operations to detect error locations of read data.

Abstract: The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols Sn, where n is a positive integer.

Abstract: A decoding device that performs decoding of data transmitted from each of a plurality of users comprises an iterative decoding section that repeats decoding of the data until no error is detected in a result of decoding, an error detection section that performs error detection on the decoding result each time decoding is performed, and a decoding order control section that estimates with respect to each of the plurality of users a decoding completion time, which is a time period the time period required until no error is detected in the result of decoding of the data transmitted from the user, and that assigns priorities to the users in increasing order of the estimated decoding completion time. The iterative decoding section performs decoding of the data transmitted from the users for the users in descending order of the priorities.

Abstract: Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Abstract: An apparatus and method for reducing power consumption in a mobile communication system are provided. The apparatus includes a time slicing processor. When a frame border of the last section for determining a burst reception end time is not detected during a burst reception operation, the time slicing processor receives a burst enough to restore the whole MPE-FEC frame to the former state or receives an early burst reception end request for notifying that it is impossible to restore the whole MPE-FEC frame to the former state, and terminates the burst reception process.

Abstract: The present invention discloses a method, apparatus and software for determining a relative measure of the risk of faults in a built product relative to a reference build of the product. The measure can be based on a balance between the additional risk added as a result of changes made in a given build and the risk reduction resulting from testing applied to the build. The product associated with the builds can be a software product, a firmware product, an electronic device, and/or any manufactured product.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

Abstract: A radio device includes a radio section which transmits a digital signal through a digital communication path, and a baseband processing section which performs a baseband processing on the digital signal received from the radio section, wherein the baseband processing section performs error detection of the digital signal before performing the baseband processing, and wherein, when an error is detected in the digital signal, the baseband processing section performs the baseband processing without waiting for reception of a retransmitted signal from the radio section.

Abstract: Provided is a method and system for calculating a bivariate Gaussian Q function using a univariate Gaussian Q function to thereby analyze an error probability of a communication system. A method of calculating an error probability of a communication system may include: receiving encoded communication information from another communication system; restoring information desired to be transmitted by another user by decoding the encoded communication system; and calculating the error probability by analyzing the restored information using a bivariate Gaussian Q function, the error probability indicating a probability that the restored information is different from the information desired to be transmitted by the other user. The calculating may include calculating the bivariate Gaussian Q function using a univariate Gaussian Q function.

Abstract: A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.

Abstract: In a semiconductor storage device 10 included in a liquid container 20, on reception of an encoding request for encoding readout data, a write-read controller 140 changes over the position of a switch 141 to output encoded readout data, which is obtained by an encoding operation in a data encoding circuit 150, to a data signal terminal SDAT. In the case of no reception of the encoding request for encoding the readout data, on the other hand, the write-read controller 140 changes over the position of the switch 141 to output raw data read out from a memory array 100 to the data signal terminal SDAT.

Abstract: A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.

Abstract: Exemplary receiving apparatus receives serial data that includes contiguous blocks each having M-bit known pattern. The apparatus includes a serial-parallel conversion circuit that arranges bits in the serial data to generates N-bit wide (N<M) parallel data, a register group including a first register that stores a word of the parallel data and second registers to which the word of the parallel data is sequentially shifted and stored, a comparing circuit that compares the known pattern with storage patterns each including M contiguous bits stored in the register group, and a detecting circuit. The detecting circuit detects reception of the serial data if the comparing circuit detects a first match between the known pattern and a first one of the storage patterns, and a second match between the known pattern and a second one of the storage patterns that starts with a specific bit during a specific clock cycle.

Abstract: A system includes at least one adaptive filter coupled to a first communication channel and at least one other communications channel. The at least one adaptive filter includes at least one set of adaptive filter coefficients. A memory stores at least one predetermined set of filter coefficient thresholds. The filter coefficient thresholds may be indicative of channel faults, channel to channel faults or a length of the channel. A controller is configured to compare the set of filter coefficients to the predetermined set of filter coefficient thresholds. The controller is configured to determine the information about the channels based on compare results.

Abstract: A test pattern generating device generates a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit, wherein each of the common circuits has a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit. A set of scan chains and a set of assumed faults are created for each of the common circuits. Any of the common circuits is determined as the common circuit of a first test target. After the determined common circuit of the first test target is subjected to ATPG and detection of circuit fault, a test pattern generated in successful ATPG about the common circuit of the first test target is diverted to the common circuit determined as the second test target, and ATPG and detection of a circuit fault of the non-common circuit part.

Abstract: Disclosed is an apparatus having a detector for an iterative LDPC-coded MIMO-OFDM system, where the detector is configured to use a structured irregular LDPC code in conjunction with a belief propagation algorithm. Also disclosed is an apparatus having a detector for a structured irregular LDPC-coded MIMO-OFDM system, where the detector is configured to use an iterative Recursive Least Squares-based data detection and channel estimation technique. Corresponding methods and computer program products are also disclosed.

Abstract: A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.

Abstract: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.

Abstract: Circuits and methods to generate a True Random Number Generator (TRNG) with tamper-detection are presented. In one embodiment, the circuit includes two identical TRNG circuits and logic circuitry that combines and correlates the outputs of the two TRNG circuits. The two identical TRNG circuits are located in close proximity to each other inside an Integrated Circuit (IC). The logic circuitry analyzes the outputs of the two TRNG circuits and the historical values of the relation between the outputs of the two TRNG circuits to determine if the outputs are correlated. If the outputs are not correlated, the logic circuitry outputs a true random number sequence based on the combination of the two TRNG circuits. As a result, circuit tampering, such as changes in temperature or voltage supplies, is detected in the IC.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A device includes a taxonomy schema; a display link base; a calculation link base; an XBRL document memory unit which stores an instance; an error inference unit which compares a calculated value of an input value of the instance corresponding to an item element of the calculation value in accordance with the calculation link base with the input value of the instance corresponding to the calculated value based on the display link base, detects a discrepancy between the calculation value and the input value, specifies a calculation tree structure of the calculation link base including the item element in which the discrepancy is detected and a display tree structure of the display link base including the item element in which the discrepancy is detected, and infers that a state of too many or too few item elements is regarded as a discrepancy error in the case that such an item element is set only in either one of the trees and that the item element has an input that is consistent with an absolute value of the

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOYA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: A method for fail-safe transmission of information between a transmitter and a receiver is disclosed. At least two telegrams relating to the information are transmitted as a first telegram via a first channel and a second telegram via a second channel from the transmitter to the receiver. To identify an error affecting the information during transmission, a first identifier is generated from a first subset of the first telegram being used at the receiver to identify the information contained in the first telegram. This method is used for communication from a safety switching device to a control unit.

Abstract: An error detection code (EDC) memory module coupled via a bus to a data memory module. In response to a request for data words from a specified memory address within the data memory module, the data memory module provides a predetermined number of data words and the EDC memory module provides a corresponding EDC word.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for efficient in-band reliability with separate cyclic redundancy code (CRC) frames. In some embodiments, a memory system uses data frames to transfer data between a host and a memory device. The system also uses a separate frame (e.g., a CRC frame) to transfer a CRC checksum that covers the data frames.

Abstract: A method and apparatus for distributing dynamically reconfigurable content to a mobile device is provided. One embodiment of a method for encoding a data stream to enable error correction by a receiver of the data stream includes storing a block of the data stream in a first memory array, processing the first memory array to produce a second memory array, inverting the second memory array, and storing the second memory array, as inverted, as a third memory array.

Abstract: In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). The CNUs generate check-node messages using a scaled min-sum algorithm, an offset min-sum algorithm, or a scaled and offset min-sum algorithm. Initially, the controller selects a scaling factor and an offset value. The scaling factor may be set to one for no scaling, and the offset value may be set to zero for no offsetting. If the decoder is unable to correctly decode a codeword, then (i) the controller selects a new scaling and/or offset value and (ii) the decoder attempts to correctly decode the codeword using the new scaling and/or offset value. By changing the scaling factor and/or offset value, LDPC decoders of the present invention may be capable of improving error-floor characteristics over LDPC decoders that use only fixed or no scaling factors or fixed or no offsetting factors.

Abstract: Determining whether or not an instruction execution part that executes an instruction from a processor meets an error generation condition; when an error setting direction that directs to set an error has been input, outputting a determination direction to determine whether or not the instruction execution part meets the error generation condition, and, in a case where the error generation condition is not met when the error setting direction has been input, again outputting, after a predetermined time has elapsed from the output of the determination direction, the determination direction; and outputting an error generation direction to the instruction execution part in a case where the instruction execution part meets the error generation condition by the determination are carried out.

Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.

Abstract: Techniques are provided for receiving a transmitted first packet that was formatted using a known scrambling algorithm with an unknown scrambling seed. An encoded packet payload is extracted from the first packet header. The encoded packet payload header is decoded to obtain a first scrambled packet payload header. For each potential value of the unknown seed, the first scrambled packet payload header is descrambled to produce a first set of descrambled packet payload headers and for each potential value of initial register values associated with a cyclic redundancy check, the cyclic redundancy check is executed comprising polynomial division on each of the descrambled packet payload headers such that when the polynomial division results in a zero remainder, a potential unscrambled payload header for the first packet is obtained. Information about the first packet is obtained from the potential unscrambled payload header.

Abstract: Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

Abstract: In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: A management method for a non-volatile memory comprises the steps of providing the non-volatile memory with at least one block having a plurality of pages to store user data and parity data; dividing at least one of the pages into a plurality of partitions each including the user data and parity data; determining codeword length of each of the partitions, the codeword length comprising message length with sufficient storage to store the user data and parity length storing the parity data; and storing extra parity data in the partition with the codeword length. When storing extra parity data in the codeword length, the parity length is increased and the message length is decreased.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: Data bits stored in memory cells are recognized by an ECC generator as data bit strings in a first direction and data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on a respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on a respective correction code in the second direction, and causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: A digital broadcasting system comprising of a digital broadcasting station, a set of digital broadcast receivers, and a switched network, wherein the digital broadcasting station transmits a digital signal to the set of digital broadcast receivers, and the digital broadcast receivers exchange error correction information with each other using the network to compensate errors in local receptions of the digital signal at each digital broadcast receiver location.

Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used.

Abstract: A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: The method is executed by a call control server that establishes a media session for sending and receiving media data between a calling terminal and a called terminal. The method includes exchanging messages with calling terminal and called terminal for establishing the media session, generating a session information necessary for establishing the media session based on the messages exchanged with the calling terminal and/or the called terminal, monitoring a media information included in the messages, the media information containing a definition specifying a way of exchanging the media data, determining, based on the monitoring result, whether the media session has been established, and transferring the session information to at least one other call control server different from the call control server if the media session has been established.

Abstract: A method for creating a high efficiency, error minimizing code is provided. In addition, an apparatus having a high efficiency, error minimizing code is provided. In particular, the present invention provides a high efficiency, error minimizing code for use in connection with systems having a communication channel in which identifiable dominant errors occur, and that is used to transmit data that may be usefully applied in the system even though the received signal is not exactly equal to the original signal. Furthermore, the present invention provides a code that may be used to constrain the effects of dominant errors in a communication channel.