Abstract: A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.

Abstract: The present invention provides a decoding method and device for Reed-Solomon (RS) codes. The method includes the following steps: A: filling data to be decoded in a byte interleaver by column in turn; B: performing cyclic shift to data in a check region of the byte interleaver by row and/or by column, so as to make the data of each row in the check region become check data in sequence of data of corresponding row in an information region of the byte interleaver; C: performing RS decoding by row method, and writing information data of each row obtained after decoding into the corresponding row in the information region of the byte interleaver in turn; and D: reading business data of the decoded information data from the information region of the byte interleaver by column. The method and device of the present invention achieve the best interleaving effect.

Abstract: A method of detecting errors in road characteristics in a transportation network database includes collecting sequential location measurements from probes traversing between two end points, fitting trace segments having a curved or linear shape between the sequential location measurements collected from the probes to form a probe trace, comparing a position of the probe traces with a position of a calculated path between the two end points, where the calculated path is formed from linked transportation network segments each of the linked transportation segments having a curved or linear shape, where the calculated path follows the road characteristics defined by the attributes associated with the linked transportation segments, and identifying a potential error in the attributes if a probe trace deviating in position from the calculated path is greater than a deviation threshold.

Abstract: A system and method for processing keystrokes made while operating a medical device to prevent keypad entry errors. The key press-to-press time is monitored and a subsequent key press rejected if the actual key press-to-press time is shorter than a key press-to-press limit. The actual key inactive time between the release of a key and the subsequent press of a key is compared to an inactive time limit. The subsequent key press is rejected if the actual inactive time is shorter than the inactive time limit. Alerts are provided and further key presses are ignored until the operator presses a CLEAR key. The active time of a key press is monitored and compared to an active time limit. If the actual key press active time exceeds the key press active time limit, an alert is provided but the key press is recognized. An adaptive approach is disclosed in which key presses of an operator are monitored and timing limits modified in accordance with the keying patterns of that operator.

Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: In an information processing device, error detection information is generated from additional information and a header is generated from error detection information. An encoded header is then generated by appending a header-error correction code to the header and encoded additional information is generated by appending an information-error correction code to the additional information. Finally, an information-appended image is generated by integratedly appending the encoded header and the encoded additional information to the target image.

Abstract: A method of deriving an indicator of the signal quality in an in-service packet-based network at least having means to detect errors in packets and means to determine the overall amount of network traffic received. The method comprises the steps of: obtaining a value of the number of packets received having errors therein; obtaining a value of the overall amount of the network traffic received; calculating the indicator of signal quality (eBER) using the ratio of the number of packets received having errors therein to the overall amount of network traffic received.

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract: A method of wireless data communication between a hearing instrument and another device, includes receiving N data packages A1, A2, . . . , AN, wherein the N data packages are obtained by dividing a data package D, receiving data package C, wherein the data package C is formed as a function of A1, A2, . . . , AN in accordance with a relationship C=F (A1, A2, . . . , AN), performing error detection, and recovering AE, one of the data packages A1, A2, . . . , AN that contains an error, in accordance with a relationship AE=R(A1, A2, . . . , C, . . . , AN), in which A1, A2, . . . , C, . . . , AN indicates that the data package C is used in place of AE in a list of arguments for the function R.

Abstract: A method for determining a transport block size and a signal transmission method using the same are disclosed. When the signal transmission method constructs a transport block size combination by predetermining the transport block size, it prevents the insertion of any dummy bits in consideration of the limitation of an input bit length of an encoder during an encoding step. If a CRC is attached to the transport block and the transport block is segmented into a plurality of code blocks, the signal transmission method can establish a length of the transport block in consideration of a length of the CRC attached to each code block.

Abstract: A duplicate-aware disk array (DADA) leaves duplicated content on the disk array largely unmodified, instead of removing duplicated content, and then uses these duplicates to improve system performance, reliability, and availability of the disk array. Several implementations disclosed herein are directed to the selection of one duplicate from among a plurality of duplicates to act as the proxy for the other duplicates found in the disk array. Certain implementations disclosed herein are directed to scrubbing latent sector errors (LSEs) on duplicate-aware disk arrays. Other implementations are directed to disk reconstruction/recovery on duplicate-aware disk arrays. Yet other implementations are directed to load balancing on duplicate-aware disk arrays.

Abstract: A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract: A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space.

Abstract: A method of operating a wireless communications system, comprises encoding (12) information into a low rate code word, providing (20) at least two spatial sub-streams comprising different combinations of bits remaining after puncturing of the low rate code word, simultaneously transmitting (22) each of the at least two spatial sub-streams by way of a respective radio channel, receiving (24) the at least two spatial sub-streams, applying (28) a decoding process to the received at least two spatial sub-streams, and, if the decoding process is unsuccessful, transmitting simultaneously further spatial sub-streams comprising different combinations of bits remaining after puncturing of the low rate code word, at least one of the further spatial sub-streams being a not previously transmitted combination of bits remaining after puncturing of the low rate code word, receiving the further spatial sub-streams and applying the decoding process to the originally received at least two spatial sub-streams and the further su

Abstract: A decoding device includes a first receiving section for receiving a data packets, a second receiving section for receiving a plurality of error correction packets which includes matrix configuration information regarding the plural data packets, a deciding section for deciding a number of packets to be accumulated to restore a lost data packet, based on the matrix configuration information, an accumulating section for accumulating the data packets received by the first receiving section in the number of packets to be accumulated, and a restoring section for, when a loss of any of the data packets received by the first receiving section is detected, restoring the lost data packet by using at least one of the data packets and the error correction packets.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: Certain aspects of a method and system for interlocking data integrity for network adapters are disclosed. Aspects of one method may include executing a plurality of interlocking checks within a network adapter. Each interlocking check may comprise receiving a plurality of input check values associated with a plurality of input data packets corresponding to a first protocol. A plurality of check values may be generated which are associated with the plurality of input data packets and a plurality of output data packets corresponding to a second protocol. The data integrity of the plurality of input data packets and the plurality of output data packets may be validated based on one or more comparisons between one or more of the generated plurality of check values and one or more of the received plurality of input check values.

Abstract: A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams and erasure attributes associated with the datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a frame table (400) and to create codewords, the decoder storing the datagrams in table columns to create codewords in table rows, correcting the codewords, and configured to store the erasure attributes in an erasure table (552). The erasure table is characterized in that it comprises a plurality of entries (560), each of which is associated with a column of the frame table. Each entry is comprised of a plurality of elements (570).

Abstract: An IC card is provided that is capable of identifying a communication type of incoming data received by non-contact communication. The IC card includes: an error detection portion that, for each of a plurality of communication types, performs error detection of incoming data based on an encoding format defined by each of the communication types; and a type identification portion that identifies, among the plurality of communication types, a communication type in which error information is not detected by the error detection portion as a communication type of the incoming data.

Abstract: A system for use in one-way communications takes data from a source and parses it into work units. The work units may have a fixed size. The data of the work units is given to a redundant array of independent disks (RAID) library. The RAID library applies parity to the data and produces a number of output streams. Each stream includes data from the work units and redundant data from the parity application. The streams are combined and sent over a network. The inverse parity is applied on the receiving side to recreate the data. The redundant data is used in place of any data having an error condition, such as being lost or corrupted. The data is reconstructed on the receiving end without the need to resend data.

Abstract: An apparatus and a method for decoding bits of a received signal in a communication system are provided. The method includes determining path metrics of respective states in a trellis corresponding to the received signal, selecting a start state in the trellis for a traceback in a last window of the trellis, repeating the traceback at least twice within the last window, and when the repeating of the traceback is completed, determining the decoded bits of the received signal using a survived path of a last traceback.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set.

Abstract: In a wireless communication system (200), a compact control signaling scheme is provided for signaling the selected retransmission mode and codeword identifier for a codeword retransmission when one of a plurality of codewords (CW1, CW2) being transmitted over two codeword pipes to a receiver (201.i) fails the transmission and when the base station/transmitter (210) switches from a higher order channel rank (231) to a lower order channel rank (241), either by including one or more additional signaling bits in the control signal (240) to identify the retransmitted codeword, or by re-using existing control signal information in a way that can be recognized by the subscriber station/receiver to identify the retransmitted codeword. With the compact control signal, the receiver (201.i) is able to determine which codeword is being retransmitted and to determine the corresponding time-frequency resource allocation for the retransmitted codeword.

Abstract: The disclosure discloses an alarm report method for cascaded equipments, comprises: after receiving link alarm information, a radio equipment determines the source of the link alarm information; the radio equipment selects one link alarm information report mode from multiple predetermined link alarm information report modes according to the result of determining the source; the radio equipment reports the link alarm information to a Radio Equipment Controller (REC) according to the selected link alarm information report mode. The disclosure further discloses an alarm report system and device for cascaded equipments. The disclosure can effectively lower the alarm information processing complexity of an REC and the correlation of alarms.

Abstract: The technology in this application provides for efficient use of a common uplink radio resource, like the common E-DCH resource. A UE lacking a valid radio network identifier, e.g., a UE in an idle mode, receives a data unit and adds error detection bits to generate a new data unit. The new data unit is divided into segments at a lower protocol layer which are provided for transmission to the network via the common uplink radio resource. A network node detects lower protocol layer data unit segments received on the common uplink radio resource and assembles them into an assembled data unit at a higher protocol layer. Error detection bits included with the assembled data unit are used to determine if the assembled data unit includes correctly received data unit segments, e.g., data unit segments from the same UE.

Abstract: Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

Abstract: A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Abstract: A video receiving apparatus includes a receiving unit, a detecting unit, a determining unit, and a control unit. The receiving unit receives a video stream transmitted from a video distribution apparatus and to be reproduced by a video reproducing unit. The detecting unit detects an error occurrence position on the video stream in response to an error occurring during receiving of the video stream. The determining unit determines a reproduction start time based on the error occurrence position detected by the detecting unit and a position of a predetermined synchronization code in the video stream so that reproduction of the video stream is started before the error occurrence position. The control unit transmits a reproduction request including the determined reproduction start time to the video distribution apparatus.

Abstract: Embodiments of a decoder and method of decoding blocks of soft bits in a wireless receiver are generally described herein. Other embodiments may be described and claimed. In some embodiments, a memory is initialized with encoded input data and updated with sums of extrinsic reliabilities. Decoded output data is provided from the memory after a predetermined number of iterations.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.

Abstract: A method is disclosed to debug a computer program. The method provides a computer program comprising source code, and a listing of that source code. The method further provides a computing device comprising a data storage medium, and stores the computer program in that data storage medium. The method then runs the computer program, and subsequently detects an error condition. The method creates and saves to the data storage medium a dump file comprising (N) save areas. Using information abstracted from the dump file and the source code listing, the method reproduces the source code execution at the time the error condition was detected.

Abstract: A failure determination apparatus for a vehicle includes: a failure determination element configured to determine that failure occurs at the vehicle when a state with failure detection continues for a first period, and to determine that the failure is resolved when a state without the failure detection continues for a second period; a notification element configured to notify failure information to an external device when the failure determination element determines that the failure occurs at the vehicle; a repair completion detection element configured to detect completion of repair of the vehicle with respect to the failure; and a short-cut element configured to shorten the second period when the repair completion detection element detects the completion of repair of the vehicle.

Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level.

Abstract: A method for creating cyclic permutation matrices P (810), with an arbitrary size Z×Z set by a parameter Z5 and which are used to create one or more LDPC related matrices in OFDMA systems, comprising: defining an integer value Z; creating an initial matrix (810); creating a matrix (810) by using cyclic shifts to each row; repeating stage 3, up to Z?2 times as required, thus creating up to Z?2 matrices: P(o) . . . P(Z?I); creating an additional stairs matrix P(st). A method for using cyclic per-mutation matrixes P (840), with a fixed size Z×Z set by a parameter Z, and which are used to create one or more LDPC related matrices (820) in OFDMA systems, comprising: defining an integer value Z; storing in memory means an initial matrix (810) and its cyclic shifts permutations (840), thus keeping memory means matrices: P(o) . . . P(Z?I); storing an additional stairs matrix P(st) (840); using these matrices (810) to create LDPC related matrices (840) or LDPC operations.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.

Abstract: Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame.

Abstract: Data is decoded by obtaining a cost function. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Processing related to error correction decoding is performed on the selected group of check nodes.

Abstract: Requests for retrieval of data items from another data processing apparatus include embedded objects having executable class functions for performing operations at the target data processing apparatus. This has the advantages of the request implicitly sending data as well as requesting data and allows the request to perform a test on data within an object (such as a comparison with parameters of the request to determine whether the request may be satisfied). Objects within the request may be embedded within each other with different encryption and compression applied to the different objects. As well as achieving communication efficiencies, the ability to selectively encrypt components of a request may be used to provide greater security. For example, a store may be able to interpret the request, while credit details may be separately encrypted such that only a bank may decrypt that subcomponent of the request.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: A video transmitting apparatus includes a providing unit configured to provide retransmission request information including information for retransmitting video information to be transmitted to a video receiving apparatus, a control unit configured to perform connection control for communication with the video receiving apparatus, a transmitting unit configured to transmit the retransmission request information provided by the providing unit and the video information to the video receiving apparatus, through communication for which connection control is performed by the control unit, a receiving unit configured to receive a retransmission request based on the retransmission request information, the retransmission request being transmitted from the video receiving apparatus, and a retransmitting unit configured to retransmit a specific part of the video information in accordance with the retransmission request received by the receiving unit.

Abstract: The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.

Abstract: A method for processing noise interference in a serial advanced technology attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: Methods and apparatus are provided for controlling decoding in a receiver. A codeword is received and decoded. It is determined whether the decoding is a decoding success or a decoding failure. A number of unreliable bits of the codeword is determined when the decoding is the decoding failure. Iterative decoding is performed when the number of unreliable bits is less than a first threshold value.

Abstract: An error rate sensitive error correction (ERSEC) system acting on product code is disclosed herein that improves error correction effectiveness by allocating error correction resources based on error susceptibility. The ERSEC system acts on vectors (bits or multiple-bit symbols) of a data matrix arranged from a data sequence. The ERSEC system obtains a signal-to-noise (SNR) profile that includes different SNR domains, assigns at least two vectors of the same dimension to different SNR domains, and allocates a level of error correction for the assigned vectors based on the SNR magnitudes of the assigned-to SNR domains.

Abstract: Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. If an error is detected, a data integrity signature may be corrupted. A completion signature may be written. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature and completion signature checked.

Abstract: A method for detecting a persistent error in a digital memory is provided. Error location information for errors detected in the digital memory is received. A group of the errors that are associated with a same error position is identified from the error location information. A number of the errors of the group that are associated with a same area of the digital memory is identified. A persistent error is determined based upon the number of the errors of the group.

Abstract: A filtering method, system, and equipment applied in digital communication technologies are disclosed in the embodiments of the present invention. The filtering method of the present embodiments includes: acquiring filtering coefficients of a part of all subcarriers according to data transmission errors; acquiring filtering coefficients of remaining subcarriers through an interpolation algorithm according to the filtering coefficients of the part of subcarriers; and finally, filtering the data corresponding to the multiple subcarriers according to the filtering coefficients of the part of subcarriers and the filtering coefficients of the remaining subcarriers. The part of subcarriers may be selected at a regular interval, or may be subcarriers which are located at a motion value away from the part of subcarriers selected in the previous update of the filtering coefficients. The method of the present embodiments reduces the amount of operation and hardware expenditure, and saves the cost.

Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.