Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A receiver can include a sampler module for sampling a data-bearing input signal to extract data encoded in the data-bearing analog input signal. The sampling results in data-symbol sequences. The data-symbol sequences can be used to identify error events. The identified error events can be used as a basis for adjusting tap coefficients. The tap coefficients can be used in setting reference levels for the sampler module.

Abstract: A method and apparatus are capable of masking a signal loss condition. According to an exemplary embodiment, the method includes steps of receiving a signal, detecting a period of loss of the signal, and enabling a received portion of the signal to be reproduced continuously and causing a portion of the signal lost during the period to be skipped.

Abstract: A method begins by a processing module receiving a plurality of requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices when the data is broadcast and in response to a request of the plurality of requests. The method continues with the processing module generating a unique retrieval matrix for each of the plurality of requests based on an identity of a requesting device and the error coding dispersal storage function to produce a plurality of unique retrieval matrixes. The method continues with the processing module storing the plurality of sets of encoded data slices and the plurality of unique retrieval matrixes in a dispersed storage network memory as a plurality of unique copies of the data.

Abstract: Maintaining bandwidth in links betweens servers and storage arrays comprising a device. The device establishes the links. The device identifies a first link from the links. The first link has a high response time. The device transmits a plurality of data packets on the first link. Each data packet is associated with a corresponding acknowledgment (ACK). The transmission is performed without waiting for the corresponding ACK to be received. The device tracks the ACK received in response to each of the transmitted data packets. The device detects a failure of the first link. In response to the detection, the device identifies invalid data packets. The invalid data packets comprise data packets transmitted on the first link after the detected failure.

Abstract: An information processing apparatus includes an MMU that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses that are addresses in physical memory and virtual addresses that are addresses in virtual memory. Stored in a RAM are page table information indicating a page table, as well as error detection information attached to the page table information for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU. A CPU detects the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU on the basis of the error detection information.

Abstract: In one embodiment, a first set of digital data (e.g., an image) is tested for the presence of a certain feature (e.g., a certain face), yielding one of two outcomes (e.g., not-present, or present). If the testing yields the first outcome, no additional testing is performed. If, however, the testing yields the second outcome, further testing is performed to further check this outcome. Such further testing is performed on a second set of digital data that is based on, but different from, the first set of data. Only if the original testing and the further testing both yield the same second outcome is it treated as a valid result. A variety of other features and arrangements are also detailed.

Abstract: The invention relates to a method for protecting a sensitive operation by checking the integrity of at least a subset of the data manipulated by the sensitive operation. Data to be checked are divided into blocks, an intermediate integrity check value being computed for each block, the intermediate integrity check values being computed in random order. The invention also relates to a cryptographic device wherein at least one sensitive operation of the cryptographic device is protected by a method according to the invention.

Abstract: To decode a manifestation of a codeword in which K information bits are encoded as N>K codeword bits, messages are exchanged between N bit nodes and N?K check nodes. During computation, messages are expressed with a full message length greater than two bits. In each iteration, representations of at least some of the exchanged messages are stored. For at least one node, if representations of messages sent from that node are stored, then the representation of one or more of the messages is stored using at least two bits but using fewer bits than the full message length, and the representation of one other message is stored with full message length. Preferably, the messages that are stored using fewer bits than the full message length are messages sent from check nodes.

Abstract: A path of a signal extends from an initial point through first and second cells to an end point. The signal is supplied as a first signal to the first cell and outputted therefrom as a second signal. The signal is supplied as a third signal to the second cell and outputted therefrom as a fourth signal. First delay amounts of the signal in the first cell and a transition time of the second signal are calculated based on a transition time of the first signal and a voltage supplied to the first cell. Second delay amounts of the signal in the second cell and a transition time of the fourth signal are calculated similarly. Here, the transition time of the second signal is set to be a transition time of the third signal. Jitter values in the end point are calculated based on the first and second amounts.

Abstract: A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory.

Abstract: An apparatus for efficiently transmitting and receiving uncompressed AV data by using UEP during high-frequency wireless communication, as well as a transmission frame structure to which the UEP is applied are provided. A method of transmitting uncompressed AV data includes determining whether a transmission efficiency of uncompressed AV data drops below a threshold while the uncompressed AV data is transmitted; deciding whether to use a UEP mode if it is determined that the transmission efficiency has dropped below the threshold, the UEP mode indicating a manner of dividing bits, the bits constituting the uncompressed AV data, into significant bits and non-significant bits; and retransmitting the uncompressed AV data by using the UEP mode based on decision regarding use of the UEP mode.

Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.

Abstract: A device for using a programmable component carrying out at least one logical function in a radiative environment includes: a mechanism for error detection in a data-storing working memory space actually serving to carry out each logical function of the device through use of data stored in at least one reference memory space storing a data copy implemented by at least one logical function; a mechanism blocking at least one output of at least one logical function of the component for which an error in the data implemented by the logical function is detected by the mechanism for detection; and a mechanism correcting each error detected in the working space.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a decoder circuit and a scalar circuit. The decoder circuit is operable to perform a data decoding algorithm by processing at least one decoder message, and the scalar circuit is operable to multiply the decoder message by a variable scalar value.

Abstract: A method of error detection for a data packet, the method comprising the steps of: i) identifying a set of non-compliances (N), the non-compliances being illegal bit sequences according to a coding standard; ii) identifying a first subset (N+) of non-compliances that are to be treated as errors; iii) identifying a second subset (N.) of non-acceptable near-compliances; iv) decoding the data packet according to the coding standard; and v) adaptively deciding based on the first and second subsets whether to treat a detected non-compliance within the decoded data packet as an error or as an acceptable near-compliance.

Abstract: In a magnetic data processing device, an input part sequentially receives magnetic data output from a magnetic sensor. A storage part stores a plurality of the magnetic data as a data set of statistical population. An index derivation part derives a distribution index of the data set of the statistical population. A reliability determination part determines whether or not reliability of the data set of the statistical population is acceptable based on the distribution index and a decision criterion. A decision criterion setting part increases strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is acceptable, and decreases the strictness of the decision criterion when the reliability determination part determines that the reliability of the data set of the statistical population is unacceptable.

Abstract: A power control apparatus is provided that includes a calculation unit, a detection unit, a storage unit, a selection unit and an execution unit. The detection unit detects whether a required spare capacity is short, based on the required spare capacity, the spare power, and the total spare power capacity. The storage unit stores power control operation items. The selection unit selects power control operation items if the required spare capacity is short. The execution unit executes application operation of one or more the power control operation items until the required spare capacity becomes available, and executes waiting operation of one or more power control operation items executing the application operation if the required spare capacity is available.

Abstract: A receiver for a mobile communication device comprises an primary detector for generating an initial sequence estimate comprising a plurality of initial symbol estimates from a received symbol sequence corrupted by intersymbol interference, and a secondary detector to receive said initial sequence estimate and to output a final sequence estimate comprising a plurality of final symbol estimates. The secondary detector comprises a sequence generator configured to generate one or more revised sequence estimates by replacing at least one initial symbol estimate in said initial sequence estimate with a corresponding nearest neighbor symbol in each of said revised symbol estimates; an error calculator to compute error metrics for said revised sequence estimates; and a selection circuit to compare error metrics for said initial and revised sequence estimates and to output one of said initial or revised sequence estimates as said final sequence estimate based on said error metrics.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.

Abstract: Described herein are embodiments of methods and systems for detecting communications of a first meter board by a second meter board and correlating the time and duration of the communications with metrology data gathered during that time. In accordance with one aspect, a method is provided for diagnosing metrology errors caused by communication activities of a meter board. In one embodiment, the method includes: receiving a signal, wherein the signal indicates a presence of communication activities between a first processor of a meter and another device over a network; recording a time of receipt and duration of the communication activities between the first processor of the meter and another device over the network; and correlating the time and duration of the communication activities between the first processor of the meter and another device over the network with metrology data of the meter measured at the same time and duration.

Abstract: Techniques are described herein that are capable of automatically allocating clients for testing a software program. For instance, a number of the clients that are to be allocated for the testing may be determined based on a workload that is to be imposed by the clients during execution of the testing. For example, the number of the clients may be a minimum number of the clients that is capable of accommodating the workload. In accordance with this example, the minimum number of the clients may be allocated in a targeted environment so that the test may be performed on those clients. Additional clients may be allocated along with the minimum number of the clients in the targeted environment to accommodate excess workload.

Abstract: The invention relates to a method for checking the integrity of a set of data packets received by a receiving communication device from a sending communication device, the data packets of the set being received in unpredictable order. The invention also relates to a communication device implementing a method according to the invention, in particular to a smart card.

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract: An exemplary memory device has at least one memory chip that stores data and error correcting information. An error detecting circuit in the memory chip performs a calculation on the data and error correcting information to obtain error detection information indicating the locations of bit errors in the data. The uncorrected data and the error detection information are output from the memory chip. The uncorrected data and error detection information may also be output from the memory device, or the memory device may include a memory controller chip with an error correcting circuit that uses the error detection information to correct the bit errors and outputs corrected data from the memory device.

Abstract: The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is implemented so that the hardware resources can be reused in different modes. In addition, memory access is achieved via routing networks with fixed interconnections and memory address generators, the complexity of the hardware implementation is reduced accordingly. Further, the present invention provides an early termination function with which the iterative operations can be terminated early when a threshold is reached so that the power consumption can be thus reduced. The hardware resources for early termination shares a part of hardware resources with an encoder according to the present invention so that the complexity of the hardware implementation can also be reduced.

Abstract: A decoding device is provided, which can minimize the number of coded data addition requests by the decoding device, reduce processing time to prevent delay, and minimize frame rate reduction. The decoding device performs data reproduction by performing error correction of data of a predicted image using coded data which is an error correction code generated based on original data. The decoding device includes a coded bit receiving part, a preset value generating/updating part, a decoding part that performs a decoding process based on a preset value or a predicted value, and coded bits, and a bit addition request determining part that determines whether or not there is a need to request additional coded bits from decoding process results from the decoder. When it is determined to perform a decoding process with additional coded data, the preset value generating/updating part updates the preset value based on previous decoding process results.

Abstract: A teletext decoder is provided which is suitable for decoding a packet of teletext signal to generate a teletext. The teletext decoder includes an error judgment device for judging the accuracy of a plurality of sliced bits, and correcting an error occurrence bit in the sliced bits on the basis of a plurality of sampling points and a slicer level when the plurality of sliced bits are incorrect.

Abstract: A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit values may be removed from the possible decoding paths to consider, and decoding the encoded data bits by selecting a decoding path from remaining decoding paths of the possible decoding paths that were not removed. A-priori bit values may be extracted from various messages, such as DL-MAP, UL-MAP, RNG-REQ, and BW-REQ messages.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: Disclosed herein is a semiconductor integrated circuit capable of detecting an abnormality that can cause a malfunction in signal transmission via an isolation element and of issuing a stop signal to the target to be controlled. The semiconductor integrated circuit includes a transmission circuit generating and outputting a transmission signal reflecting transmission data supplied from outside, a reception circuit reproducing the transmission data based on a reception signal, an isolation element isolating the transmission circuit from the reception circuit and transmitting the transmission signal as the reception signal, an abnormality detection part detecting an abnormality that can cause a malfunction in signal transmission via the isolation element, and a control part outputting a stop signal if the abnormality detection part detects the abnormality, regardless of the transmission data supplied to the transmission circuit from outside.

Abstract: A communication method transmits a detection signal including a valve ID and detection information, receives the detection signal, performs error detection on the valve ID and detection information, and uses the valve ID and detection information when there is no error. The communication method generates third data corresponding to the detection information in accordance with a predetermined rule to increase redundancy of the detection information, generates computed data by performing an exclusive disjunction logic operation with the valve ID and third data, transmits the detection signal that includes the computed data and detection information, receives the detection signal, retrieves the third data corresponding to the detection information from the detection information, restores the valve ID by performing an exclusive disjunction logical operation with the computed data and the third data, and determines whether a restored valve ID conforms to a stored first data.

Abstract: A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.

Abstract: A fault diagnosis apparatus and method capable of simultaneously detecting the fault of a multiplexer and the fault of an A/D converter and isolating and identifying causes of these faults, the multiplexer and the A/D converter being used in a multi-channel analog input/output circuit. Test-voltage values are inputted from a diagnosis-voltage input unit into the multiplexer and the A/D converter constituting an analog-signal conversion unit, the multiplexer having plural channels, the A/D converter converting outputs from the multiplexer into digital signals, the test-voltage values being different from each other for each channel of the multiplexer. Comparisons are made between the digital voltage values and the test-voltage values inputted, the digital voltage values being outputted for each channel of the multiplexer. From this comparison result, it is judged whether the multiplexer is at fault or the A/D converter is at fault.

Abstract: In an operation of two qubit gate having failure information related to success or failure, by using a code to concatenate N-error-correcting code transversally executing a Pauli gate, a Hadamard gate and a CNOT gate, an error-correction is executed by an error-correcting teleportation, and the CNOT gate is executed to an encoded qubit by the error-correcting teleportation. In Bell measurement of the error-correcting teleportation, when a measurement result of non-encoded qubit is processed, by suitably defining failure information of the encoded qubit of level (l+1) from the failure information of encoded qubits of level l, the measurement result of the encoded qubit of each level is determined, and the failure information of the encoded qubit of each level is defined. As a result, a measurement result of a logical qubit as the encoded qubit of the highest level is determined.

Abstract: The invention relates to error control for point-to-multipoint (PTM) transmissions of content data over a radio interface. A method embodiment for controlling a PTM transmission in a PTM-enabled network comprises the steps of receiving and storing redundancy data at a dedicated redundancy data storage in a radio access network, wherein the redundancy data are provided for a correction of transmission errors in the content data resulting from the transmission of the content data without the redundancy data over one or more radio interfaces; receiving a request for redundancy data from a redundancy data control node; and responding to the redundancy data request by providing at least a portion of the redundancy data.

Abstract: A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise injection circuit. The noise injection circuit is operable to: determine a difference between a first data output and a second data output to yield an error; and augment an interim data with a noise value corresponding to the error to yield a noise injected output. The interim data may be either the first data output or the second data output.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.

Abstract: A transmitter generates an encrypted data by processing a specific data according to a specific transmission mode, generates a verification code according to the specific transmission mode, and provides a protocol data unit according to the encrypted data and the verification code. After transmission, a receiver decodes the protocol data unit and determines whether the decrypted data of the protocol data unit matches the verification code, thereby providing error detection for wireless transmission.

Abstract: A method for correcting at least one error in a data transmission over a packet-based communication network includes the steps of: generating a sequence of data packets for transmission over the packet-based communication network, the sequence of data packets being arranged into a plurality of packet frames, each of at least a subset of the packet frames including at least a primary data packet and a number of redundant data packets which is a function of a prescribed redundancy pattern, the subset of packet frames having a non-uniform distribution of redundant data packets therein; transmitting the sequence of data packets over the communication network; and recovering at least one missing data packet in the sequence of data packets using at least one corresponding redundant data packet in at least one subsequently received packet frame when the missing data packet is identified in a receiver of the sequence of data packets.

Abstract: In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.

Abstract: Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A method for correcting read data error of a nonvolatile memory device, the error correction method including performing a first read operation of applying a first non-selection read voltage to a plurality of unselected memory cells to read a plurality of selected memory cells, performing a second read operation of applying a second non-selection read voltage less than the first non-selection read voltage to the unselected memory cells to read the selected memory cells, and comparing data sensed in the first and second read operations to detect error locations of read data.

Abstract: The invention provides a method, device and system for encoding and decoding data. The method includes receiving information including data units, storing the data units into a memory and encoding the data units by performing a plurality of store and exclusive-or operations on the data units resulting in encoded symbols Sn, where n is a positive integer.

Abstract: An error correction coding device includes a time divider for dividing field data of L packets into N data packets and (L-N) parity packets, a first RS (Reed-Solomon) encoder adding parities of a predetermined number of bytes to the data packets, respectively, a storage unit for storing the data packets, and a second RS encoder generating parity packets corresponding to the stored data packets. An error correction decoding device includes a first RS decoder correcting errors in a horizontal direction of the field data using parities of the predetermined number of bytes included in the L packets, a storage unit storing the error-corrected data packets, and a second RS decoder correcting errors in a vertical direction of the field data using the parity packets. Thus, the error correction can be strongly performed using parities existing in the horizontal and vertical directions with respect to the field data.

Abstract: An error correction coding device includes a time divider for dividing field data of L packets into N data packets and (L-N) parity packets, a first RS (Reed-Solomon) encoder adding parities of a predetermined number of bytes to the data packets, respectively, a storage unit for storing the data packets, and a second RS encoder generating parity packets corresponding to the stored data packets. An error correction decoding device includes a first RS decoder correcting errors in a horizontal direction of the field data using parities of the predetermined number of bytes included in the L packets, a storage unit storing the error-corrected data packets, and a second RS decoder correcting errors in a vertical direction of the field data using the parity packets. Thus, the error correction can be strongly performed using parities existing in the horizontal and vertical directions with respect to the field data.