Short Channel Insulated Gate Field Effect Transistor Patents (Class 257/327)
  • Patent number: 8896060
    Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
  • Patent number: 8890261
    Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided. The field effect transistor device includes a source region; a drain region; a plurality of fins connecting the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each fin having a width of between about ten nanometers and about 40 nanometers; and a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Haensch, Katherine Lynn Saenger
  • Patent number: 8884368
    Abstract: Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 8884361
    Abstract: A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Shirai, Nobuyoshi Matsuura
  • Patent number: 8878270
    Abstract: A semiconductor memory device including a bit line, a word line, a transistor, and a capacitor is provided. The transistor includes source and drain electrodes; an oxide semiconductor film in contact with at least both top surfaces of the source and drain electrodes; a gate insulating film in contact with at least a top surface of the oxide semiconductor film; a gate electrode which overlaps with the oxide semiconductor film with the gate insulating film provided therebetween; and an insulating film covering the source and drain electrodes, the gate insulating film, and the gate electrode. The transistor is provided in a mesh of a netlike conductive film when seen from the above. Here, the drain electrode and the netlike conductive film serve as one and the other of a pair of capacitor electrodes of the capacitor. A dielectric film of the capacitor includes at least the insulating film.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 8877625
    Abstract: One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jun Lian
  • Patent number: 8872282
    Abstract: A semiconductor device is implementated that includes a source region, multiple elongated drain regions, a channel region, a source electrode, a drain electrode, and a gate electrode. The source region is a flat planar region formed on a compound semiconductor layer. The multiple elongated drain regions are formed so that they are each electrically isolated from each other on the compound semiconductor layer. The channel region is formed so that it contacts one side of the source region and is electrically isolated from the source region and the multiple elongated drain regions. The source electrode is formed at least in a portion on top of the source region. The drain electrode is formed so that it is connected electrically to the multiple elongated drain regions. The gate electrode is formed so that it is connected electrically to the multiple channel regions.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jeoungchill Shim
  • Patent number: 8860128
    Abstract: A semiconductor device includes a first pillar, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The third pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The first-conductive type region of each of the second pillar and the third pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type region of a respective one of the second pillar and the third pillar.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: October 14, 2014
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Tomohiko Kudo
  • Patent number: 8846478
    Abstract: A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Publication number: 20140264555
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8836035
    Abstract: An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Hak-Lay Chuang, Lee-Wee Teo, Han-Gan Chew
  • Patent number: 8828820
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 9, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8809919
    Abstract: A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuo Hashimi, Hidekazu Sato
  • Patent number: 8809940
    Abstract: A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen
  • Patent number: 8809939
    Abstract: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 19, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Akihito Tanabe
  • Patent number: 8803224
    Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 12, 2014
    Assignee: SK hynix Inc.
    Inventor: Kyoung Bong Rouh
  • Patent number: 8796758
    Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 8796093
    Abstract: A FinFET structure is fabricated using a process that facilitates the effective doping of fin structures. A doped layer is annealed to drive dopants into the fins. The doped layer is removed following annealing. Subsequent to removal of the doped layer, doped semiconductor material is grown epitaxially on the side walls of the fins, forming doped regions extending laterally from the fin side walls. Growth of the semiconductor material may be timed to form diamond-shaped, unmerged epitaxy.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140209997
    Abstract: A thin film transistor based on carbon nanotubes includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The work-functions of the source electrode and of the drain electrode are different from that of the semiconductor layer, enabling the creation of both p-type and n-type field-effect transistors.
    Type: Application
    Filed: June 26, 2013
    Publication date: July 31, 2014
    Inventors: QING-KAI QIAN, QUN-QING LI
  • Patent number: 8790978
    Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akihiro Usujima, Shigeo Satoh
  • Publication number: 20140203348
    Abstract: Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 24, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Heesoo Kang, Sungil Park, Changwoo Oh
  • Patent number: 8779502
    Abstract: According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Atsuhiro Kinoshita, Masahiro Kiyotoshi, Daisuke Hagishima, Koichi Muraoka
  • Patent number: 8772860
    Abstract: A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
  • Patent number: 8766353
    Abstract: An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Isaac Lauer, Ghavam G. Shahidi
  • Publication number: 20140159139
    Abstract: A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 12, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay CHUANG, Lee-Wee TEO, Ming ZHU
  • Patent number: 8735981
    Abstract: Disclosed is a transistor component having a control structure with a channel control layer of an amorphous semiconductor insulating material extending in a current flow direction along a channel zone.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Schmidt
  • Publication number: 20140131790
    Abstract: A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 15, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20140117435
    Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
    Type: Application
    Filed: January 7, 2014
    Publication date: May 1, 2014
    Applicant: Spansion LLC
    Inventors: Chuan LIN, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan, Kenichi Ohtsuka, Angela T. Hui, Scott Allan Bell
  • Patent number: 8710557
    Abstract: The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: April 29, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Qianqian Huang, Zhan Zhan, Xin Huang, Yangyuan Wang
  • Publication number: 20140110783
    Abstract: A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei ZHANG
  • Patent number: 8704290
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Patent number: 8704332
    Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
  • Publication number: 20140097487
    Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: ADVANCED ION BEAM TECHNOLOGY, INC.
    Inventors: Tzu-Shih YEN, Daniel TANG, Tsungnan CHENG
  • Patent number: 8692315
    Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 8, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Hiroshi Kumano
  • Patent number: 8692316
    Abstract: One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: April 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ruilong Xie
  • Publication number: 20140084359
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a first electrode, and a contact region. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The first electrode has a first and a second portion. The first portion is provided in a first direction and has a lower end being positioned below a lower end of the third semiconductor region. The second portion is in contact with the first portion and is provided on the third semiconductor region. The contact region is provided between the first portion and the second semiconductor region and is electrically connected to the first electrode and the second semiconductor region.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 27, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori TSUCHIYA, Takashi Shinohe
  • Patent number: 8680607
    Abstract: Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: March 25, 2014
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Jun Zeng, Mohamed N. Darwish
  • Patent number: 8680606
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune
  • Publication number: 20140077286
    Abstract: According to one embodiment, a field-effect transistor is provided with a first conductivity-type first semiconductor layer, a source layer formed of a second conductivity-type semiconductor, a drain layer formed of a second conductivity-type semiconductor, and a gate electrode. The source layer is located on the first semiconductor layer. The drain layer is also located on the first semiconductor layer and is separated from the source layer. The gate electrode is located adjacent to the side wall of the drain layer which faces the source layer, and may also be located adjacent to the side wall of the source layer facing the drain layer, and on the first semiconductor layer with a gate insulating film formed therebetween. The upper surface of the gate electrode is recessed with respect to at least the upper surface of the drain layer.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiko KUBO
  • Patent number: 8674433
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8664652
    Abstract: A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ?r/d is greater than or equal to 0.08 (nm?1) and less than or equal to 7.9 (nm?1) when the relative permittivity of a material used for the gate insulating layer is ?r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 ?m.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Daisuke Kawae
  • Patent number: 8659077
    Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes a channel structure including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Aritra Dasgupta, Unoh Kwon, Sean M. Polvino
  • Patent number: 8659069
    Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Sung-Ho Heo, Jae-Ho Choi, Hun-Hyeong Lim, Ki-Hyun Hwang, Woo-Sung Lee
  • Publication number: 20140042521
    Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz
  • Patent number: 8648410
    Abstract: An electronic device can include a gate electrode and a gate tap that makes an unlanded contact to the gate electrode. The electronic device can further include a source region and a drain region that may include a drift region. In an embodiment, the gate electrode has a height that is greater than its width. In another embodiment, the electronic device can include gate taps that spaced apart from each other, wherein at least some of the gate taps contact the gate electrode over the channel region. In a further embodiment, at a location where the gate tap contacts the gate electrode, the gate tap is wider than the gate electrode. A variety of processes can be used to form the electronic device.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 11, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Peter Coppens, Eddy De Backer, Freddy De Pestel, Gordon M. Grivna
  • Patent number: 8643100
    Abstract: A FET includes a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile. A semiconductor manufacturing process produces a FET including a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 4, 2014
    Assignee: Broadcom Corporation
    Inventor: Akira Ito
  • Patent number: 8641926
    Abstract: Devices are provided comprising conductive or semiconductive layers comprising compositions comprising aqueous dispersions of polythiophenes having homopolymers or co-polymers of Formula I(a) or Formula I(b) and at least one colloid-forming polymeric acid. Methods of making such compositions and using them in organic electronic devices are further provided.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 4, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Che Hsiung Hsu, Yong Cao, Sunghan Kim, Daniel David Lecloux, Huawen Li, Charles Douglas Macpherson, Chi Zhang, Hjalti Skulason
  • Patent number: 8637375
    Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 28, 2014
    Assignee: NXP B.V.
    Inventors: Gilberto Curatola, Marcus J. H. Van Dal
  • Publication number: 20130341704
    Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.
    Type: Application
    Filed: December 30, 2011
    Publication date: December 26, 2013
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jack T. Kavalieros, Robert S. Chau, Seung Hoon Sung
  • Patent number: 8610204
    Abstract: A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 17, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo