Abstract: A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region.

Abstract: A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

Abstract: A power rectifier includes a stage having a first Tunneling Field-Effect Transistor (“TFET”) having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed.

Abstract: A semiconductor device having high-k gate insulation films and a method of fabricating the semiconductor device are provided. The semiconductor device includes a first gate insulation film on a substrate and the first gate insulation film includes a material selected from the group consisting of HfO2, ZrO2, Ta2O5, TiO2, SrTiO3 and (Ba,Sr)TiO3, and lanthanum (La). Additionally, the semiconductor device includes a first barrier film on the first gate insulation film, a first gate electrode on the first barrier film, and n-type source/drain regions in the substrate at both sides of the first gate electrode.

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Abstract: A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack.

Abstract: According to the present invention, a semiconductor having excellent yield is provided. The semiconductor device (10) of the present invention includes: a base material (die pad) (2), a semiconductor element (3), and an adhesive layer (1) intervening the space between the base material and the semiconductor element (3) to adhere the base material and the semiconductor element. Thermal conductive filler (8) is contained in the adhesive layer (1), and when the content of the thermal conductive filler dispersed in the whole of the adhesive layer is expressed as C, the content of the thermal conductive filler in the region 1 ranging from the interface of the adhesive layer at the side of the semiconductor element to the depth by 2 ?m is expressed as C1, and the content of the thermal conductive filler in the region 2 ranging from the interface of the adhesive layer at the side of the base material to the depth by 2 ?m is expressed as C2, the following formulae are satisfied: C1<C, and C2<C.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract: As disclosed herein, a method for fabricating a nanowire device with improved epitaxy, includes forming a nanowire stack on a substrate, the nanowire stack having one or more sacrificial layers, where the substrate includes a bulk substrate, an oxide layer, and an extremely thin silicon (ETSOI) layer, removing the sacrificial layers, depositing and patterning a gate material over the nanowire stack, the gate material having sidewalls, covering the sidewalls of the gate material with a spacer layer, and epitaxially growing an in-situ doped layer comprised of doped silicon from the ETSOI layer. The ETSOI may have a (100) crystallographic orientation. A pFET source/drain may be epitaxially grown by including an in-situ doped layer of boron doped SiGe. An nFET source/drain may be epitaxially grown by including an in-situ doped layer of phosphorus doped Si:C. A device corresponding to the method is also disclosed herein.

Abstract: A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: The present disclosure provides a semiconductor structure. In accordance with some embodiments, the semiconductor structure includes a substrate, one or more fins each including a first semiconductor layer formed over the substrate, an oxide layer formed wrapping over an upper portion of each of the one or more fins, and a gate stack including a high-K (HK) dielectric layer and a metal gate (MG) electrode formed wrapping over the oxide layer. The first semiconductor layer may include silicon germanium (SiGex), and the oxide layer may include silicon germanium oxide (SiGexOy).

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

Abstract: A number of techniques for determining bit line related defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Defects related to bit line to NAND string contacts are determined by application of an AC stress mode along bit lines, followed by a defect detection operation. If the AC stress is applied to be out of phase on adjacent bit lines, this can also be used to accelerate bit line to bit line defects. The subsequent defect determination phase can include an erase operation followed a read to determine whether the NAND strings of the erased block read as erased, a process that can also be followed by a program and subsequent read to further check for defects.

Abstract: Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

Abstract: An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.

Abstract: An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion.

Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.

Abstract: A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.

Abstract: A method, system and computer program product for generating answers to questions. In one embodiment, the method comprises receiving an input query; conducting a search to identify candidate answers to the input query, and producing a plurality of scores for each of the candidate answers. For each of the candidate answers, one, of a plurality of candidate ranking functions, is selected. This selected ranking function is applied to the each of the candidate answers to determine a ranking for the candidate answer based on the scores for that candidate answer. One or more of the candidate answers is selected, based on the rankings for the candidate answers, as one or more answers to the input query. In an embodiment, the ranking function selection is performed using information about the question. In an embodiment, the ranking function selection is performed using information about each answer.

Abstract: A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

Abstract: In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided.

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

Abstract: The systems and methods described herein include a sensor for suitable for sensing chemical and biological substances. The sensor comprises a semiconductor layer formed in or on a substrate and a channel having nano-scale dimensions formed in the semiconductor layer, where the structure creates an electrically conducting pathway between a first contact and a second contact on the semiconductor layer. In certain preferred embodiments, the nano-scale channel has a trapezoidal cross-section with an effective width and exposed lateral faces, where the effective width is selected to have same order of magnitude as a Debye length (LD) of the semiconductor material of which the semiconductor layer is formed.

Abstract: A method for forming a fin-shaped structure includes the following steps. A pad layer is formed on a substrate. A sacrificial pattern is formed on the pad layer. A spacer is formed on the pad layer beside the sacrificial pattern, wherein the ratio of the height of the spacer to the pad layer is larger than 5. The sacrificial pattern is removed. The layout of the spacer is transferred to the substrate to form at least a fin-shaped structure having a taper profile in the substrate.

Abstract: CMOS devices are fabricated with a channel layer having minimized dopant fluctuation and diffusion. Embodiments include forming a dummy gate, on a substrate, between a pair of spacers, forming, in the substrate, a source and drain separated by a ground plane layer, removing the dummy gate from the substrate, forming a cavity between the pair of spacers, forming, after removal of the dummy gate, a channel layer on the substrate, forming a high-k layer on the channel layer and on side surfaces of the cavity, and forming a replacement gate in the cavity.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.

Abstract: A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.

Abstract: A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.

Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract: An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut.

Abstract: In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device.

Abstract: An assembler receives a circuit device and a mass of conductive material such as a diode, metal material, etc. The assembler bonds a first facing of a circuit device to a substrate. Adjacent to the circuit device, the assembler bonds a first facing of the mass of conductive material to the substrate. The assembler applies an overmold layer of insulation material over the substrate adjacent the circuit device and the mass of conductive material. Subsequent to applying the overmold layer of insulation material, the assembler provides a conductive link between a second facing of the circuit device and a second facing of the mass of conductive material.

Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.