Abstract: The power conversion apparatus includes semiconductor modules and a circuit board on which a control circuit is formed. Each semiconductor module includes signal terminals electrically connected to the circuit board. The signal terminals of each semiconductor module are arranged in a line so as to form a terminal row along a first direction. The semiconductor modules are grouped into upper arm semiconductor modules and lower arm semiconductor modules each connected to a corresponding one of the upper arm semiconductor module. Upper arm terminal rows as the terminal rows of the upper arm semiconductor modules and lower arm terminal rows as the terminal rows of the lower arm semiconductor modules are arranged in a staggered manner along a second direction perpendicular to the first direction and to a third direction in which the signal terminals of the semiconductor modules project, the first, second and third directions being perpendicular to one another.

Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract: A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.

Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.

Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

Abstract: A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A method for manufacturing a semiconductor device includes forming a trench for defining an active region over a semiconductor substrate, forming a doped region by implanting impurities into the trench, forming an oxide film in the trench by performing an oxidation process, forming a nitride film at inner sidewalls of the trench, and forming a device isolation film in the trench.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.

Abstract: A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts.

Abstract: A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.

Abstract: A semiconductor device having a via structure in a stress relief layer is provided. The semiconductor device may include an isolation layer on the circuit region, a stress relief layer on the via region, and a via structure in the stress relief layer and the substrate. The stress relief layer may have a thickness larger than that of the isolation layer and a stepped cross section.

Abstract: One aspect of the invention relates to a semiconductor chip with a semiconductor body. The semiconductor body has an inner region and a ring-shaped outer region. An electronic structure is monolithically integrated in the inner region and has a controllable first semiconductor component with a first load path and a first control input for controlling the first load path. Further, a ring-shaped second electronic component is monolithically integrated in the outer region and surrounds the inner region. Moreover, the second electronic component has a second load path that is electrically not connected in parallel to the first load path.

Abstract: A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer.

Abstract: An embodiment of an electronic system may be provided so as to have superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in PCBs coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions.

Abstract: Approaches for analyzing a power grid of an integrated circuit are described. In one embodiment, a method includes selecting at least one portion of the integrated circuit to be analyzed. A power grid model corresponding to the integrated circuit is retrieved from a database, and a first simulation of the programmable integrated circuit is performed. The first simulation generates a respective waveform of an electrical characteristic over time for each connection of a component within the selected portion to voltage supply or voltage ground. A simulation is performed of the power grid model using the respective waveforms as input stimulus for each connection in the selected portion.

Abstract: A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.

Abstract: Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.

Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Abstract: A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a).

Abstract: A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).

Abstract: Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials.

Abstract: A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern.

Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.

Abstract: A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.

Abstract: A semiconductor device structure and a method for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction crossing the first direction on the semiconductor substrate, the gate line intersecting the fin via a gate dielectric layer; forming a dielectric spacer surrounding the gate line; forming a conductive spacer surrounding the dielectric spacer; and performing inter-device electrical isolation at a predetermined region, wherein isolated portions of the gate line form gate electrodes of respective unit devices, and isolated portions of the conductive spacer form contacts of the respective unit devices.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film.

Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Abstract: Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein.

Abstract: A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region.

Abstract: A flexible active device array substrate including a flexible substrate, an active device array layer, a barrier layer, and a plurality of pixel electrodes is provided. The active device array layer is disposed on the flexible substrate. The barrier layer covers the active device array layer. The barrier layer includes a plurality of organic material layers and a plurality of inorganic material layers. The organic material layers and the inorganic material layers are alternately stacked on the active device array layer. The pixel electrodes are disposed on the barrier layer, and each of the pixel electrodes is electrically connected to the active device array layer.

Abstract: A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate.

Abstract: An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art.

Abstract: The present invention relates to device matching in an integrated circuit. In one embodiment, an integrated circuit of matched devices can include: N main-devices to be matched by 4×K sub-devices configured to form K device arrays, where each of the device arrays includes four sub-device groups arrayed symmetrically around a vertical axis and a horizontal axis, where each of the sub-device groups includes N sub-devices arrayed with equal distance along a direction of the vertical axis, where K and N are integers, and N is larger than two; metal lead wires arrayed in parallel and with equal distance, and configured to connect the main-devices; a common connecting wire configured to connect common nodes of the sub-devices together; and where four sub-devices arrayed in the four sub-device groups, and other sub-devices arrayed in other sub-device groups, are coupled to form 4×K sub-devices to match the main-devices.