Abstract: Substrates are processed, with a high degree of topography, to produce a variety of semiconductors or other devices and are then stretched out, substantially flat, to achieve a significant increase in surface area. Devices made from a contiguous structure of a single, active crystalline material or from non-contiguous structures of multiple materials, such as a combination of dielectrics, thin film metals and active crystalline semiconductors, are fabricated by utilizing anisotropically etched, high aspect ratio configurations of the active material. The structure is then stretched out to achieve a significant increase in surface area, thereby enabling a substantial reduction in the cost of the substrate materials per unit area in the final product.

Abstract: A method for reducing punch-through defects during semiconductor fabrication is disclosed. Various parameters such as partial pressure, total pressure, and temperature are manipulated to reduce punch-through defects, while still maintaining an acceptable etch rate. Some embodiments of the present invention also comprise the use of precursors, such as germane, to achieve faster etch rates with lower etch temperatures.

Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.

Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate.

Abstract: The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate.

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Abstract: Provided is a method of manufacturing a substrate for liquid ejection head, including: forming a groove portion by etching on one surface side of a silicon substrate, the groove portion being formed so as to surround a portion at which a liquid supply port is to be formed on an inner side of the groove portion; forming a protective layer on the one surface side of the silicon substrate, the protective layer being formed inside the groove portion and on an outer side of the groove portion; and forming the liquid supply port by subjecting the silicon substrate to crystal anisotropic etching treatment with use of the protective layer as a mask.

Abstract: Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO2), diamond-like carbon, graphene, and silicon carbide (SiC) of a predetermined phase. In accordance with still another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a multi-layer film is disposed at the substrate surface and spans the isotropically defined cavity.

Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.

Abstract: Embodiments of MEMS devices comprise a conductive movable layer spaced apart from a conductive fixed layer by a gap, and supported by rigid support structures, or rivets, overlying depressions in the conductive movable layer, or by posts underlying depressions in the conductive movable layer. In certain embodiments, portions of the rivet structures extend through the movable layer and contact underlying layers. In other embodiments, the material used to form the rigid support structures may also be used to passivate otherwise exposed electrical leads in electrical connection with the MEMS devices, protecting the electrical leads from damage or other interference.

Abstract: A semiconductor process is disclosed. The semiconductor process includes the steps of: providing a substrate having a specific area defined thereon; and performing an etch process by using an etchant comprising H2O2 to etch the specific area for forming a recess.

Abstract: Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H2O2 and HNO3 to remove damaged chalcogenide from the sidewalls of the memory cell structures.

Abstract: The semiconductor device comprises a metal line configured to be buried in an interlayer insulation layer formed over a semiconductor substrate, a first insulating pattern configured to be formed over the interlayer insulating layer and the first metal line so that the first metal line is exposed, a second insulating pattern configured to be buried between the first insulating patterns so that the first metal line is exposed, and a third insulating pattern configured to be formed over the first insulating pattern and the second insulating pattern so that the first metal line is exposed, thereby reducing the resistance of a contact plug, such that it operates at high speed and requires low power consumption.

Abstract: At least one single crystal substrate, each having a backside surface and made of silicon carbide, and a supporting portion having a main surface and made of silicon carbide, are prepared. In this preparing step, at least one of the backside surface and main surface is formed by machining. By this forming step, a surface layer having distortion in the crystal structure is formed on at least one of the backside surface and main surface. The surface layer is removed at least partially. Following this removing step, the backside surface and main surface are connected to each other.

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A micro electro mechanical systems (MEMS) microphone, and a method of manufacturing the MEMS microphone having an interval between a membrane and a back plate, the interval being correctly adjusted by forming the membrane and the back plate after an air-gap forming portion on a silicon substrate. Since the membrane and/or the back plate are/is formed by electroless plating, a sacrificial layer is easily planarized, and a residual stress is easily removed or controlled. The MEMS microphone includes a silicon substrate in which a back chamber is formed and on which an air-gap forming portion is formed above the chamber by etching the silicon substrate to a predetermined depth above the chamber; a membrane formed on the air-gap forming portion of the silicon substrate or the silicon substrate; and a back plate that is formed on the air-gap forming portion or the silicon substrate so as to be spaced apart from the membrane, wherein an air gap is formed between the membrane and the back plate.

Abstract: Methods for creating a microelectromechanical systems (MEMS) device using a single double, silicon-on-insulator (SOI) wafer. The double SOI wafer includes at least a base layer of silicon, a first layer of silicon, and a second layer of silicon, the layers of silicon are separated by an oxide layer. A stationary electrode with rigid support beams is formed into the second layer of silicon. A proof mass and at least one spring are formed into the first layer of silicon. The proof mass is separated from the stationary electrode by a first gap and the proof mass is separated from the base silicon layer by a second gap.

Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer. The hole pattern formed thereby has a high precision, with a density thereof being double or triple that of a pattern formed by a lithography technique.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: First and second supported portions each made of silicon carbide and a supporting portion made of silicon carbide are arranged such that the first and second supported portions and the supporting portion face each other and a gap is provided between the first and second supported portions. By sublimating and recrystallizing silicon carbide of the supporting portion, the supporting portion is connected to each of the first and second single-crystal substrates. On this occasion, a through hole is formed in the supporting portion so as to be connected to the gap. Accordingly, a path is formed which allows a fluid to pass through the gap and the through hole. By closing this path, the fluid can be prevented from being leaked through the silicon carbide substrate.

Abstract: A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

Abstract: Disclosed are a variety of porous and non-porous wire-like structures of microscopic and nanoscopic scale. For instance, disclosed are structures that comprise a porous object that comprises: (i) a first region; and (ii) a second region adjacent to the first region along an axis of the object, where the first region has at least one porous property different from that of the second region. Also disclosed are structures that include: (i) a high resistivity silicon; and (ii) a cross-section that is substantially perpendicular to an axis of the object. Also disclosed are methods of making and using such structures.

Abstract: Method for manufacturing a silicon wafer free of point defect agglomerates by processes including adding pure carbon to raw material of polycrystalline silicon, melting to become a molten silicon liquid, pulling a single silicon crystal ingot comprising a perfect domain [P] from the molten silicon liquid by controlling a ratio of V/G (mm2/minute ° C.), lapping a silicon wafer cut out from the ingot, beveling the silicon wafer, chemical etching the beveled wafer so as to be removed damages of a surface of the wafer, and mirror-polishing the etched wafer, and the pure carbon is added to the raw material of polycrystalline silicon so that a density of carbon in the ingot becomes 1×1015 to 5×1015 atoms/cm3.

Abstract: Methods of forming a roughened metal surface on a substrate are provided, along with structures comprising such roughened surfaces. In preferred embodiments roughened surfaces are formed by selectively depositing metal or metal oxide on a substrate surface to form discrete, three-dimensional islands. Selective deposition may be obtained, for example, by modifying process conditions to cause metal agglomeration or by treating the substrate surface to provide a limited number of discontinuous reactive sites. The roughened metal surface may be used, for example, in the manufacture of integrated circuits.

Abstract: Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

Abstract: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon layers at the same layer level, wherein the method includes the steps of: forming a photoresist film on the polysilicon layer; forming a photoresist pattern film having side surfaces with different inclination angles by patterning the photoresist film; forming the one or more polysilicon layers having side surfaces with different inclination angles by etching the polysilicon film using the photoresist pattern film.

Abstract: A method for providing a tuned repair for damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided. A precursor gas is provided, comprising a first repair agent represented as Si—(R)x(OR?)y, where y?1 and x+y=4, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group and a second repair agent represented as Si—(R)x(OR?)yR?, where y?1 and x+y=3, and wherein R is an alkyl or aryl group and R? is an alkyl or aryl group, and R? is of a group that reduces interfacial surface tension between a wet clean chemical and the low-k dielectric. Some of the first repair agent and second repair agent are bonded to the low-k dielectric to form a monolayer of the first repair agent and the second repair agent.

Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; an sealing substrate facing the substrate, an organic light emitting unit disposed between the substrate and the sealing substrate and having a plurality of organic light emitting devices emitting light, and a plurality of grooves formed in a light extracting surface of the organic light emitting display device through which the light is emitted to the outside. In one embodiment, the grooves are formed on the sealing substrate, and in another embodiment, the grooves are formed on the substrate.

Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.

Abstract: A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.

Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.

Abstract: A method of forming a nozzle plate of a fluid ejection device includes performing a first etch from a first side of a wafer to form a tapered region, forming an oxide layer in the tapered region such that a depth of the oxide layer on the tapered walls is greater than a depth of the oxide layer on the floor, performing a second etch from the first side to remove the oxide layer from the floor and a portion of the oxide layer from the tapered wall, and performing a third etch from the first side to form an outlet passage having a straight wall.

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Abstract: Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array.

Abstract: The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

Abstract: A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.

Abstract: A method for preparing a semiconductor structure for use in the manufacture of three dimensional transistors, the structure comprising a silicon substrate and an epitaxial layer, the epitaxial layer comprising an endpoint detection epitaxial region comprising an endpoint detection impurity selected from the group consisting of carbon, germanium, or a combination.

Abstract: A semiconductor device with first and second groups of transistors, the second group transistors each having a lower operating voltage than that of each of said transistors in said first group, the first group transistors have first gate electrodes formed from a silicon based material layer on a semiconductor substrate through a first gate insulating film, the second group transistors have second gate electrodes formed such that metal based gate materials are respectively filled in gate formation trenches formed in an interlayer insulating film on the semiconductor substrate through a second gate insulating film, and a resistor on the substrate has a resistor main body utilizing the silicon based material layer and is formed on the substrate through an insulating film.

Abstract: In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit which holds a semiconductor substrate with a surface having a convex pattern formed thereon and rotates the semiconductor substrate, a first supply unit which supplies a chemical and/or pure water to the surface of the semiconductor substrate, and a second supply unit which supplies a diluted water repellent to the surface of the semiconductor substrate to form a water-repellent protective film on the surface of the convex pattern. The second supply unit comprises a buffer tank which stores the water repellent, a first supply line which supplies a purge gas to the buffer tank, a second supply line which supplies a diluent, a pump which sends off the water repellent within the buffer tank, a third supply line which supplies the water repellent sent off from the pump, and a mixing valve which mixes the diluent and the water repellent to produce the diluted water repellent.

Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.

Abstract: A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

Abstract: A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension.

Abstract: The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate.

Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.