Abstract: [Subject] To provide a pressure sensor capable of implementing cost reduction and miniaturization. [Solving Means] A pressure sensor 1 includes a silicon substrate 2 provided therein with a reference pressure chamber 8, a diaphragm 10, consisting of part of the silicon substrate 2, formed on a surface layer portion of the silicon substrate 2 to partition a reference pressure chamber 8, and an etching stop layer 9 formed on a lower surface of the diaphragm 10 facing the reference pressure chamber 8. A through-hole 11 communicating with the reference pressure chamber 8 is formed on the diaphragm 10, and a filler 13 is arranged in the through-hole 11.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of Si-containing material and/or Ge-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.

Abstract: An embodiment is a method for bonding. The method comprises bonding a handle substrate to a capping substrate; thinning the capping substrate; etching the capping substrate; and after the thinning and the etching the capping substrate, bonding the capping substrate to an active substrate. The handle substrate has an opening therethrough. The method also comprises removing the handle substrate from the capping substrate. The removing comprises providing an etchant through the opening to separate the handle substrate from the capping substrate. Other embodiments further include forming a bonding material on a surface of at least one of the handle substrate and the capping substrate such that the capping substrate is bonded to the handle substrate by the bonding material. The bonding material may be removed by using a dry etching to remove the handle substrate from the capping substrate.

Abstract: The invention relates to a method of eliminating fragments of material present on the exposed surface of a first wafer bonded to a second wafer, the method including a step consisting of placing the first wafer in a liquid solution and propagating ultrasonic waves in the solution. The invention also relates to a process for manufacturing a multilayer structure comprising the following successive steps: bonding of a first wafer to a second wafer so as to form a multilayer structure; annealing of the structure; and thinning of the first wafer, including at least one step of chemically etching the first wafer. The process further includes, after the chemical etching step, the elimination of fragments of material present on the exposed surface of the thinned first wafer.

Abstract: A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first and a silicon nitride layers, the second silicon nitride layer is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.

Abstract: In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches.

Abstract: A novel and effective structure of a stackable element (A1,A2) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A1, A2) of alternated layers of a first dielectric material (2), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material (3) of low heat conductivity that is not etched by the solution.

Abstract: Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.

Abstract: Methods of forming semiconductor devices having customized contacts are provided including providing a first insulator layer and patterning the first insulator layer such that the first insulator layer defines at least one contact window. A second insulator layer is provided on the first insulator layer and in the at least one contact window such that the second insulator layer at least partially fills the at least one contact window. A first portion of the second insulator layer is etched such that a second portion of the second insulator layer remains in the at least one contact window to provide at least one modified contact window having dimensions that are different than dimensions of the at least one contact window. Related methods and devices are also provided.

Abstract: A photonic crystal surface emitting laser, having an n-type cladding layer formed on a substrate; an active layer formed on the n-type cladding layer; an electron blocking layer formed on the active layer and made of a second p-type semiconductor; and a two-dimensional photonic crystal layer that is formed on the electron blocking layer, includes a plurality of layers that are made of a first p-type semiconductor and have different band gaps, and has a high and a low refractive index portion in an in-plane direction. The band gaps of the plurality of layers are smaller than a band gap of the second p-type semiconductor and decrease stepwise or continuously in a lamination direction of the plurality of layers. A third p-type semiconductor having an acceptor doping concentration smaller than that of the second p-type semiconductor is disposed so as to cover a surface of the electron blocking layer.

Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

Abstract: A manufacturing method for a dual damascene structure includes providing a substrate having a dielectric layer, a first hard mask layer and a second hard mask layer sequentially formed thereon, performing a first double patterning process to sequentially form a plurality of first trench openings and a plurality of second trench openings in the second hard mask layer, performing a second double patterning process to sequentially form a plurality of first via openings and a plurality of second via openings in the fist hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.

Abstract: A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: Recess markers are implanted in a material during deposition and used during etching of the material for in-situ removal rate and removal homogeneity-over-radius definitions. An embodiment includes depositing a material on a substrate, implanting two dopants at two predetermined times, respectively, during deposition of the material, etching the material, detecting depths of the two dopants during etching, calculating the removal rate of the material in situ from the depths of the two dopants, and determining from the removal rate an etching stop position. Embodiments further include laterally implanting two dopants in a material at a predetermined depth during deposition, etching the material, detecting the positions and intensities of the two dopants during etching, and calculating lateral homogeneity of the material in situ from intensities of the dopants. Embodiments further include in situ corrective action for the removal process based on the determined removal rate and lateral homogeneity.

Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

Abstract: A wafer processing method which includes a protective member attaching step of attaching a protective member to the front side of the wafer, a back grinding step of grinding the back side of the silicon (Si) substrate of the wafer so as not to expose electrodes to the back side of the silicon (Si) substrate, and an etching step of etching the back side of the silicon (Si) substrate by using an etching liquid to thereby expose the electrodes to the back side of the silicon (Si) substrate. The etching liquid includes a first etching liquid having a high etching rate to silicon (Si) and a second etching liquid capable of etching silicon (Si) and having a low etching rate to silicon dioxide (SiO2).

Abstract: Quantitative understanding of neural and biological activity at a sub-millimeter scale requires an integrated probe platform that combines biomarker sensors together with electrical stimulus/recording sites. Optically addressed biomarker sensors within such an integrated probe platform allows remote interrogation from the activity being measured. Monolithic or hybrid integrated silicon probe platforms would beneficially allow for accurate control of neural prosthetics, brain machine interfaces, etc as well as helping with complex brain diseases and disorders. According to the invention a silicon probe platform is provided employing ultra-thin silicon in conjunction with optical waveguides, optoelectronic interfaces, porous filter elements, and integrated CMOS circuitry. Such probes allowing simultaneously analysis of both neural electrical activities along with chemical activity derived from multiple biomolecular sensors with porous membrane filters.

Abstract: A method of disposing alignment keys may include preparing a substrate including a shot group which includes a plurality of chip regions, and each of chip regions includes a key region. The method further includes forming at least one alignment key in each of the key regions of the substrate. Each of the alignment keys may be adapted to be used for at least one of a plurality of exposure processes which may be different from each other, and center points of the key regions may be located at points shifted from center points of the chip regions by the same distance along the same direction.

Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: A micro-electromechanical system (MEMS) device includes a substrate, a first beam, a second beam, and a third beam. The first beam includes first and second portions separated by an isolation joint. The first and second portions each comprise a semiconductor and a first dielectric layer. An electrically conductive trace is mechanically coupled to the first beam and electrically coupled to the second portion's semiconductor but not the first portion's semiconductor. The second beam includes a second dielectric layer. The profile of each of the first, second, and third beams has been formed by a dry etch. A cavity separates a surface of the substrate from the first, second, and third beams. The cavity has been formed by a dry etch. A side wall of each of the first, second, and third beams has substantially no dielectric layer disposed thereon, and the dielectric layer has been removed by a vapor-phase etch.

Abstract: A light emitting diode chip includes a device for protection against overvoltages, e.g., an ESD protection device. The ESD protection device is integrated into a carrier, on which the semiconductor layer sequence of the light emitting diode chip is situated, and is based on a specific doping of specific regions of said carrier. By way of example, the ESD protection device is embodied as a Zener diode that is connected to the semiconductor layer sequence by means of an electrical conductor structure.

Abstract: Methods of texturing and manufacturing a solar cell are provided. The method of texturing the solar includes texturing a surface of a substrate of the solar cell using a wet etchant, and the wet etchant includes a surfactant.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: The present invention refers to a method for contactless deposition of new etching compositions onto surfaces of semiconductor devices as well as to the subsequent etching of functional layers being located on top of these semiconductor devices. Said functional layers may serve as surface passivation layers and/or anti-reflective coatings (ARCs).

Abstract: A manufacturing method of a light-emitting diode, includes the steps of: successively growing a first clad layer, an active layer and a second clad layer on a substrate; and patterning the first clad layer, the active layer and the second clad layer into a specified plane shape, and causing at least a part of an outer peripheral part of the active layer to protrude to an outside from at least one of the first clad layer and the second clad layer.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes mask layer on a processing target, pressing a template having a pattern having closed loop structure against the mask layer via an imprint material to solidify the imprint material, etching the mask layer by using the imprint material to form a mask, removing a part of the pattern having the closed loop of the mask, and etching the processing target by the mask including the pattern, the part of which is removed.

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract: Apparatus for treating wafers using a wafer carrier rotated about an axis is provided with a ring which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.

Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate, forming first spacers on sidewalls of the first trench, forming a second trench by etching the substrate under the first trench, forming second spacers on sidewalls of the second trench, forming a third trench, which has a wider width than a width between the second spacers, by etching the substrate under the second trench, forming a liner layer on the surface of the third trench, and exposing one of the sidewalls of the second trench by selectively removing the second spacers.

Abstract: A vacuum processing apparatus, comprising: a processing chamber 3 in which an object to be processed is placed and a predetermined vacuum state is formed; a first processing gas introducing means 12 for converting a first processing gas into a radical state and introducing the resulting first processing gas in the radical state into the processing chamber through first processing gas introducing ports which open to the interior of the processing chamber; a second processing gas introducing means 15 for introducing a second processing gas, which is reactive with the first processing gas in the radical state, into the processing chamber through second processing gas introducing ports which open to the interior of the processing chamber; a temperature controlling means for controlling the temperature within the processing chamber 3 to a first temperature-controlled state, in which the first processing gas in the radical state and the second processing gas process the surface of the object to be processed, thereb

Abstract: A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Abstract: There are provided a processing liquid that is capable of suppressing pattern collapse of a fine metal structure, such as a semiconductor device and a micromachine, and a method for producing a fine metal structure using the same. The processing liquid for suppressing pattern collapse of a fine metal structure, contains a phosphate ester and/or a polyoxyalkylene ether phosphate ester, and the method for producing a fine metal structure, uses the same.

Abstract: A process for removing contaminating metals from a substrate to improve electrical performance is provided. Polycationic metals are known to be particularly detrimental to the electrical properties of an insulator or semiconductor substrate. The process includes the exposure of the substrate to an aqueous solution of at least one compound of the formula: (I) where n in each occurrence is independently an integer value between 0 and 6, and X is independently in each occurrence H, NR4, Li, Na or K and at least one of X is NR4; where R in each occurrence is independently H or C1-C6 alkyl, to improve electrical performance of the substrate. A kit for preparing such a solution includes a 1-20 total weight percent aqueous concentrate of at least one compound of formula (I). The kit also provides instructions for the dilution of the concentrate to form the solution.

Abstract: Methods of forming semiconductor devices having customized contacts are provided including providing a first insulator layer and patterning the first insulator layer such that the first insulator layer defines at least one contact window. A second insulator layer is provided on the first insulator layer and in the at least one contact window such that the second insulator layer at least partially fills the at least one contact window. A first portion of the second insulator layer is etched such that a second portion of the second insulator layer remains in the at least one contact window to provide at least one modified contact window having dimensions that are different than dimensions of the at least one contact window. Related methods and devices are also provided.

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV.

Abstract: A semiconductor device is formed by implanting recess markers in a material during deposition and using the recess markers during etching of the material for precise in-situ removal rate definition and removal homogeneity-over-radius definition. An embodiment includes depositing a layer of material on a substrate, implanting first and second dopants in the material at first and second predetermined times during deposition of the material, etching the material, detecting the depths of the first and second dopants during etching, calculating the removal rate of the material in situ from the depths of the first and second dopants, and determining from the removal rate a stop position for etching.

Abstract: A beam dose computing method includes dividing a surface area of a target object into include first, second and third regions of different sizes, the third regions being less in size than the first and second regions, determining first corrected doses of a charged particle beam for correcting fogging effects in the first regions, determining corrected size values for correcting pattern line width deviations occurring due to loading effects in the second regions to create a map of base doses of the beam in respective of said second regions and to prepare a map of proximity effect correction coefficients in respective of said second regions, using the maps to determine second corrected doses of the beam for proximity effect correction in the third regions, and using the first and second corrected doses to determine an actual beam dose at each position on the surface of said object.

Abstract: A method of forming a MEMS device includes forming a sacrificial layer over a substrate. The method further includes forming a metal layer over the sacrificial layer and forming a protection layer overlying the metal layer. The method further includes etching the protection layer and the metal layer to form a structure having a remaining portion of the protection layer formed over a remaining portion of the metal layer. The method further includes etching the sacrificial layer to form a movable portion of the MEMS device, wherein the remaining portion of the protection layer protects the remaining portion of the metal layer during the etching of the sacrificial layer to form the movable portion of the MEMS device.

Abstract: The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.

Abstract: A method for treating semiconductor wafer includes: providing a stack including a high-k layer including a first oxide material, wherein the first oxide material contains hafnium and/or zirconium, and a cap-layer including a second oxide material, wherein the cap-layer has been deposited on top of the high-k layer, wherein the second oxide material contains lanthanum, a lanthanide and/or aluminium; supplying liquid A to the surface of the semiconductor wafer, liquid A being an aqueous solution containing an oxidizing agent; supplying liquid B to the surface of the semiconductor wafer, liquid B being a liquid with a pH-value lower than 6; and conducting a step SC wherein a liquid C is supplied to the surface of the semiconductor wafer, wherein step SC is carried out after step SB, wherein liquid C is an aqueous acidic solution with a fluorine concentration of at least 10 ppm.