Abstract: In the case of performing at least two plasma processing steps in a common plasma reaction chamber, a CW AC power or a pulse-modulated AC power is appropriately selected as a power for plasma processing in each step. Thereby, even in a step where plasma processing conditions are limited due to apparatus configurations, the plasma processing can be performed in more various manners. Further, uniform plasma can be generated between electrodes and a quantity of a power to be supplied between the electrodes can be reduced, by using the pulse-modulated AC power. Thereby, a plasma processing speed can be reduced so that throughput control is facilitated.

Abstract: A solar cell, a method of manufacturing the solar cell, and a method of texturing the solar cell are provided. The method of texturing the solar cell includes depositing metal particles on a solar cell substrate, and etching the solar cell substrate and forming a plurality of hemisphere-shaped grooves on the solar cell substrate to texture a surface of the solar cell substrate.

Abstract: A separated MEMS thermal actuator is disclosed which is largely insensitive to creep in the cantilevered beams of the thermal actuator. In the separated MEMS thermal actuator, a inlaid cantilevered drive beam formed in the same plane, but separated from a passive beam by a small gap. Because the inlaid cantilevered drive beam and the passive beam are not directly coupled, any changes in the quiescent position of the inlaid cantilevered drive beam may not be transmitted to the passive beam, if the magnitude of the changes are less than the size of the gap.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a method may include forming a semiconductor substrate including a pixel part and a peripheral part, forming an interlayer dielectric film including a metal wire on and/or over the semiconductor substrate, forming photo diode patterns on and/or over the interlayer dielectric film and connected to the metal wire in the pixel part, forming a device isolation dielectric layer on and/or over the interlayer dielectric film including the photo diode patterns, forming a first via hole on and/or over the device isolation dielectric layer to partially expose the photo diode patterns, and forming a second via hole on and/or over the device isolation dielectric layer to expose the metal wire in the peripheral part. According to embodiments, vertical integration of transistor circuitry and a photo diode may be achieved.

Abstract: A gas supplying system includes a processing gas supply pipe for supplying a processing gas from a gas cylinder 210 into a processing apparatus and a nonreactive gas supply source 230 for supplying a nonreactive gas into the gas supply pipe. While the system is in operation, the gas supply pipe is charged with the nonreactive gas and a control unit is in a standby state. If a processing gas use start signal is received from the processing apparatus, the system exhausts the nonreactive gas from the gas supply pipe to create a vacuum therein; charges the gas supply pipe with the processing gas; and starts a supply of the processing gas from the processing gas supply source. If a processing gas use finish signal is received from the processing apparatus, the system stops the supply of the processing gas from the processing gas supply source; exhausts the processing gas from the gas supply pipe to create a vacuum therein; and charges the gas supply pipe with the nonreactive gas.

Abstract: A photo mask comprises a H-type light-shield pattern. In an exposure process, a photo mask is used to form a STAR (Step Asymmetry Recess) gate region, thereby stably securing a storage node contact region and improving a refresh characteristic of a semiconductor device.

Abstract: A method for manufacturing a semiconductor device comprises: forming a first photoresist pattern in a double patterning technology (DPT) for overcoming a resolution limit of an exposer; and forming a second photoresist pattern. The method further comprises forming a hard mask film and an anti-reflective film to prevent an intermixing phenomenon generated when the second photoresist pattern is formed. As a result, yield and reliability of the process can be improved.

Abstract: A semiconductor substrate includes a semiconductor base substrate that has an oxide film selectively formed on a part thereof, the oxide film having a non-uniform thickness; and a semiconductor layer that is formed on the oxide film by epitaxial growth so as to have a non-uniform thickness.

Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Abstract: An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching.

Abstract: A method for locally controlling an electrical potential of a semiconductor structure or device, and hence locally controlling lateral and/or vertical photoelectrochemical (PEC) etch rates, by appropriate placement of electrically resistive layers or layers that impede electron flow within the semiconductor structure, and/or by positioning a cathode in contact with specific layers of the semiconductor structure during PEC etching.

Abstract: It is disclosed a cleaning liquid used in a process for forming a dual damascene structure comprising steps of etching a low dielectric layer (low-k layer) accumulated on a substrate having thereon a metallic layer to form a first etched-space; charging a sacrifice layer in the first etched-space; partially etching the low dielectric layer and the sacrifice layer to form a second etched-space connected to the first etched-space; and removing the sacrifice layer remaining in the first etched-space with the cleaning liquid, wherein the cleaning liquid comprises (a) 1-25 mass % of a quaternary ammonium hydroxide, such as TMAH and choline, (b) 30-70 mass % of a water soluble organic solvent, and (c) 20-60 mass % of water.

Abstract: A chip for a cell electrophysiological sensor has a substrate. The substrate has a through-hole formed from the upside to the downside, and the opening of the through-hole is formed in a curved surface curved from the upside and downside of the substrate toward the inner side of the through-hole. In this configuration, the electrolyte solution (first electrolyte solution and second electrolyte solution) flows more smoothly, and the sample cell can be sucked accurately, and the trapping rate of the sample cells is improved.

Abstract: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.

Abstract: A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from 60 to 99.75% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13; and a remover composition containing an organic amine (A), an organic phosphonic acid (B), a linear sugar alcohol (C) and water, wherein the remover composition contains the component (A) in an amount of from 0.2 to 30% by weight, the component (B) in an amount of from 0.05 to 10% by weight, the component (C) in an amount of from 0.1 to 10% by weight, and the water in an amount of from 50 to 99.65% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13.

Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and formin

Abstract: Disclosed is a substrate processing apparatus including: a reaction tube to accommodate at least one substrate; at least a pair of electrodes disposed outside the reaction tube; and a dielectric member, wherein a plasma generation region is formed at least in a space between an inner wall of the reaction tube and an outer circumferential edge of the substrate, the member includes a main face extending in a radial direction of the substrate and in a substantially entire circumferential direction of the substrate in a horizontal plane parallel to a main face of the substrate, and is disposed in an outer circumferential region of the substrate, and gas activated in the plasma generation region is supplied through a surface region of the main face of the member to the substrate.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa.

Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant.

Abstract: An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements.

Abstract: A CMP polishing liquid being capable of using in a chemical mechanical polishing comprising of: a first chemical mechanical polishing step of polishing a conductive substance layer of a substrate having an interlayer insulation film containing convex and concave regions on a surface thereof, a barrier layer coating along the surface of the interlayer insulation film, and the conductive substance layer coating the barrier layer while filling the concave regions, and thus exposing the barrier layer in the convex regions; and a second chemical mechanical polishing step of exposing the interlayer insulation film in the convex regions by polishing the barrier layer exposed in the first chemical mechanical polishing step; characterized in that a difference (B)?(A) is 650 {acute over (?)} or less, wherein the (A) is a polishing amount of the interlayer insulation film in a field area when the interlayer insulation film in the field area having a width of 1,000 ?m or more of the interlayer insulation film region f

Abstract: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle.

Abstract: A substrate supporting apparatus includes a substrate supporting portion having a substrate supporting surface facing a rear surface of a substrate; plural protruding portions provided on the substrate supporting surface, for preventing the substrate from being slid on the substrate supporting surface by friction force generated in relation with the substrate; a gas discharge opening provided in the substrate supporting surface, for discharging gas toward the rear surface of the substrate; a gas flow path whose one end is connected to the gas discharge opening; and a temperature control unit for controlling temperature of the gas flowing through the gas flow path, wherein the gas discharged to the rear surface of the substrate flows in a gap between the substrate supporting surface and the substrate, and by Bernoulli effect causing reduction of pressure of the gap, the substrate is attracted to the substrate supporting portion, thereby supporting the substrate.

Abstract: A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method including the steps of forming an SiO2 film on a first pattern of the photoresist, etching the SiO2 film so that the SiO2 may remain only in a side wall section of a first pattern of the photoresist, removing a first pattern of the photoresist, and forming a second pattern of the SiO2 film.

Abstract: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table 103 disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing gas includes at least one of organic acid ammonium salt, organic acid amine salt, organic acid amide and organic acid hydrazide.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: A method for forming micropatterns in a semiconductor device includes forming a first etch stop layer over a etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, etching portions of the first sacrificial layer and second etch stop layer to form first sacrificial patterns, forming an insulation layer along an upper surface of the first etch stop layer, forming a second sacrificial layer over the insulation layer to cover the insulation layer, planarizing the second sacrificial layer and the insulation layer to expose the first sacrificial patterns, removing the first sacrificial patterns and the second sacrificial layer, etching the second etch stop layer and insulation layer to thereby form second sacrificial patterns, etching the first etch stop layer, and etching the etch target layer.

Abstract: Mixtures of fluorine and inert gases like nitrogen and/or argon can be used for etching of semiconductors, solar panels and flat panels (TFTs and LCDs), and for cleaning of semiconductor surfaces and plasma chambers. Preferably, fluorine is comprised in an amount of 15 to 25 vol.-% in binary mixtures. The gas mixtures can be used as substitute or drop-in for respective mixtures comprising NF3 and permit a very flexible operation of plasma apparatus. For example, apparatus tuned for NF3/Ar mixtures can be operated without further tuning using fluorine and argon, optionally together with nitrogen. The fluorine content is preferably in the range of 1 to 5 vol.-%, if ternary mixtures of fluorine, nitrogen and argon are used.

Abstract: The present invention provides a plasma process detecting sensor. In the plasma process detecting sensor, a hole diameter of an insulating film is spread with almost no spread of a hole diameter of an upper electrode. Therefore, when the plasma process detecting sensor is exposed to a plasma, positive ions incident onto the bottom of a contact hole are hard to collide with an inner wall surface of a hole main body of the insulating film. As a result, the inner wall surface of the hole main body of the insulating film is hard to undergo damage, and the generation of a defect level that assists electric conduction can be suppressed. It is thus possible to suppress age deterioration of a sensor function during the measurement of a charge-up under an environment of a plasma etching condition.

Abstract: In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing regions is placed thereby exposing the insulating film from etching bottom portions by removing portions that correspond to the dividing regions and subsequently continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma thereby removing corner portions put in contact with the insulating film in the device-formation-regions, isotropic etching is performed on the semiconductor wafer at any timing.

Abstract: A semiconductor substrate includes: a first semiconductor layer; an oxide layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the oxide layer; a first recess that is formed in the second semiconductor layer with extending from an upper face of the second semiconductor layer toward the first semiconductor layer, the first recess being formed at a position where an alignment mark for determining a forming position of an element which is to be built in the semiconductor substrate is to be formed; and an etching prevention layer that is inwardly formed from a position of an upper face of the first semiconductor layer, the position corresponding to the recess, the layer comprising a material that is prevented from being etched during etching of the first semiconductor layer.

Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

Abstract: A long channel semiconductor device and a manufacturing method thereof are provided. The method for forming a long channel semiconductor device includes: providing a substrate; forming a trench in the substrate with a trench bottom defining a first channel length; forming a spacer on a sidewall of the trench; recessing the trench bottom to form a recessed bottom defining a second channel length longer than the first channel length; forming a gate dielectric layer on the recessed bottom; forming a gate conductor on the gate dielectric layer; and forming source/drain regions in the substrate adjacent to the spacer.

Abstract: A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device.

Abstract: A method for aligning a probe relative to a Supporting substrate defining a first planar surface, an edge, and a first crystal plane includes the steps of masking the surface of the substrate to define an exposed area on the first surface at the edge; and etching, using an etch reagent, a recess in the exposed area, the recess defining first and second opposed sidewalls, an end wall remote from the edge, and a bottom wall. The method further includes the step of providing a probe substrate defining a second planar surface and a second crystal plane identical to the first crystal plane, and positioning the probe substrate so that the first and the second crystal planes are positioned identically when forming a probe from the probe substrate using the etch reagent, wherein the probe defines congruent surfaces to the first and second sidewalls.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: There is provided a method of forming a semiconductor device. According to the method, a gate pattern having a capping insulating layer is formed on a substrate, a first etch stop layer is conformably formed. A first interlayer insulating layer having a planarized upper surface, a second etch stop layer and a second interlayer insulating layer are sequentially formed on the first etch stop layer. A first opening and a second opening are formed. The first opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer, the first etch stop layer and the capping insulating pattern to expose the gate electrode, and the second opening penetrates the second interlayer insulating layer, the second etch stop layer, the first interlayer insulating layer and the first etch stop layer to expose the substrate. The forming the first and second openings includes at least one selective etching process and a nonselective etching process.

Abstract: In a manufacturing method of a semiconductor device, a trench is formed in a semiconductor substrate by an anisotropic dry etching so as to have an aspect ratio greater than or equal to 10, and a damaged layer that is generated in a wall and a bottom of the trench due to the anisotropic dry etching is removed by an isotropic dry etching. The isotropic dry etching is performed with a first gas including carbon and fluorine and a second gas including oxygen. A temperature of the semiconductor substrate is controlled so that the damaged layer is removed from a whole surface of the wall and the bottom in the isotropic dry etching.

Abstract: A method of fabricating a thick gallium nitride (GaN) layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCI and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of forming the porous GaN layer and the thick GaN layer in-situ proceeds in a single chamber. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN etching and growth are performed using an HVPE process gas such that costs are greatly reduced.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: A device fabricated using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until a relatively late fabrication stage. As a result, flatness of the (poly)silicon layer is preserved for the deposition of any necessary over-layers, which substantially obviates the need for filling the voids created by the structure formation with silicon oxide.

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

Abstract: The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern.

Abstract: A dry etching gas comprising a C4-6 fluorine compound which has an ether bond or carbonyl group and one or more fluorine atoms in the molecule and is constituted only of carbon, fluorine, and oxygen atoms and in which the ratio of the number of fluorine atoms to the number of carbon atoms (F/C) is 1.9 or lower (provided that the compound is neither a fluorine compound having one cyclic ether bond and one carbon-carbon double bond nor a saturated fluorine compound having one carbonyl group); a mixed dry etching gas comprising the dry etching gas and at least one gas selected from the group consisting of rare gases, O2, O3, CO, CO2, CHF3, CH2F2, CF4, C2F6, and C3F8; and a method of dry etching which comprises converting either of these dry etching gases into a plasma and processing a semiconductor material with the plasma.

Abstract: A method of dividing a wafer whose strength is reduced along a plurality of dividing lines formed in a lattice pattern on the front surface, along the dividing lines, comprising the steps of: a tape affixing step for affixing a protective tape to one side of the wafer; a wafer holding step for holding the wafer affixed to the protective tape on both sides of each dividing line through the protective tape; and a breaking step for dividing the wafer along each dividing line by sucking, along each dividing line, the wafer held through the protective tape.

Abstract: A method of forming a micro pattern in a semiconductor device includes forming an etching object layer and a hard mask layer on a semiconductor substrate. Cross-shaped first auxiliary patterns are formed on the hard mask layer. An insulating layer is formed on the hard mask layer including the first auxiliary pattern. A second auxiliary pattern is formed on the insulating layer between the first auxiliary patterns. An etching process is performed such that the insulating layer remains only on a lower portion of the second auxiliary pattern. The hard mask is etched through an etching process using the first and second auxiliary patterns as an etching mask to form a hard mask pattern. The etching object layer is etched using the hard mask pattern as an etching mask.