Abstract: A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.

Abstract: A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom

Abstract: A multiple-substrate processing apparatus includes: a reaction chamber comprised of two discrete reaction stations aligned one behind the other for simultaneously processing two substrates; a transfer chamber disposed underneath the reaction chamber, for loading and unloading substrates to and from the reaction stations simultaneously; and a load lock chamber disposed next to the transfer chamber. The transfer arm includes one or more end-effectors for simultaneously supporting two substrates one behind the other as viewed in the substrate-loading/unloading direction.

Abstract: The surface of a material is textured and by exposing the surface to pulses from an ultrafast laser. The laser treatment causes pillars to form on the treated surface. These pillars provide for greater light absorption. Texturing and crystallization can be carried out as a single step process. The crystallization of the material provides for higher electric conductivity and changes in optical and electronic properties of the material. The method may be performed in vacuum or a gaseous environment. The gaseous environment may aid in texturing and/or modifying physical and chemical properties of the surfaces. This method may be used on various material surfaces, such as semiconductors, metals and their alloys, ceramics, polymers, glasses, composites, as well as crystalline, nanocrystalline, polycrystalline, microcrystalline, and amorphous phases.

Abstract: A method to integrate a micro electro mechanical system and a CMOS image sensor is disclosed. First a substrate is provided. The substrate includes a micro electro mechanical system (MEMS) region and a CMOS image sensor (CIS) region. The micro electro mechanical system region includes a micro electro mechanical system component and the CMOS image sensor region includes a CMOS image sensor element. Second, an etching procedure is performed on the substrate to form a micro electro mechanical system trench and a CMOS image sensor trench. The etching procedure includes at least a dry etching and at least a wet etching.

Abstract: In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.

Abstract: A method of surface treatment for silicon material. The method includes providing a first silicon material having a surface region. The first silicon material has a first purity characteristics and a first surface roughness characteristics. A chemical polishing process is perform to the surface region to cause the surface region to have a second roughness characteristics. Thereafter, a chemical leaching process is performed to the surface region to cause the first silicon material in a depth within a vicinity of the surface region to have a second purity characteristics. A polysilicon material characterized by a grain size greater than about 0.1 mm is formed using a deposition process overlying the surface region.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.

Abstract: A method for removing a damaged low dielectric constant material following an etch process, an ashing process, or a wet cleaning process is described. A dry, non-plasma removal process is implemented to remove a thin layer of damaged material on a feature following formation of the feature. The dry, non-plasma removal process comprises a chemical treatment of the damaged material, followed by a thermal treatment of the chemically treated surface layer. The two steps, chemical and thermal treatment, can be repeated.

Abstract: It is an object of one embodiment of the preset invention to conduct separation without damaging a semiconductor element when the semiconductor element is made flexible. Further, it is another object of one embodiment of the preset invention to provide a technique for weakening adhesion between a separation layer and a buffer layer. Furthermore, it is another object of one embodiment of the preset invention to provide a technique for preventing generation of the bending stress on a semiconductor element due to separation. A semiconductor element formed over a separation layer with a buffer layer interposed therebetween is separated by dissolving the separation layer by using an etchant. Alternatively, separation is conducted by inserting a film into a region where a separation layer is dissolved by being in contact with an etchant and moving the film in a direction toward a region where the separation layer is not dissolved.

Abstract: A method of making a memory cell or magnetic element by double patterning. The method includes providing a starting stack having a first area, masking a portion of the first area of the starting stack resulting in a first masked portion and a first unmasked portion. Then, removing the first unmasked portion of the starting stack to provide a second area. A portion of this second area is masked, resulting in a second masked portion and a second unmasked portion. The method also includes removing the second unmasked portion to provide a third area, with the finished cell or element being the third area.

Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.

Abstract: A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped.

Abstract: A method of manufacturing an MEMS sensor according to the present invention includes the steps of: forming a first sacrificial layer on one surface of a substrate; forming a lower electrode on the first sacrificial layer; forming a second sacrificial layer made of a metallic material on the first sacrificial layer to cover the lower electrode; forming an upper electrode made of a metallic material on the second sacrificial layer; forming a protective film made of a nonmetallic material on the substrate to collectively cover the first sacrificial layer, the second sacrificial layer and the upper electrode; and removing at least the second sacrificial layer by forming a through-hole in the protective film and supplying an etchant to the inner side of the protective film through the through-hole.

Abstract: A method for forming a pattern of a semiconductor device comprises: forming a stacked film including an underlying layer, an antireflection film and a photoresist film over a semiconductor substrate; coating an over-coating composition over the photoresist film to form an over-coating film; performing an exposing and developing process with a cell mask on the photoresist film where the over-coating film is formed to form a photoresist pattern; forming a silicon-containing-RELACS layer over the antireflection film including the photoresist pattern where the over-coating film is formed; removing the over-coating film and the silicon containing RELACS layer on the photoresist pattern to form a spacer of the silicon containing RELACS layer at sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the antireflection film and the underlying layer with the spacer of the silicon containing RELACS layer as a mask to form an antireflection pattern and an underlying pattern.

Abstract: A semiconductor device cleaning method includes etching one of a semiconductor substrate for forming a contact hole in the semiconductor substrate and the bottom of the contact hole on a semiconductor substrate, and cleaning the semiconductor substrate with a cleaning solution, wherein the cleaning solution includes a mixture of sulfuric acid (H2SO4), hydrogen peroxide (H2O2) and hydrogen fluoride (HF). Cleaning the semiconductor substrate may include clamping the semiconductor substrate on a spin chuck, cleaning the semiconductor substrate by spraying the semiconductor substrate with the cleaning solution while spinning the semiconductor substrate using the spin chuck, spraying and rinsing the semiconductor substrate with deionized water while spinning the semiconductor substrate, and drying the semiconductor substrate by continuing to spin the semiconductor substrate.

Abstract: Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process on the substrate using the mask layer as a mask, and removing the self-assembly material layer. Accordingly, it is possible to fabricate nano-devices through a nano-scale substrate patterning process, ion implantation process and etching process, without using a light source.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a first opening pattern and a second opening pattern larger in size than the first opening pattern in a first film formed above a semiconductor substrate and in a second film on the first film, the second film comprising a material different from the first film; forming a blocking film on the second film, the blocking film substantially blocking only the first opening pattern between the first and second opening patterns of the second film; and selectively applying isotropic etching to an inner side face of the second opening pattern of the first film after forming the blocking film, thereby enlarging only the size of the second opening pattern between the size of the first opening pattern and the size of the second opening pattern of the first film.

Abstract: A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

Abstract: A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns.

Abstract: In a first aspect, a first method of forming an epitaxial film on a substrate is provided. The first method includes (a) providing a substrate; (b) exposing the substrate to at least a silicon source so as to form an epitaxial film on at least a portion of the substrate; and (c) exposing the substrate to HCl and Cl2 so as to etch the epitaxial film and any other films formed during step (b). Numerous other aspects are provided.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming an etching layer (17) formed of silicon on a semiconductor substrate (10); forming a mask layer (20) with a pattern on the etching layer (17), which includes an intermediate layer (22) as a silicon oxide film and a top layer (24) as a polysilicon; and etching the etching layer (17) using the mask layer (20) as a mask, and eliminating the top layer (24).

Abstract: The method of etching a sacrificial layer according to the present invention includes the steps of forming a sacrificial layer having a protrusive shape on a base layer, forming a covering film covering the sacrificial layer, forming a protective film made of a material whose etching selection ratio to the sacrificial layer is greater than the etching selection ratio of the covering film to the sacrificial layer on a portion of the covering film opposed to the side surface of the sacrificial layer, and etching the sacrificial layer after the formation of the protective film.

Abstract: A method of forming a MEMS structure over active circuitry in a semiconductor body includes forming active circuitry in a semiconductor body, and forming the MEMS structure over the active circuitry, wherein at least a portion of the MEMS structure spatially overlaps the active circuitry.

Abstract: To provide an etching method employing a novel CVD system and an etching apparatus applicable to the method. In the etching method, performed are an adsorption step of employing halogen radicals generated from a halogen through formation of a plasma thereof, and a precursor 24 formed from the halogen and a noble metal component generated through etching of a noble metal member 11 by the halogen radicals, wherein crystal nuclei of the precursor 24 are caused to be adsorbed on a substrate 3; and an etching step of anisotropically etching, in a thickness direction by the halogen radicals, a portion of the substrate 3 on which the crystal nuclei have been adsorbed.

Abstract: Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable of being chemically bonded to the reaction pattern. A coating layer is then formed on substantially all of the structure that includes the self-assembled monolayer. Afterwards, the contact holes are formed on the semiconductor substrate by performing an etching process.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: A light absorbent for forming an organic anti-reflective layer, represented by the following formula 1 or formula 2, is provided: wherein A represents a substituted or unsubstituted, linear or branched, saturated tetravalent hydrocarbon group, a substituted or unsubstituted, linear or branched, saturated hydrocarbon group and containing one or more heteroatoms, a substituted or unsubstituted aromatic group, a substituted or unsubstituted heteroaromatic group, a substituted or unsubstituted alicyclic group, a substituted or unsubstituted heteroalicyclic group, a substituted or unsubstituted diaryl ether, a substituted or unsubstituted diaryl sulfide, a substituted or unsubstituted diaryl sulfoxide, a substituted or unsubstituted diaryl ketone, or a substituted or unsubstituted diaryl bisphenol A; R1, R2, and R3 each independently represent a hydrogen atom, a halogen atom, a substituted or unsubstituted alkyl group a substituted or unsubstituted aryl group, a substituted or unsubstituted acetal group, o

Abstract: A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips.

Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.

Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).

Abstract: Methods of forming aluminum oxide layers on substrates are disclosed. In some embodiments, the method includes depositing an aluminum oxide seed layer on the substrate using a first process having a first deposition rate. The method further includes depositing a bulk aluminum oxide layer atop the seed layer using a metalorganic chemical vapor deposition (MOCVD) process having a second deposition rate greater than the first deposition rate.

Abstract: A method of fabricating a thickness of silicon material includes providing a silicon ingot material having a surface region and introducing a plurality of particles having an energy of about 1-5 MeV through the surface region to a depth to define a cleave region and a thickness of detachable material between the cleave region and the surface region. Additionally, the method includes processing the silicon ingot material to free the thickness of detachable material at a vicinity of the cleave region and causing formation of a free-standing thickness of material characterized by a carrier lifetime about 10 microseconds and a thickness ranging from about 20 microns to about 150 microns with a thickness variation of less than about five percent. Furthermore, the method includes treating the free-standing thickness of material using a thermal treatment process to recover the carrier lifetime to about 200 microseconds and greater.

Abstract: A biosensor chip (100) for detecting biological particles, the biosensor chip (100) comprising a sensor active region (101) being sensitive for the biological particles and being arranged in a Back End of the Line portion (102) of the biosensor chip (100).

Abstract: A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.

Abstract: A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue.

Abstract: Disclosed is a light emitting device. The light emitting device comprises a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, the second conductive semiconductor layer comprising a first area and a second area, a third conductive semiconductor layer on the second area of the second conductive semiconductor layer, a first electrode layer electrically connecting the first conductive semiconductor layer with the second conductive semiconductor layer of the second area, and a second electrode layer electrically connecting the second conductive semiconductor layer with the third conductive semiconductor layer.

Abstract: A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer.

Abstract: A cleaning composition of a semiconductor device for laminating an organosiloxane-based thin film and a photoresist layer in this order on a substrate having a low dielectric interlayer insulation film and a copper wiring or a copper alloy wiring, then applying selective exposure and development treatments to the subject photoresist layer to form a photoresist pattern, subsequently applying a dry etching treatment to the organosiloxane-based thin film and the low dielectric interlayer insulation film while using this resist pattern as a mask and then removing the organosiloxane-based thin film, a residue generated by the dry etching treatment, a modified photoresist having been modified by the dry etching treatment and an unmodified photoresist layer located in a lower layer than the modified photoresist, the cleaning composition containing from 15 to 20% by mass of hydrogen peroxide, from 0.0001 to 0.003% by mass of an amino polymethylene phosphonic acid, from 0.02 to 0.

Abstract: A method for producing a device includes embedding trenches with an epitaxial layer having high crystallinity while a mask oxide film remains unremoved. An n-type semiconductor is formed on the surface of a silicon substrate, and a mask oxide film and a mask nitride film are formed on the surface of the n-type semiconductor. The mask laminated film is opened by photolithography and etching, and trenches are formed in the silicon substrate. The width of the remaining mask laminated film is narrowed, whereby portions of the n-type semiconductor close to the opening ends of the trenches are exposed. The trenches are embedded with a p-type semiconductor, whereby the surface of the mask laminated film is prevented from being covered with the p-type semiconductor. The p-type semiconductor is grown from the second exposed portions of the n-type semiconductor. V-shaped grooves are prevented from forming on the surface of the p-type semiconductor.

Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.

Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.

Abstract: A method of forming a contact hole in an insulating film coating amorphous Si having an irregular surface formed on an insulating substrate, for connecting the amorphous Si to a conductor film formed on the insulating film includes etching the insulating film using reactive ion etching to a depth whereat the irregularity does not disappear, and sputter-etching by physically colliding Ar radicals produced by Ar gas plasma discharge onto the surface of the amorphous Si.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and a carbon dioxide (CO2) gas to form vias. The fluorocarbon gas may be C4F6 gas. A ratio of a flow rate of the C4F6 gas to a flow rate of the CO2 gas can vary from approximately 1:2 to 1:10. In another embodiment, the porous low-k dielectric layer is etched with a process gas mixture that includes a fluorocarbon gas and an argon gas with no CHF3 gas to form trenches aligned with the vias in an integrated dual-damascene structure. The fluorocarbon gas may be CF4 gas.

Abstract: Embodiments of MEMS devices comprise a conductive movable layer spaced apart from a conductive fixed layer by a gap, and supported by rigid support structures, or rivets, overlying depressions in the conductive movable layer, or by posts underlying depressions in the conductive movable layer. In certain embodiments, portions of the rivet structures extend through the movable layer and contact underlying layers. In other embodiments, the material used to form the rigid support structures may also be used to passivate otherwise exposed electrical leads in electrical connection with the MEMS devices, protecting the electrical leads from damage or other interference.

Abstract: In the present invention, an npn junction is formed by circularly forming a p? type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated.

Abstract: A method of manufacturing a cantilever-based micro-electromechanical device comprising the steps of providing a first conductive material layer on a substrate to from a plurality of electrodes. Then, depositing a sacrificial material layer on the electrodes and substrate, thereby defining a non-exposed surface and an exposed surface of the sacrificial material. The method comprises the steps of patterning and etching the sacrificial material layer such that at least a portion of at least one electrode is exposed and spuner etching the sacrificial material layer such that the exposed surface of the sacrificial material layer comprises edges which are incongruous with the edges of the non-exposed surface. The method then involves forming a cantilever structure. Finally, the method comprises the step of removing at least a portion of the sacrificial material layer such that at least a portion of the cantilever structure is suspended.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact layer over the third subcell having a fifth band gap greater than at least the magnitude of the second band gap.