Abstract: A solar cell with high photon utilization includes a substrate, a transparent conductive oxide layer, an anti-reflection coating (ARC) layer and at least one main charge collecting line. The substrate has a front side and a back side. The substrate has a first-type semiconductor layer close to the back side and a second-type semiconductor layer close to the front side. The transparent conductive oxide layer is formed on the front side. The ARC layer is formed on the transparent conductive oxide layer. The main charge collecting line penetrates through the ARC layer and projects from the ARC layer, and the main charge collecting line is electrically connected to the transparent conductive oxide layer. A method of manufacturing the solar cell is also disclosed.

Abstract: A processing object 2 is sucked and fixed by a sucker 11 and rotated by a rotator 12. In that state, a processing liquid supplied from a processing liquid supply 22 is applied through a processing liquid application tube 21 onto a surface of the processing object 2. Thermal electrons emitted from a thermionic source 33 are accelerated by an acceleration electrode 34 and pass through a Be film 32 to impinge upon the processing liquid on the surface of the processing object 2. When the processing liquid on the surface of the processing object is irradiated with the electron beam, the processing liquid is ionized or radicalized to become active, thereby effectively processing the surface of the processing object 2.

Abstract: The present invention provides microelectrode array stabilizing devices and associated methods. A microelectrode array stabilizing device includes a first microelectrode array substrate having a plurality of first microelectrodes configured to penetrate tissue. A plurality of first interlocking structures are coupled to the first microelectrode array substrate, with each of the plurality of first interlocking structures including a first interlocking mechanism at a distal end. The device may further include a second microelectrode array substrate which optionally has a plurality of second microelectrodes configured to penetrate tissue. A plurality of second interlocking structures are coupled to the second microelectrode array substrate, each of the plurality of second interlocking structures including a second interlocking mechanism at a distal end. The second interlocking mechanism is complimentary to the first interlocking mechanism.

Abstract: A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

Abstract: A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film, removing the second mask in a wiring trench forming region including the via hole, and etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region. Removing the first mask in the wiring trench forming region includes etching the first mask and etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole.

Abstract: A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region.

Abstract: A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin.

Abstract: A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip.

Abstract: In a semiconductor device manufacturing method according to this invention, an SiO2 film used as a mask at the time of trench formation is removed by a wet process after hydrophilic treatment is performed on the interior of a hydrophobic trench.

Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).

Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.

Abstract: A fluid mixing apparatus is constituted by a plurality of flow passageways for conveying fluids, respectively, and jet outlets, corresponding to and communicating with the flow passageways, respectively, for jetting the fluids therefrom so that movement directions of the fluids intersect each other to mix the fluids. The jet outlets are provided at a surface of a substrate in which the flow passageways are provided. At least one of the flow passageways communicating with at least one of the jet outlets has a center axis partially shifted from a center axis of at least one of the jet outlets so as to incline a movement direction of a fluid jetted from at least one of the jet outlets with respect to the surface of the substrate.

Abstract: A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.

Abstract: A method for manufacturing a capped sensor element by providing a substrate with a sensor structure, the sensor structure being produced in the substrate using a sacrificial material, applying a cap made of zeolite to the sensor structure and the sacrificial material, and removing the sacrificial material, the sacrificial material being removed through the cap made of zeolite. A sensor element having capping is also provided.

Abstract: A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

Abstract: In accordance with an embodiment of the invention, there is provided an electrostatic chuck comprising an electrode, and a surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck. The surface layer includes a plurality of protrusions extending to a height above portions of the surface layer surrounding the protrusions to support the substrate upon the protrusions during electrostatic clamping of the substrate. The protrusions are substantially equally spaced across the surface layer as measured by a center to center distance between pairs of neighboring protrusions.

Abstract: Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a masking layer, patterning the masking layer, and etching the CNT film through the patterned masking layer using a non-oxygen based chemistry. Other aspects are also described.

Abstract: An integrated device including a sensor and the like formed on a ?-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a ?-alumina film epitaxially grown on a portion of the silicon substrate; a second function area formed on an area of the silicon substrate other than an area where the ?-alumina film is grown; and wiring means for connecting the first function area with the second function area.

Abstract: A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern.

Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Abstract: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.

Abstract: The present invention relates to methods for producing anode materials for use in nonaqueous electrolyte secondary batteries. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a solution containing metals ions and a dissolution component. When the anode material is contacted with the solution, the dissolution component dissolves a part of the semiconductor material in the anode material and deposit the metal on the anode material. After deposition, the anode material and metal are annealed to form a uniform metal-semiconductor alloy layer. The anode material of the present invention can be in a monolithic form or a particle form. When the anode material is in a particle form, the particulate anode material can be further shaped and sintered to agglomerate the particulate anode material.

Abstract: A method for forming very small isolated dots of a target material, e.g., a ferromagnetic material or phase change material, on a substrate includes providing a substrate having a layer of the target material disposed on a surface thereof, etching the layer of target material so as to form a plurality of lines of the material on the surface of the substrate, and etching the lines of the target material so as to form a rectangular matrix of substantially similar, very small isolated dots of the target material on the substrate. By the successive formation of orthogonally intersecting linear patterns on the substrate, including the formation and use of “hard” etch masks, spacer approach and selective etching techniques, the method enables very small (<65 nm) isolated dots of the target material to be formed on the substrate reliably and with the use of conventional 193 nm wavelength photolithographic methods and apparatus.

Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.

Abstract: A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

Abstract: The present invention provides a circuit board which can improve characteristics of a circuit element, an electronic device, and a method for producing a circuit board. The method for producing a circuit board of the present invention is a method for producing a circuit board including one or more polysilicon layers at the same layer level, wherein the method includes the steps of: forming a photoresist film on the polysilicon layer; forming a photoresist pattern film having side surfaces with different inclination angles by patterning the photoresist film; forming the one or more polysilicon layers having side surfaces with different inclination angles by etching the polysilicon film using the photoresist pattern film.

Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).

Abstract: The embodiments of the present invention are directed to the formation of multi-layer three-dimensional structures by forming and attaching a plurality of individual layers where each of the layers comprises one or more materials forming a desired pattern. In one embodiment, a multi-layer three-dimensional structure is formed by forming a plurality of individual layers and attaching at least them together. In another embodiment, a multi-layer three-dimensional structure is formed by 1) forming one or more individual layers, 2) attaching the one or more formed layers onto a substrate, 3) if desired, forming new structures on the attached one or more layers.

Abstract: A solid-state image pickup device which includes a substrate carrying a plurality of photoelectric conversion elements which are two-dimensionally arranged therein the substrate having a plurality of rectangular light-receiving faces each corresponding to the photoelectric conversion element, a flattening layer having a plurality of approximately rectangular concave faces each located to correspond to the light-receiving faces, and a color filter having color layers of plural kinds of colors and buried in the concave faces of the flattening layer, the color filter exhibiting a larger refractive index than that of the flattening layer, wherein the color layers are respectively enabled to function as a convex lens.

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract: With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a single-sided etching or an asymmetric etching thereon. The present invention provides a method of etching a wafer comprising: performing a single-sided etching or an asymmetric etching on the wafer, wherein the performing the single-sided etching or the asymmetric etching comprises: overlapping two wafers whose one sides face each other; and etching the overlapped two wafers, and a solar cell including the etched wafers.

Abstract: A resist film made of a chemically amplified resist is formed on a substrate. Subsequently, a barrier film for preventing a component of the resist film from eluting into an immersion liquid or preventing the immersion liquid from permeating into the resist film is formed on the resist film. Thereafter, with an immersion liquid provided on the barrier film, pattern exposure is carried out by selectively irradiating the resist film with exposing light through the barrier film. Then, after removing the barrier film, the resist film having been subjected to the pattern exposure is developed, so as to form a resist pattern made of the resist film.

Abstract: An electronic component or display device of the present invention can be provided by using a following pattern formation method. On a substrate treated with a first etching with a first resist pattern as a first mask, a second resist pattern is transfer-printed on the first resist patterns so as to partially overlap with the first resist pattern and partially extended from the first resist pattern. And then a second etching is performed by using the first resist pattern and the second resist pattern as a second mask. The first resist pattern and the second resist pattern are used for forming wirings and/or terminals, and the extended portion of the second resist pattern is used to make the wirings to have a cross section of a stair-like edge shape.

Abstract: A process for etching the surfaces of semiconductor substrates utilizes a texturing tank which introduces a process fluid through a circulating system. The process fluid is heated to a desired temperature and maintained at a desired concentration prior to entering a processing area where laminar flow is produced to more quickly and uniformly roughen the surface of semiconductor substrates. The texturing tank permits removal of bubbles and eliminates temperature stratification in the processing area.

Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.

Abstract: An apparatus having a multiple gas injection port system for providing a high uniform etching rate across the substrate is provided. In one embodiment, the apparatus includes a nozzle in the semiconductor processing apparatus having a hollow cylindrical body having a first outer diameter defining a hollow cylindrical sleeve and a second outer diameter defining a tip, a longitudinal passage formed longitudinally through the body of the hollow cylindrical sleeve and at least partially extending to the tip, and a lateral passage formed in the tip coupled to the longitudinal passage, the lateral passage extending outward from the longitudinal passage having an opening formed on an outer surface of the tip.

Abstract: The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.

Abstract: An object of the present invention is to provide a gallium nitride-based compound semiconductor light emitting device having excellent light extraction efficiency and a high emission output in which a planar shape is a rectangular shape with vertical and longitudinal sides each having a different length. The present light emitting device comprises a substrate and a gallium nitride-based compound semiconductor layer formed on the substrate, wherein a planar shape is a rectangular shape with vertical and longitudinal sides each having a different length, and a side surface of the gallium nitride-based compound semiconductor layer is not vertical to a principal surface of the substrate.

Abstract: Embodiments of the present invention provide apparatus and method for front side protection while processing side and backside of a substrate. One embodiment of the present invention provides a showerhead configured to provide a purge gas to a front side of a substrate during a backside etch processing. The showerhead comprises a body configured to be disposed over the front side of the substrate. The body has a process surface configured to face the front side of the substrate. The process surface has an outer circular region, a central region, a middle region between the outer central region and the central region. The first plurality of holes are distributed in the outer circular region and configured to direct the purge gas towards an edge area of the front side of the substrate. No gas delivery hole is distributed within a substantial portion of the middle region.

Abstract: A substrate processing method that can prevent a decrease in the yield of semiconductor devices manufactured from substrates. A gas containing fluorine atoms is supplied into a chamber, and then chlorine gas is supplied into the chamber. Further, a gas containing nitrogen atoms is supplied into the chamber.

Abstract: An etching process includes forming a metal-fluoride layer at least as a part of an etching mask formed over a semiconductor layer at a temperature of 150° C. or higher; patterning the metal-fluoride layer; and etching the semiconductor layer using the patterned metal-fluoride layer as a mask. Using this etching method, even an etching-resistant semiconductor layer such as a Group III-V nitride semiconductor can be easily etched by a relatively simpler process.

Abstract: A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5, and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path.

Abstract: Silicon nano wires having silicon nitride shells and a method of manufacturing the same are provided. Each silicon nano wire has a core portion formed of silicon, and a shell portion formed of silicon nitride surrounding the core portion. The method includes removing silicon oxide formed on the shell of the silicon nano wire and forming a silicon nitride shell.

Abstract: Provided may be a treatment method to remove defects created on the surface of a substrate, a method of fabricating an image sensor by using the treatment method, and an image sensor fabricated by the same. The treatment method may include providing a semiconductor substrate including a surface defect, providing a chemical solution to a surface of the semiconductor substrate, and removing the surface defect by consuming the surface of the semiconductor substrate and forming a chemical oxide layer on the semiconductor substrate.

Abstract: A method for producing a micromechanical diaphragm sensor includes providing a semiconductor substrate having a first region, a diaphragm, and a cavity that is located at least partially below the diaphragm. Above at least one part of the first region, a second region is generated in or on the surface of the semiconductor substrate, with at least one part of the second region being provided as crosspieces. The diaphragm is formed by a deposited sealing layer, and includes at least a part of the crosspieces.

Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.