Abstract: Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of the present invention provides a hoop assembly for using a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein, and three or more lifting fingers attached to the hoop. The three or more lifting fingers are configured to support a substrate outside the inner volume of the confinement ring.

Abstract: A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H2). The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: (A) solid polymer particles being finely dispersed in the aqueous phase and containing pendant functional groups (a1) capable of strongly interacting and forming strong complexes with the metal of the surfaces to be polished, and pendant functional groups (a2) capable of interacting less strongly with the metal of the surfaces to be polished than the functional groups (a1); and (B) an organic non-polymeric compound dissolved in the aqueous phase and capable of interacting and forming strong, water-soluble complexes with the metal of the surfaces to be polished and causing an increase of the material removal rate MRR and the static etch rate SER of the metal surfaces to be polished with increasing concentration of the compound (B); a CMP process comprising selecting (A) and (B) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

Abstract: The present invention provides an organic light-emitting diode package structure including a first substrate, a second substrate, at least an organic light-emitting diode device and a dam. The first substrate and a surface of the second substrate are disposed opposite to each other, wherein the surface of the second substrate includes a plurality of concavities, each of the concavities has an opening area, and a ratio of a sum of the opening areas of the concavities to an area of the first surface of the second substrate is substantially between 0 and 1. The organic light-emitting diode device is disposed on the first substrate, and a light emitting surface of the organic light-emitting diode device faces the second substrate. The dam is disposed between the first substrate and the second substrate to combine the first substrate and the second substrate, and the dam surrounds the organic light-emitting diode device.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.

Abstract: Provided is a method of producing a liquid ejection head substrate, the method including, in sequence; grinding a second surface of a silicon substrate, which is an opposite surface of a first surface on which a function element is formed, polishing the ground second surface, etching the polished second surface by reactive ion etching using ion incident energy, forming an etching mask on the second surface after the reactive ion etching, and forming a liquid supply port by subjecting the silicon substrate to wet etching using the etching mask.

Abstract: Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: In a method for manufacturing a semiconductor device, a process of providing a semiconductor wafer having a wiring layer having conductive patterns and a plurality of insulation films containing a first insulation film surrounding side surfaces of the conductive patterns are provided. After the process of providing the semiconductor wafer, a process of removing some regions of the plurality of insulation films to form openings is provided. Herein, the first insulation film is disposed to a position closer to the circumference of the semiconductor wafer than a position closest to the outermost circumference of the wafer among the arrangement positions of the conductive patterns.

Abstract: Methods and apparatus for isotropically etching a metal from a work piece, while recovering and reconstituting the chemical etchant are described. Various embodiments include apparatus and methods for etching where the recovered and reconstituted etchant is reused in a continuous loop recirculation scheme. Steady state conditions can be achieved where these processes are repeated over and over with occasional bleed and feed to replenish reagents and/or adjust parameters such as pH, ionic strength, salinity and the like.

Abstract: [Technical Problem] A sapphire substrate and a method for manufacturing the same are provided, which enables growth of a nitride semiconductor having excellent crystallinity and can achieve a nitride semiconductor light emitting element having excellent light extraction efficiency. [Solution to Problem] A sapphire substrate provided with a plurality of projections on a principal surface on which a nitride semiconductor is grown to form a nitride semiconductor light emitting element, wherein the projection is substantially pyramidal-shaped having a pointed top and constituted by a plurality of side surfaces, wherein the side surface has an inclined angle of between 53° and 59° from a bottom surface of the projection, and wherein the side surface is crystal-growth-suppressed surface on which growth of nitride semiconductor is suppressed relative to the substrate surface located between the adjacent projections.

Abstract: A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Abstract: A method of processing a substrate through the use of an apparatus, including a substrate carrier for carrying a substrate; a liquid-applying unit for applying chemical to said substrate; and a gas-applying unit for applying gas atmosphere generated by vaporizing the liquid to said substrate. And the apparatus includes a plurality of process units, and the same process is applied to the substrate in each said process units.

Abstract: To provide a rinsing agent for lithography, which contains C6-C8 straight-chain alkanediol, and water.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Abstract: The methods involve selectively depositing a resist containing a solid hydrogenated rosin resin and a liquid hydrogenated rosin resin ester as a mixture on a semiconductor followed by etching uncoated portions of the semiconductor and simultaneously inhibiting undercutting of the resist. The etched portions may then be metallized to form current tracks.

Abstract: A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed. The adjuvant comprising a mixture of a linear polyelectrolyte with a graft type polyelectrolyte makes it possible to increase polishing selectivity as compared to CMP slurry using the linear polyelectrolyte alone, and to obtain a desired range of polishing selectivity by controlling the ratio of the linear polyelectrolyte to the graft type polyelectrolyte.

Abstract: This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(?3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract: The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column direction over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. An etch mask film is formed over the semiconductor substrate including the auxiliary film. An etch process is performed in order to form second etch mask patterns having the second pitch in such a manner that the etch mask film, the auxiliary film, and the first etch mask patterns are isolated from one another in a row direction and the etch mask film remains between the first etch mask patterns. The auxiliary film between the first and second etch mask patterns is removed.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.

Abstract: The present disclosure provides devices, systems and methods for sequencing nucleic acid molecules. Nucleic acid molecules can be sequenced with a high accuracy (e.g., greater than 97% in a single pass) using a chip comprising an array of independently addressable nanopore sensors at a density of at least about 500 sites per 1 mm2. An individual nanopore sensor can include a nanopore in a membrane that is adjacent or in proximity to a sensing electrode.

Abstract: A plasma etching method for forming a hole in an etching target film by a plasma processing apparatus is provided. The apparatus includes an RF power supply for applying RF power for plasma generation to at least one of upper and lower electrodes, and a DC power supply for applying minus DC voltage to the upper electrode. A first condition that plasma is generated by turning on the RF power supply and minus DC voltage is applied to the upper electrode and a second condition that the plasma is extinguished by turning off the RF power supply and minus DC voltage is applied to the upper electrode are alternately repeated. Etching is performed by positive ions in the plasma under the first condition and negative ions are supplied into the hole by the DC voltage to neutralize positive ions in the hole under the second condition.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: The present invention provides a semiconductor device manufacturing method. This method comprises: etching a first dielectric layer to form a recess; depositing a second dielectric layer over said first dielectric layer and said recess, such that said recess is enclosed by said first dielectric layer and said second dielectric layer to form an air gap; and performing etching, such that a first trench is formed in said first dielectric layer and said second dielectric layer, adjacent to said air gap. The first trench can be filled with a conductive material to form wiring.

Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: In a manufacturing method of a semiconductor device, a first insulating film covering a ferroelectric capacitor is formed, and a first opening that has a relatively large diameter and reaches an electrode of the ferroelectric capacitor is formed in the first insulating film, and then recovery annealing of the ferroelectric capacitor is performed, and thereby, a path for oxygen can be secured in performing the recovery annealing, and the sufficient recovery annealing can be performed without causing problems during a manufacturing process.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A method of making a thermally-assisted recording (TAR) disk includes etching an initial layer of generally spherically shaped FePt grains encapsulated by shells of graphitic carbon layers. The etching partially or completely removes the carbon layers on the tops of the shells, exposing the FePt grains while leaving carbon segregant material between the FePt grains. Additional Fe, Pt and C are then simultaneously deposited. The additional Fe and Pt grow on the exposed FePt grains and increase the vertical height of the grains, resulting in growth of columnar FePt grains. The additional C forms on top of the grains that together with the intergranular carbon form larger carbon shells. The resulting FePt grains thus have a generally columnar shape with perpendicular magnetic anisotropy, rather than a generally spherical shape. Lateral grain isolation is maintained by the carbon segregant remaining between the grains.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

Abstract: A processed object processing apparatus which enables a plurality of processes to be carried out efficiently. A plurality of treatment systems are communicably connected together in a line and in which the objects to be processed are processed. A load lock system is communicably connected to the treatment systems and has a transfer mechanism that transfers the objects to be processed into and out of each of the treatment systems. At least one of the treatment systems is a vacuum treatment system, and the load lock system is disposed in a position such as to form a line with the treatment systems.

Abstract: A method for fabricating a micropattern of a semiconductor device is provided. The method includes forming a first hard mask over an etch target layer, forming a first sacrificial layer over the first hard mask, etching the first sacrificial layer to form a sacrificial pattern and forming spacers on both sidewalls of the sacrificial pattern, A second sacrificial layer is formed over the spacers and the first hard mask. A dummy mask is formed in a bent portion of the second sacrificial layer between the adjacent spacers. The sacrificial pattern and the second sacrificial layer are etched using the dummy mask and the spacers as an etch barrier layer to form a dummy pattern between the adjacent spacers. The first hard mask is etched using the spacers and the dummy pattern as an etch barrier layer to form a first hard mask pattern.

Abstract: A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater element made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic having planar heater zones, power supply lines, power return lines and vias.

Abstract: Monocrystalline semiconductor substrates are textured with alkaline solutions to form pyramid structures on their surfaces to reduce incident light reflectance and improve light absorption of the wafers. The alkaline baths include compounds which inhibit the formation of flat areas between pyramid structures to improve the light adsorption.

Abstract: The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.

Abstract: A protective chuck is magnetically levitated on a substrate with a gas layer between the bottom surface of the protective chuck and the substrate surface. The gas layer protects a surface region of the substrate against a fluid layer covering the remaining of the substrate surface without contacting the substrate, reducing or eliminating potential damage to the substrate surface. The magnetically levitated protective chuck can enable combinatorial processing of a substrate, providing multiple isolated processing regions on a single substrate with different material and processing conditions.

Abstract: A method is provided for treating the surface of high aspect ratio nanostructures to help protect the delicate nanostructures during some of the rigorous processing involved in fabrication of semiconductor devices. A wafer containing high aspect ratio nanostructures is treated to make the surfaces of the nanostructures more hydrophobic. The treatment may include the application of a primer that chemically alters the surfaces of the nanostructures preventing them from getting damaged during subsequent wet clean processes. The wafer may then be further processed, for example a wet cleaning process followed by a drying process. The increased hydrophobicity of the nanostructures helps to reduce or prevent collapse of the nanostructures.

Abstract: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.

Abstract: There is provided a semiconductor device manufacturing apparatus capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing apparatus includes: an etching processing mechanism for performing an etching process that etches a low dielectric insulating film formed on a substrate; a CO2 plasma processing mechanism for performing a CO2 plasma process that exposes the substrate to CO2 plasma after the etching process; a polarization reducing mechanism for performing a polarization reducing process that reduces polarization in the low dielectric insulating film after the CO2 plasma process; and a transfer mechanism for transferring the substrate.

Abstract: An apparatus for preventing stiction of a three-dimensional MEMS (microelectromechanical system) microstructure, the apparatus including: a substrate; and a plurality of micro projections formed on a top surface of the substrate with a predetermined height in such a way that a cleaning solution flowing out from the microstructure disposed thereabove is discharged.

Abstract: In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach.

Abstract: A substrate comprises a first mark and a second mark. The first mark comprises a first pattern with at least one mark feature formed by a first material and at least one region formed by a second material. The first and second materials have different material characteristics with respect to a substrate treatment process such that a step height in a direction substantially perpendicular to the surface of the substrate may be created by applying the substrate treatment process. The second mark can be provided with a second step height by applying the substrate treatment process. The second step height is substantially different from the first step height.

Abstract: A method of removing an alumina layer around a main pole layer during perpendicular magnetic recording head fabrication is disclosed. The alumina etch sequence includes immersing a substrate in a series of aqueous solutions purged with an inert gas to remove oxygen thereby avoiding corrosion of the main pole. Initially, the substrate is soaked and heated in deionized (DI) water. Once heated, the substrate is immersed in an etching bath at about 80° C. and pH 10.5. Bath chemistry is preferably based on Na2CO3 and NaHCO3, and N2 purging improves etch uniformity and reduces residue. Thereafter, the substrate is rinsed in a second DI water bath between room temperature and 80° C., and finally subjected to a quick dump rinse before drying. Inert gas, preferably N2, may be introduced into the aqueous solutions through a purge board having a plurality of openings and positioned proximate to the bottom of a bath container.