Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.

Abstract: A monolithic fabrication method of parallel-plate electrowetting-on-dielectric (EWOD) chips for digital microfluidics of picoliter droplets is disclosed. Instead of assembling a second substrate to form a top plate, the top plate is generated in situ as a thin-film membrane that forms a monolithic cavity having a gap height on the order of micrometers with excellent accuracy and uniformity. The membrane is embedded with EWOD driving electrodes and confines droplets against the device substrate to perform digital microfluidic operations. Two main attributes of the monolithic architecture that distinguish it from tradition methods are: (i) it enables excellent control of droplet dimensions down to the micrometer scale, and (ii) it does not require the typical alignment and assembly steps of the two plates.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: A method of printing comprises the steps of: providing a solid state material having an exposed surface; applying an auxiliary layer to the exposed surface to form a composite structure, the auxiliary layer having a stress pattern; subjecting the composite structure to conditions facilitating fracture of the solid state material along a plane at a depth therein; and removing the auxiliary layer and, therewith, a layer of the solid state material terminating at the fracture depth, wherein an exposed surface of the removed layer of solid state material has a surface topology corresponding to the stress pattern.

Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.

Abstract: Fabricating of one or more semiconductor devices with critical gate dimension control is facilitated by: providing a multilayer stack structure over a substrate; etching through the multilayer stack structure, with critical gate dimension control, to define multiple gate lines; providing a protective layer over the multiple gate lines; and patterning and cutting one or more gate lines of the multiple gate lines to facilitate defining multiple gate structures of the one or more semiconductor devices. Etching through the multilayer stack structure is facilitated by lithographically patterning the multilayer stack structure, and critical dimension feedback control is provided to at least one of the lithographically patterning or the etching through the multilayer stack structure.

Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Abstract: A method for fabricating a structure in magnetic recording head is described. First and second hard mask layers are provided on the layer(s) for the structure. A BARC layer and photoresist mask having a pattern are provided on the second hard mask layer. The pattern includes a line corresponding to the structure. The pattern is transferred to the BARC layer and the second hard mask layer in a single etch using an etch chemistry. At least the second hard mask layer is trimmed using substantially the same first etch chemistry. A mask including a hard mask line corresponding to the line and less than thirty nanometers wide is thus formed. The pattern of the second hard mask is transferred to the first hard mask layer. The pattern of the first hard mask layer is transferred to the layer(s) such that the structure has substantially the width.

Abstract: A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.

Abstract: Provided is a method of forming a pattern, including (a) forming a chemically amplified resist composition into a film, (b) exposing the film to light, (c) developing the exposed film with a developer containing an organic solvent, and (d) rinsing the developed film with a rinse liquid containing an organic solvent, which rinse liquid has a specific gravity larger than that of the developer.

Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.

Abstract: Post etch treatments (PETs) of low-k dielectric films are described. For example, a method of patterning a low-k dielectric film includes etching a low-k dielectric layer disposed above a substrate with a first plasma process. The etching involves forming a fluorocarbon polymer on the low-k dielectric layer. The low-k dielectric layer is surface-conditioned with a second plasma process. The surface-conditioning removes the fluorocarbon polymer and forms an Si—O-containing protecting layer on the low-k dielectric layer. The Si—O-containing protecting layer is removed with a third plasma process.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract: The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C, SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated.

Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.

Abstract: A manufacturing method of a magnetic recording medium includes steps of forming a magnetic recording layer, a first mask layer, a second mask layer containing silicon as primary component, a strip layer, a third mask layer, and a resist layer, a step of patterning the resist layer to provide a pattern, steps of transferring the pattern to the third mask layer, to the strip layer, and to the second mask layer, a step of removing the strip layer by wet etching and of stripping the third mask layer and the resist layer above the magnetic recording layer, steps of transferring the pattern to the first mask layer and to the magnetic recording layer, and a step of stripping the first mask layer remaining on the magnetic recording layer.

Abstract: Bare aluminum baffles are adapted for resist stripping chambers and include an outer aluminum oxide layer, which can be a native aluminum oxide layer or a layer formed by chemically treating a new or used bare aluminum baffle to form a thin outer aluminum oxide layer.

Abstract: A method for manufacturing a device comprising an elastic member on a substrate includes steps of: forming a sacrificial layer by forming a plurality of sacrificial sub-layers on the substrate; forming a plate member in or on the sacrificial layers connected to the substrate and substantially parallel to a top surface of the substrate; and removing the sacrificial sub-layers after forming the plate member by removing the sacrificial sub-layers in an order different from the reverse order of forming the sacrificial sub-layers.

Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

Abstract: A method for fabricating a 3D (three-dimensional) structure is disclosed to provide hydrophobicity to a surface of a 3D structure by using a dipping method in which a predetermined-shaped structure is immersed in a molten metal solution. The method includes: immersing a predetermined-shaped structure in a molten metal solution to coat a molten metal material on the surface of the predetermined-shaped structure; anodizing a metal base coated with the molten metal material; coating a polymer material on an outer surface of the metal-coated base to form a negative replica structure; covering an outer surface of the negative replica structure with an outer formation material; and removing the metal-coated base from the negative replica structure and the outer formation material.

Abstract: Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact.

Abstract: A wafer transfer assembly and method of using the assembly to transfer device wafers between processing tools in a manufacturing process are described herein. The assembly comprises a wafer transfer disk, an end effector configured to receive and support the wafer transfer disk, and an elongated handle extending from the end effector. The wafer transfer disk comprises a wafer-engaging surface configured to support a debonded device wafer placed on the wafer transfer assembly with the device surface adjacent the wafer-engaging surface. The wafer-engaging surface has non-stick properties, and yields a low bonding strength interface between the wafer-engaging surface and device surface. The resulting transfer stack can be transported to other processing tools for additional processing of the debonded device wafer, followed by separating the debonded device wafer and the wafer transfer disk without damaging the device wafer.

Abstract: A cleaning solution of the present invention contains a sodium ion, a potassium ion, an iron ion, an ammonium salt of a sulfuric ester represented by General Formula (1), and water, and each content of the sodium ion, the potassium ion, and the iron ion is 1 ppb to 500 ppb. ROSO3—(X)+ (1) where R is an alkyl group with a carbon number of 8-22 or an alkenyl group with a carbon number of 8-22, and (X)+ is an ammonium ion.

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.

Abstract: Afforded are a polishing agent, and a compound semiconductor manufacturing method and semiconductor device manufacturing method utilizing the agent, whereby the surface quality of compound semiconductor substrates can be favorably maintained, and high polishing rates can be sustained as well. The polishing agent is a polishing agent for Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductors, and includes an alkali metal carbonate, an alkali metal organic salt, a chlorine-based oxidizer, and an alkali metal phosphate, wherein the sum of the concentrations of the alkali metal carbonate and the alkali metal organic salt is between 0.01 mol/L and 0.02 mol/L, inclusive. The compound semiconductor manufacturing method comprises a step of preparing a Ga?In(1-?)As?P(1-?) (0???1; 0???1) compound semiconductor, and a step of polishing the face of the compound semiconductor utilizing an aforedescribed polishing agent.

Abstract: A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate.

Abstract: There is provided a nitride semiconductor light-emitting element including a transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the transparent conductor. There is also provided a nitride semiconductor light-emitting element including a first transparent conductor, a metal layer, a second transparent conductor, a first conductivity-type nitride semiconductor layer, a light-emitting layer, and a second conductivity-type nitride semiconductor layer, the metal layer, the second transparent conductor, the first conductivity-type nitride semiconductor layer, the light-emitting layer, and the second conductivity-type nitride semiconductor layer being successively stacked on the first transparent conductor.

Abstract: The present invention provides a laser irradiation apparatus which can accurately control positions of beam spots of laser beams emitted from laser oscillators and the distance between the adjacent beam spots. A laser irradiation apparatus of the present invention includes a first movable stage with an irradiation body provided, two or more laser oscillators emitting laser beams, a plurality of second movable stages with the laser oscillators and optical systems provided, and a means for detecting at least one alignment maker. The first stage and the second stages may move not only in one direction but also in a plurality of directions. Further, the optical systems are to shape the laser beams emitted from the laser oscillators into linear beams on the irradiation surface.

Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member using an electroless nickel deposition process; e) depositing a gold layer on the nickel coating using an electroless gold deposition process; and f) depositing palladium on the gold layer using an electroless palladium deposition process to improve wear resistance of the connector pads while preserving bondability of the contact pads.

Abstract: A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings.

Abstract: A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.

Abstract: A method for etching trenches in an etch layer disposed below a patterned organic mask is provided. The patterned organic mask is treated, comprising flowing a treatment gas comprising H2 and N2, forming a plasma from the treatment gas, making patterned organic mask more resistant to wiggling, and stopping the flow of the treatment gas. Trenches are etched in the etch layer through the patterned organic mask.

Abstract: The invention relates to a method for etching a structure (1) including at least one material (4) to be etched, said method consisting in: selecting at least one chemical species that can react with the material (4) to be etched; selecting at least one soluble compound that can release this chemical species; producing a solution (11) containing the compound and a powder of particles or solid grains (13) in suspension; placing the material to be etched in the presence of the solution; and producing high-frequency ultrasounds in the solution, at at least one frequency, capable of generating active cavitation bubbles such that the chemical species is generated and reacts with the material to be etched, thereby producing a soluble compound or a precipitate.

Abstract: A method for manufacturing a semiconductor device having a cooling mechanism comprises a modified region forming step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region within the object along a line to form a modified region, an etching step of anisotropically etching the object after the modified region forming step so as to advance the etching selectively along the first modified region and form a flow path for circulating a coolant as a cooling mechanism within the object, and a functional device forming step of forming a functional device on one main face side of the object.

Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.

Abstract: The present invention provides an etching solution less affected by trench structures and also provides an isolation structure-formation process employing the solution. The etching solution contains hydrofluoric acid and an organic solvent. The organic solvent has a ?H value defined by Hansen solubility parameters in the range of 4 to 12 inclusive and the saturation solubility thereof in water is 5 wt % or more at 20° C. This solution can be adopted instead of known etching solutions used in conventional production processes of semiconductor elements.

Abstract: Disclosed herein are methods for assembling nanostructures. The assembling methods include contacting the plurality of nanostructures to a substrate having one or more discontinuities. At least a portion of the plurality of nanostructures assemble adjacent to the discontinuity, the assembled nanostructures including at least one nanostructure having a bridging, molecule. Devices, such as field-effect transistors, are also disclosed.

Abstract: A method of forming memory device is provided. A substrate having at least two cell areas and at least one peripheral area between the cell areas is provided. A target layer, a sacrificed layer and a first mask layer having first mask patterns in the cell areas and second mask patterns in the peripheral area are sequentially formed on the substrate. Sacrificed layer is partially removed to form sacrificed patterns by using the first mask layer as a mask. Spacers are formed on sidewalls of the sacrificed patterns. The sacrificed patterns and at least the spacers in the peripheral area are removed. A second mask layer is formed in the cell areas. Target layer is partially removed, using the second mask layer and remaining spacers as a mask, to form word lines in the cell areas and select gates in a portion of cell areas adjacent to the peripheral area.

Abstract: The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity.

Abstract: A micromachined microphone or speaker embedded within, or positioned on top of, a substrate suitable for carrying microelectronic chips and components. The acoustic element converts sound energy into electrical energy which is then amplified by electronic components positioned on the surface of the substrate. Alternatively, the acoustic element may be driven by electronics to produce sound. The substrate can be used in standard microelectronic packaging applications.

Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.

Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.