Diffusion Of Impurity Material, E.g., Doping Material, Electrode Material, Into Or Out Of A Semiconductor Body, Or Between Semiconductor Regions; Interactions Between Two Or More Impurities; Redistribution Of Impurities (epo) Patents (Class 257/E21.135)
  • Publication number: 20130010990
    Abstract: A semiconductor microphone including a silicon substrate having a perimeter; an N-well diffused into the substrate at the perimeter; a deformable diaphragm disposed over at least a portion of the silicon substrate and in contact with at least a portion of the perimeter; and a signal channel in electrical communication with the diaphragm. The signal channel includes a microphone output channel and a feedback output channel. The diaphragm produces an electric signal on the signal channel in response to deformation of the diaphragm and a portion of the electric signal is transmitted on the feedback output channel to the N-well.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Applicant: ROBERT BOSCH GMBH
    Inventors: Sucheendran Sridharan, John Matthew Muza
  • Publication number: 20130009216
    Abstract: A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang
  • Publication number: 20130001674
    Abstract: A semiconductor device with a high voltage compensation component is manufactured by etching a trench into an epitaxial semiconductor material doped with n-type dopant atoms and p-type dopant atoms and disposing a first semiconductor or insulating material along one or more sidewalls of the trench. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for the n-type dopant atoms than the p-type dopant atoms. A second semiconductor material is disposed in the trench along the first semiconductor or insulating material. The second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Hans Weber
  • Publication number: 20120326699
    Abstract: Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Applicant: NXP B.V
    Inventors: Maarten Jacobus SWANENBERG, Dusan GOLUBOVIC
  • Publication number: 20120329251
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 27, 2012
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Jiangtao Hu
  • Patent number: 8338275
    Abstract: A method of forming a metal contact on a silicon substrate is disclosed. The method includes depositing a nanoparticle ink on a substrate surface in a pattern, the nanoparticle ink comprising set of nanoparticles and a set of solvents. The method also includes heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a densified nanoparticle layer with a nanoparticle layer thickness of greater than about 50 nm. The method further includes depositing an SiNx layer on the substrate surface, SiNx layer having a SiNx layer thickness of between about 50 nm and about 110 nm; exposing the substrate to an etchant that is selective to the densified nanoparticle layer for a second time period and at a second temperature in order to create a via; and forming a metal contact in the via, wherein an ohmic contact is formed with the silicon substrate.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 25, 2012
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Daniel Kray
  • Patent number: 8324071
    Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junhee Choi, Andrei Zoulkarneev
  • Publication number: 20120299088
    Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Lars P. Heineck, Shyam Surthi, Jaydip Guha
  • Publication number: 20120292732
    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Inventors: Gordon M. Grivna, Jefferson W. Hall, Mohammed Tanvir Quddus
  • Publication number: 20120280272
    Abstract: A maximum-punch-through semiconductor device such as an insulated gate bipolar transistor (IGBT) or a diode, and a method for producing same are disclosed. The MPT semiconductor device can include at least a two-layer structure having an emitter metallization, a channel region, a base layer with a predetermined doping concentration ND, a buffer layer and a collector metallization. A thickness W of the base layer can be determined by: W = V bd + V pt 4010 ? ? kV ? ? cm - 5 / 8 * ( N D ) 1 / 8 wherein a punch-through voltage Vpt of the semiconductor device is between 70% and 99% of a break down voltage Vbd of the semiconductor device, and wherein the thickness W is a minimum thickness of the base layer between a junction to the channel region and the buffer layer.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 8, 2012
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Arnost KOPTA, Jan VOBECKY, Wolfgang JANISCH
  • Patent number: 8304323
    Abstract: [PROBLEMS] To provide a semiconductor element manufacturing method by which a semiconductor element having high accuracy and high function can be manufactured by controlling diffusion depth and diffusion concentration in a pn junction region with high accuracy. [MEANS FOR SOLVING PROBLEMS] A diffusion control layer (2) composed of a thin film of a substance having a smaller diffusion coefficient than that of a diffusion source (3) is formed between a surface of a substrate (1) and the diffusion source (3), and an element of the diffusion source (3) is permitted to thermally diffuse through the diffusion control layer (2). Thus, the diffusion depth and the diffusion concentration in the semiconductor region, which is formed on the surface portion of the substrate and has a conductivity type different from that of the substrate, can be highly accurately controlled, and the semiconductor element having high accuracy and high function can be manufactured.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: November 6, 2012
    Assignee: Saga University
    Inventors: Thoru Tanaka, Hiroshi Ogawa, Mitsuhiro Nishio
  • Publication number: 20120273900
    Abstract: The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.
    Type: Application
    Filed: April 19, 2012
    Publication date: November 1, 2012
    Inventors: Shigeo TOKUMITSU, Akio Uenishi
  • Publication number: 20120267681
    Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.
    Type: Application
    Filed: November 2, 2010
    Publication date: October 25, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Publication number: 20120267602
    Abstract: Provided is a method for controlling a device using a doped carbon-nanostructure, and a device including the doped carbon-nanostructure, in which the method for controlling the device selectively controls the mobility of electrons or holes using N-type or P-type doped carbon-nanostructure; the N-type or P-type impurities-doped carbon-nanostructure can selectively control the transport of electrons or holes according to a doped material; and also since the doped carbon-nanostructure limits the transport of charge that is the opposite charge to the transport facilitating charge, it can improve the efficiency of device by adding to a functional layer of device or using as a separate layer in the electrons or holes-only transporting device.
    Type: Application
    Filed: November 16, 2011
    Publication date: October 25, 2012
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sang Ouk Kim, Ji Sun Park, Ju Min Lee, Myoung Hoon Song
  • Patent number: 8293613
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first insulating layer formed over the semiconductor substrate, and a first semiconductor layer formed over the first insulation layer. At least one gettering region is formed in at least one of the first insulating layer and the first semiconductor layer. The gettering region includes a plurality of gettering sites, and at least one gettering site includes one of a precipitate, a dispersoid, an interface with the dispersoid, a stacking fault and a dislocation.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Young-Nam Kim, Young-Sam Lim, Gi-Jung Kim, Pil-Kyu Kang
  • Publication number: 20120261804
    Abstract: A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Patent number: 8283241
    Abstract: A dopant device includes: a dopant holder that holds Ge which is solid at normal temperature and liquefies the Ge near a surface of the semiconductor melt, the dopant holder including a communicating hole for delivering the liquefied Ge downwardly; a cover portion for covering the Ge held by the dopant holder; and a vent provided on the cover portion for communicating with the outside. A dopant injecting method is carried out using such a dopant device, the dopant injecting method including: loading Ge dopant in a solid state into the doping device; liquefying the solid Ge dopant loaded into the doping device while holding the doping device at a predetermined height from a surface of a semiconductor melt; and doping the semiconductor melt with the liquefied Ge that is flowed from the communicating hole.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 9, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Yasuhito Narushima, Shinichi Kawazoe, Fukuo Ogawa, Toshimichi Kubota
  • Publication number: 20120252196
    Abstract: A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Robert D. Clark
  • Publication number: 20120241742
    Abstract: A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 27, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Alan G. Wood, Tim Corbett
  • Patent number: 8274081
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Publication number: 20120235230
    Abstract: In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 20, 2012
    Inventors: Chanho Park, Ashok Challa, Ritu Sodhi
  • Publication number: 20120228736
    Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
  • Publication number: 20120228629
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 13, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Publication number: 20120225544
    Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.
    Type: Application
    Filed: February 28, 2012
    Publication date: September 6, 2012
    Inventors: Manfred SCHNEEGANS, Carsten AHRENS, Adolf KOLLER, Gerald LACKNER, Anton MAUDER, Hans-Joachim SCHULZE
  • Publication number: 20120223330
    Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Applicant: CREE, INC.
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Lin Cheng, Anant Agarwal
  • Patent number: 8258559
    Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: September 4, 2012
    Assignee: Siliconfile Technologies Inc.
    Inventor: Byoung-Su Lee
  • Publication number: 20120217543
    Abstract: At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.
    Type: Application
    Filed: December 16, 2011
    Publication date: August 30, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi MINOURA, Toshihide Kikkawa, Toshihiro Ohki
  • Publication number: 20120211747
    Abstract: A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.
    Type: Application
    Filed: August 28, 2009
    Publication date: August 23, 2012
    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Paul Ronald Stribley, Soon Tat Kong
  • Patent number: 8247318
    Abstract: The present invention provides a method of providing a desired catalyst electron energy level. The method includes providing a donor material quantum confinement structure (QCS) having a first Fermi level, and providing an acceptor QCS material having a second Fermi level, where the first Fermi level is higher than the second Fermi level. According to the method the acceptor is disposed proximal to the donor to alter an electronic structure of the donor and the acceptor materials to provide the desired catalyst electron energy level.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 21, 2012
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Honda Motor Co., Ltd
    Inventors: Timothy P. Holme, Friedrich B. Prinz
  • Patent number: 8237239
    Abstract: A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: August 7, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Huang-Lang Pai, Hung-Shern Tsai
  • Patent number: 8236596
    Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The bands or chains are driven synchronously at ultra-low tension by a pin drive roller or sprocket at either the inlet or outlet end of the furnace, with appropriate tensioning systems disposed in the return path. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: August 7, 2012
    Assignee: TP Solar, Inc.
    Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter M. Ragay
  • Patent number: 8236676
    Abstract: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: August 7, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Hans-Joachim Schulze, Franz-Josef Niedernostheide
  • Publication number: 20120193769
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Application
    Filed: May 23, 2011
    Publication date: August 2, 2012
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Publication number: 20120187415
    Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.
    Type: Application
    Filed: April 5, 2012
    Publication date: July 26, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: John F. Kaeding, Hitoshi Sato, Michael Iza, Hirokuni Asamizu, Hong Zhong, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8222712
    Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
    Type: Grant
    Filed: March 8, 2009
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Shigeya Toyokawa, Kozo Watanabe, Masatoshi Taya
  • Publication number: 20120175749
    Abstract: A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Wilfried E. Haensch, Pranita Kulkarni, Tenko Yamashita
  • Publication number: 20120178201
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Inventors: YOUICHI MACHII, Masato Yoshida, Takeshi Nojiri, Kaoru Okaniwa, Mitsunori Iwamuro, Shuuichirou Adachi, Takuya Aoyagi
  • Publication number: 20120178203
    Abstract: Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 12, 2012
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Virendra V. Rana, Pranav Anbalagan
  • Patent number: 8211785
    Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaharu Itani, Takayuki Ito, Kyoichi Suguro
  • Patent number: 8206550
    Abstract: A system for manufacturing a semiconductor device that has a gate electrode and a pair of diffusion layers formed in a semiconductor substrate on sides of the gate electrode, the system including structure for forming an insulating film and a gate electrode on a semiconductor substrate, obtaining a thickness of an affected layer formed in a surface of the semiconductor substrate, forming a pair of diffusion layers by injecting an impurity element into the semiconductor substrate in areas flanking the gate electrodes based on a predetermined injection parameter, performing activating heat treatment based on a predetermined heat treatment parameter, and deriving the injection parameter or heat treatment parameter in response to the obtained thickness of the affected layer such that the diffusion layers are set to a predetermined sheet resistance.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: June 26, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hikaru Kokura
  • Patent number: 8207005
    Abstract: Embodiments of the invention contemplate the formation of a high efficiency solar cell using novel methods to form the active doped region(s) and the metal contact structure of the solar cell device. In one embodiment, the methods include the steps of depositing a dielectric material that is used to define the boundaries of the active regions and/or contact structure of a solar cell device. Various techniques may be used to form the active regions of the solar cell and the metal contact structure.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 26, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weidman, Rohit Mishra, Michael P. Stewart, Kapila P. Wijekoon, Yonghwa Chris Cha, Tristan Holtam, Vinay Shah
  • Patent number: 8193039
    Abstract: A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 5, 2012
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Publication number: 20120133026
    Abstract: An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes.
    Type: Application
    Filed: October 29, 2008
    Publication date: May 31, 2012
    Inventors: Jianhua Yang, Duncan Stewart, Phillip J. Kuekes, William M. Tong
  • Publication number: 20120129293
    Abstract: The invention relates to methods of making unsupported articles of semiconducting material using thermally active molds having an external surface temperature, Tsurface, and a core temperature, Tcore, whererin Tsurface>Tcore.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 24, 2012
    Inventors: Sergey Potapenko, Balram Suman, Lili Tian, Alex Usenko
  • Patent number: 8183666
    Abstract: A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Schulze
  • Publication number: 20120122306
    Abstract: A diffusing agent composition contains a condensation product (A) and an impurity diffusion component (B). The condensation product (A) is a reaction product yielded by hydrolyzing an alkoxysilane. The impurity diffusion component (B) is a monoester or diester of phosphoric acid, or a mixture thereof.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 17, 2012
    Applicant: c/o Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Takashi Kamizono
  • Publication number: 20120119265
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Publication number: 20120119267
    Abstract: A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.
    Type: Application
    Filed: August 5, 2011
    Publication date: May 17, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Eiji Yoshida
  • Patent number: 8178431
    Abstract: The invention relates to a process for producing a p-n junction in a nanostructure, in which the nanostructure has one or more nanoconstituents made of a semiconductor material with a single type of doping having one conductivity type, characterized in that it includes a step consisting in forming a dielectric element (3, 32, . . . , 3n) embedding the nanostructure over a height h, the dielectric element generating a surface potential capable of inverting the conductivity type over a defined width W of the nanoconstituents(s) thus embedded over the height h.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: May 15, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Eddy Romain-Latu, Philippe Gilet
  • Publication number: 20120097204
    Abstract: A nanomesh phononic structure includes: a sheet including a first material, the sheet having a plurality of phononic-sized features spaced apart at a phononic pitch, the phononic pitch being smaller than or equal to twice a maximum phonon mean free path of the first material and the phononic size being smaller than or equal to the maximum phonon mean free path of the first material.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 26, 2012
    Inventors: Jen-Kan Yu, Slobodan Mitrovic, James R. Heath