Abstract: A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

Abstract: Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.

Abstract: A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.

Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.

Abstract: A method of reducing the loss of elements of a photovoltaic thin film structure during an annealing process, includes depositing a thin film on a substrate, wherein the thin film includes a single chemical element or a chemical compound, coating the thin film with a protective layer to form a coated thin film structure, wherein the protective layer prevents part of the single chemical element or part of the chemical compound from escaping during an annealing process, and annealing the coated thin film structure to form a coated photovoltaic thin film structure, wherein the coated photovoltaic thin film retains the part of the single chemical element or the part of the chemical compound that is prevented from escaping during the annealing by the protective layer.

Abstract: A template for imprinting in which a pattern is transferred onto a first substrate applied curable resin thereon, including a second substrate having a surface to be contacted with the curable resin, a concave portion provided on the surface and corresponding to a pattern to be transferred onto the first substrate, and at least one convex portion arranged in the concave portion to decrease volume of the concave portion.

Abstract: Methods of fabricating a memory device can include forming a plurality of wordlines on a semiconductor substrate. A ground select line can be formed on a first side of the wordlines. A string select line can be formed on a second side of the wordlines. The wordlines can extend between the ground select line and the string select line. First spacers may be formed between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines. Second spacers can be formed on sidewalls of the ground select line and the string select line displaced from the first spacers. The second spacers can be formed from a different material than the first spacers.

Abstract: A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.

Abstract: An embodiment relates a method comprising creating a reversible change in an electrical property by adsorption of a gas by a composition, wherein the composition comprises a noble metal-containing nanoparticle and a single walled carbon nanotube. Another embodiment relates to a method comprising forming a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube and forming a device containing the said composition. Yet another method relates to a device comprising a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube on a silicon wafer, wherein the composition exhibits a reversible change in an electrical property by adsorption of a gas by the composition.

Abstract: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.

Abstract: The present invention relates to a functional device in which it is possible to improve durability by inhibiting corrosion due to an electrolyte solution, and it is possible to reduce series resistance, and also relates to a method for producing the same. A functional device includes a transparent photoelectrode including a photoelectric substrate 11 and a photoelectrode layer 12a, a counter electrode substrate 18a composed of a metal, an electrolyte solution 15 filled in a space between the two substrates, a corrosion-resistant conductive layer 17a which is disposed on the counter electrode substrate and has corrosion resistance to the electrolyte solution, and a conductive catalyst layer 16. The counter electrode substrate is composed of any of Al, Cu, Ag, Au, and SUS; the corrosion-resistant conductive layer is composed of any of Ti, Cr, Ni, Nb, Mo, Ru, Rh, Ta, W, In, Pt, and Hastelloy; and the conductive catalyst layer is composed of any of carbon, Tu, Rh, Pd, Os, Ir, Pt, and conductive polymers.

Abstract: A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell.

Abstract: A semiconductor memory includes a composite floating structure where an insulation film is formed on a semiconductor substrate, Si-based quantum dots covered with an extremely thin Si oxide film is formed on the insulation film, silicide quantum dots covered with a high dielectric insulation film are formed on the extremely thin Si oxide film, and Si-based quantum dots covered with a high dielectric insulation film are formed on the high dielectric insulation film. Multivalued memory operations can be conducted at a high speed and with stability by applying a certain positive voltage to a gate electrode to accumulate electrons in the silicide quantum dots and by applying a certain negative voltage and weak light to the gate electrode to emit the electrons from the silicide quantum dots.

Abstract: An ashing method of a target substrate is applied after plasma-etching a part of a low-k film by using a patterned resist film as a mask in a vacuum processing chamber. The method includes a process of removing the resist film in the vacuum processing chamber, and a pre-ashing process, performed prior to the main ashing process, for ashing the target substrate for a time period while maintaining the target substrate at a temperature in a range of from about 80 to 150° C.

Abstract: Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.

Abstract: To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×10?1 A/cm2 or less, (3) suppress hysteresis caused by the generation of fixed charges, and (4) prevent an increase in EOT even if heat treatment at 700° C. or more is performed and obtain excellent heat resistance.

Abstract: A semiconductor device comprises a buried gate formed by being buried under a surface of a semiconductor substrate, a dummy gate formed on the buried gate, and a landing plug formed on a junction region of the semiconductor substrate being adjacent to the dummy gate.

Abstract: Nanoelements such as single walled carbon nanotubes are assembled in three dimensions into a nanoscale template on a substrate by means of electrophoresis and dielectrophoresis at ambient temperature. The current-voltage relation indicates that strong substrate-nanotube interconnects carrying mA currents are established inside the template pores. The method is suitable for large-scale, rapid, three-dimensional assembly of 1,000,000 nanotubes per square centimeter area using mild conditions. Circuit interconnects made by the method can be used for nanoscale electronics applications.

Abstract: It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method. Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer.

Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

Abstract: A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.

Abstract: A semiconductor device is provided with first and second silicon pillars formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surfaces of the first and second silicon pillars via a gate insulation film, first and second diffusion layers provided on a lower part and an upper part of the first silicon pillar, respectively, a cap insulation film covering an upper part of the second silicon pillar, a gate contact connected to the gate electrode, and a protection insulation film in contact with the upper surfaces of the first and second silicon pillars. The gate contact is connected to an upper region of the gate electrode provided at the periphery of the cap insulation film. An opening is formed on the protection insulation film provided at the side of the first silicon pillar.

Abstract: Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer.

Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer, a second metal layer, a metal via layer and an insulating layer. The first metal layer and the second metal layer are patterned and aligned symmetrically so as to form etching through holes. The metal via layer surrounds each etching through hole. The insulating layer fills each etching through hole and is disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole and the insulating layer between the substrate and the metal layer so as to form a suspended multilayer microstructure on the substrate.

Abstract: A semiconductor device has a singulated die having a substrate and a die edge. An interconnect dielectric layer is located on the substrate, and integrated circuit has interconnections located within the interconnect dielectric layer. A trench is located in the interconnect dielectric layer and between a seal ring and a remnant of the interconnect dielectric layer. The seal ring is located within the interconnect dielectric layer and between the trench and the integrated circuit, with the remnant of the interconnect dielectric layer being located between the trench and the edge of the die.

Abstract: A method of manufacturing a semiconductor device includes depositing a first capping layer on a dielectric layer. The method also includes etching the first capping layer from a second portion of the semiconductor device. The first capping layer remaining in a first portion of the semiconductor device may form a PMOS device. The method further includes depositing a second capping layer after etching the first capping layer. After the second capping layer is deposited a maskless process results in selectively etching the second capping layer from the first portion of the semiconductor device. The second portion of the semiconductor device may be a NMOS device. The method described may be used in manufacturing integrated CMOS devices as scaling reduces device size. Additionally, the method of selectively etching capping layers may be used to manufacture multi-threshold voltage devices.

Abstract: This invention pertains to silsesquioxane resins useful in antireflective coatings wherein the silsesquioxane resin is comprised of the units (Ph(CH2)rSiO(3?x)/2(OR?)x)m (HSiO(3?x)/2(OR?)x)n (MeSiO(3?x)/2(OR?)x)o (RSiO(3?x)/2(OR?)x)p (R1SiO(3?x)/2(OR?)x)q where Ph is a phenyl group, Me is a methyl group; R? is hydrogen atom or a hydrocarbon group having from 1 to 4 carbon atoms; R is selected from a hydroxyl producing group; and R1 is selected from substituted phenyl groups, ester groups, polyether groups; mercapto groups, and reactive or curable organic functional groups; and r has a value of 0, 1, 2, 3, or 4; x has a value of 0, 1 or 2; wherein in the resin m has a value of 0 to 0.95; n has a value of 0.05 to 0.95; o has a value of 0.05 to 0.95; p has a value of 0.05 to 0.5; q has a value of 0 to 0.5; and m+n+o+p+q?1.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: A method of forming patterns of a semiconductor device comprises forming a number of first insulating patterns that define sidewalls by patterning a first insulating layer formed over a semiconductor substrate, forming second insulating patterns, each second insulating pattern comprising a horizontal portion having two ends and being parallel to the semiconductor substrate and spaced protruding portions protruding from both ends of the horizontal portion parallel to the sidewalls of the first insulating patterns, forming third insulating patterns each filling a space between the protruding portions, removing the protruding portions to form trenches, and forming conductive patterns within the respective trenches.

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.

Abstract: A method of forming an ohmic layer for a semiconductor device includes forming a metal layer on a Silicon Carbide (SiC) layer and forming an ablation capping layer on the metal layer. Laser light is impinged through the ablation capping layer to form a metal-SiC material.

Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Abstract: Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.

Abstract: A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber.

Abstract: A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.

Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.

Abstract: The present invention relates to a substrate notably designed to enter into the constitution of a solar cell, of which one face, called the inner face, is designed to receive a molybdenum-based conductive element. This substrate is characterized in that the conductive element is formed of several layers based on molybdenum, at least one of these layers being enriched with molybdenum oxide. The present invention also relates to solar cells employing such a substrate and a method for producing same.