On Flat Or Curved Insulated Base, E.g., Printed Circuit, Etc. Patents (Class 29/829)
  • Publication number: 20130078408
    Abstract: A segmentable wiring board includes a ceramic base body, a conductor, a metal plating film and a glass layer, the glass layer having an upwardly-protruding convexity located on the metal plating film. The ceramic base body has a plurality of wiring substrate regions and dividing grooves located in boundaries among the plurality of wiring substrate regions. Moreover, the conductor is located in a periphery of each of the plurality of wiring substrate regions. Moreover, the metal plating film is located on the conductor. Further, the glass layer coveringly extends from an inner surface of each of the dividing grooves of the ceramic base body to the metal plating film.
    Type: Application
    Filed: May 28, 2011
    Publication date: March 28, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Noritaka Niino, Masaya Ochi
  • Publication number: 20130077264
    Abstract: An electronic apparatus partially overmolded with a overmold sealing material that seals the circuit board, protects the electrical components on the circuit board and provides seals between the circuit board and mating devices is disclosed. The electronic apparatus may be an engine controller. The electrical components may be an electrical edge connector, a sensor, and a heat sink. The sensor may be a pressure sensor. The controller may be connected to a throttle body such that the overmold sealing material provides a first seal between the controller and the throttle body allowing the pressure sensor to be in fluid communication with the interior of the throttle body. A wire harness may be connected to the controller such that the overmold sealing material provides a second seal between the wire harness and the controller protecting the electrical connection. The overmold sealing material may also be translucent.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: ELECTROJET, INC.
    Inventor: Kyle E. E. Schwulst
  • Publication number: 20130074593
    Abstract: According to one embodiment, a first substrate has a pair of thermosensitive films, a heater film, and a passage protective film having corrosion resistance in a passage forming region on a first main surface, and has a metal sealing film having corrosion resistance in a region other than the passage forming region. A second substrate has a groove formed in the passage forming region on a second main surface and a side wall forming portion separating other regions other than the passage forming region from the groove and protruding beyond the other regions. A fixing member fixes the first substrate to the second substrate. The side wall forming portion of the second substrate is compression bonded so that the side wall forming portion is located on the metal sealing film on the first substrate.
    Type: Application
    Filed: March 14, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideo ETO, Makoto SAITO
  • Patent number: 8402644
    Abstract: A method of manufacturing an electronic parts packaging structure including the steps of preparing a plurality of sheet-like units each of which is constructed by a first insulating layer, a wiring formed on one surface of the first insulating layer, electronic parts connected to the wiring, a second insulating layer formed on an one surface side of the first insulating layer to cover the electronic parts, and a connecting portion for connecting electrically the wiring, and stacking mutually the units to arrange directions of unit adjacent in a thickness direction alternately oppositely, and bonding the units such that electronic parts of respective units are electrically connected mutually via connecting portions.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 26, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Gomyo, Yukiharu Takeuchi, Hidenori Takayanagi, Takaharu Yamano
  • Publication number: 20130069639
    Abstract: A flexible printed circuit board (PCB) magnetostrictive (MS) sensor comprising a first direct current (DC) bias PCB layer comprising a first plurality of conductive traces, a first alternating current (AC) PCB layer disposed on the first DC bias PCB layer, the first AC PCB layer comprising a first AC coil, a pocket PCB layer disposed on the first AC PCB layer, the pocket PCB layer to receive a strip of MS material, a second AC PCB layer disposed on the pocket PCB layer, the second AC PCB layer comprising a second AC coil, and a second DC bias PCB layer disposed on the second AC PCB layer, the second DC bias PCB layer comprising a second plurality of conductive traces. The traces from the first plurality of conductive traces are electrically coupled to traces from the second plurality of conductive traces.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 21, 2013
    Applicant: Southwest Research Institute
    Inventors: Adam C. COBB, Jonathan D. BARTLETT, Charles E. DUFFER
  • Publication number: 20130069686
    Abstract: A probing device and manufacturing method thereof are provided. The manufacturing method includes first disposing a plurality of space transformers on a reinforcing plate and the space transformer includes several first pads. Then, the space transformer is fixed on the reinforcing plate. Thereafter, photoresist films having a plurality of openings is formed on the space transformer. The first pads are disposed in the openings. After that, a metal layer is formed and covered on the first pad. Later, the photoresist film is removed and the metal layer is planarized to form a second pad. Afterwards, the reinforcing plate is electrically connected with a PCB. Thereafter, a probe head having a plurality of probing area is provided and each probing area is corresponding to one of the space transformer. The probes in the probing area are electrically connected with the internal circuitry of the space transformer.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 21, 2013
    Applicant: MPI corporation
    Inventors: Chien-Chou Wu, Ming-Chi Chen, Chung-Che Li
  • Publication number: 20130067739
    Abstract: A flip-chip bonder fabricates an optical assembly by horizontally positioning a flexible portion of a substrate including a waveguide with the waveguide exposed at one end edge of the substrate; bending a portion of the flexible substrate to place the waveguide exposed end in approximately a vertical position; vertically positioning a bond head containing an optical component upon the waveguide exposed substrate edge to optically mate the optical component with the exposed waveguide; and fixably mounting the optical component to the substrate edge.
    Type: Application
    Filed: November 14, 2012
    Publication date: March 21, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Publication number: 20130068505
    Abstract: Methods for chemically strengthening the edges of glass sheets are provided. Voids can be formed in a mother sheet. The edges of these voids may correspond to a portion of the new edges that would normally be created during separation and free shaping of the mother sheet. The mother sheet can then be immersed in a chemical strengthener. The edges of the voids can be chemically strengthened in addition to the front and back sides of the mother sheet. After thin film processing and separation, each of the resulting individual sheets has been chemically strengthened on both sides and on a portion of its edges.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 21, 2013
    Inventors: Seung Jae Hong, Casey J. Feinstein, Lili Huang, Sunggu Kang, Kuo-Hua Sung, John Z. Zhong
  • Publication number: 20130071071
    Abstract: Assembling an optical transceiver. A connector housing for a semiconductor package may be received. The connector housing may include a first alignment feature for assembling the optical transceiver. Additionally, a semiconductor package may be received. The semiconductor package may include a leadframe that has a second alignment feature which is complementary to the first alignment feature. The semiconductor package may be attached to the connector housing to form the optical transceiver by aligning the second alignment feature of the leadframe of the semiconductor package with the first alignment feature of the connector housing. This alignment may operate to align an optical axis a fiber optic transmitter and/or a fiber optic receiver with a corresponding fiber optic connector.
    Type: Application
    Filed: February 28, 2012
    Publication date: March 21, 2013
    Inventors: Markus N. Becht, Galin I. Ivanov, Evan L. Marchman
  • Patent number: 8399767
    Abstract: Sealing devices are provided along with methods of installing energy dissipating tubing. An aspect of the invention provides a sealing device for connecting an energy dissipative tube having a length of tubing, a first resin layer surrounding the outside of the tubing, a conductive layer adjacent to the outside of the first resin layer, and a second resin layer surrounding the conductive layer and the first resin layer. The sealing device includes one or more penetrating members configured to penetrate the second resin layer and establish electrical continuity with the conductive layer.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: March 19, 2013
    Assignee: Titeflex Corporation
    Inventors: Scott Duquette, Brian Coppola
  • Publication number: 20130061468
    Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.
    Type: Application
    Filed: November 6, 2012
    Publication date: March 14, 2013
    Inventor: Shih-Hao Sun
  • Publication number: 20130063217
    Abstract: There are provided a surface-mounted crystal oscillator and a manufacturing method thereof which can realize miniaturization, improve quality, reduce a manufacturing cost, and enhance productivity. According to the surface-mounted crystal oscillator and the manufacturing method thereof, through terminals and of AgPd are formed on wall surfaces of through holes formed at corner portions of a rectangular ceramic substrate, a metal electrode of a support electrode lower portion of AgPd which is connected to the through terminal and forms a lower layer of a support electrode is formed on a front side of the substrate, the support electrode which holds a crystal piece is formed on the support electrode lower layer portion by using Ag, and a cover is mounted on an insulating film formed on the inner side of the periphery of the substrate and effect airtight sealing.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 14, 2013
    Applicant: NIHON DEMPA KOGYO CO., LTD.
    Inventor: MASASHI SATO
  • Publication number: 20130063314
    Abstract: A mobile wireless communications device may include a portable housing and a printed circuit board (PCB) carried by the portable housing. The mobile wireless communications device may also include at least one electronic component carried by the PCB and an electrically conductive enclosure coupled to the PCB and having a top spaced above the PCB over the at least one electronic component. The top of the electrically conductive enclosure may have a slot therein defining a slot antenna.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: Research In Motion Limited
    Inventors: John Alfred Whitmore, Ying Tong Man
  • Publication number: 20130062091
    Abstract: The invention relates to a main housing element for a multi-part housing of an electrical device. The main housing element consists of a frame element and at least one connector element integrated in the frame element and produced in one piece with the frame element. The connecting region between the at least one connector element and the frame element is configured as a predetermined breaking point. In the course of assembly of the main housing element a mechanical separation of the connector element from the frame element takes place, whereby the connector element and the frame element are uncoupled.
    Type: Application
    Filed: March 18, 2010
    Publication date: March 14, 2013
    Applicant: ROBERT BOSCH GMBH
    Inventors: Jibu John, Thomas Fuerst, Jörg Huttenlocher
  • Patent number: 8395903
    Abstract: An interconnect array uses repeated application of an interconnect pattern (“tile”). The tile has eight I/O signal pins forming a perimeter array, a central pin that can be either a ground pin or an I/O power pin, and an offset ground pin. The I/O signal pins are associated with the same or multiple I/O banks. If the central pin is an I/O power pin, it is optionally associated with an I/O bank associated with one or more of the I/O signal pins.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: March 12, 2013
    Assignee: Xilinx, Inc.
    Inventors: Paul Ying-Fung Wu, Richard L. Wheeler
  • Publication number: 20130058050
    Abstract: According to exemplary embodiments, a controlled-depth slot extending into a circuit board is provided. The controlled depth slot may be milled, and may comprise ½ radial plated through-holes to generate a solderable “D” interconnect feature. The slot may include interconnect features on one to five sides. According to another exemplary embodiment, a circuit board having a depth-controlled interconnect slot is provided in conjunction with one or more solderable technology modules. The one or more solderable technology modules may include memory devices, power devices such as Point of Load Supplies (POLS), security devices and anti-tamper devices, capacitance devices, and other types of chips such as Field Programmable Gate Arrays (FPGAs). The solderable technology modules may be soldered into the slot to secure the modules in the slot and connect the modules to interconnects on the circuit board.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Applicant: MERCURY COMPUTER SYSTEMS, INC.
    Inventors: Darryl J. MCKENNEY, Daniel TOOHEY, Stephen MARIANI, Michael GUST, Absu METHRATTA, Timothy FLEURY, Steven IMPERALLI
  • Publication number: 20130055566
    Abstract: A method for introducing electrical insulations in a printed circuit board includes selectively introducing groove-shaped recesses between different regions of an electrically conductive layer on a substrate along a machining path using a thermal energy input such that end portions of each of the recesses or different ones of the recesses are joined to one another. The end portions are introduced parallel to one another without overlap such that a strip-shaped region of the conductive layer is initially retained between the end portions so as to insulate the different regions.
    Type: Application
    Filed: March 23, 2011
    Publication date: March 7, 2013
    Applicant: LPKF LASER & ELECTRONICS AG
    Inventor: Jan Van Aalst
  • Patent number: 8389870
    Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim, Rohan Mandrekar
  • Publication number: 20130050962
    Abstract: A device for protecting a circuit board from electromagnetic interference, and which includes shield to be attached to the circuit board. The device includes a metal plate and a plurality of tangs. The metal plate has a perimeter portion. The plurality of tangs are spaced about and extend transversely away from at least a portion of the perimeter portion of the metal plate. Each tang includes a bridge portion and a finger portion. The bridge portion has a first end attached to the perimeter portion and a second end spaced away from the perimeter portion and attached to the finger portion. The finger portion extends away from the second end of the bridge potion and is disposed at an obtuse angle relative to the bridge portion such that the plurality of tangs, in combination, are adapted to receive the circuit board.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Applicant: FISHER CONTROLS INTERNATIONAL LLC
    Inventors: Scott R. Kratzer, Davin S. Nicholas, Barry L. Gaarder
  • Publication number: 20130052847
    Abstract: An information handling system mezzanine circuit board disposed in a parallel configuration over a motherboard is selectively coupled and de-coupled at the motherboard with a retraction and latching device that translates retraction force applied at an accessible actuation portion to push upward from below the mezzanine circuit board. A retraction portion of the retraction and latching device provides an upward force at the bottom surface of the mezzanine circuit board to separate the mezzanine circuit board connector from the motherboard connector so that an end user can lift the mezzanine circuit board away from the motherboard.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 28, 2013
    Inventors: Stephen N. Figuerado, Martin Hardis
  • Publication number: 20130048363
    Abstract: A circuit board includes a board, a first signal trace and a second signal trace on the board, a first solder pad formed on the board and connected to a terminal of the first signal trace near to one end of the second signal trace, and a second pad formed on the board and connected to a terminal of the second signal trace near to the first solder pad. The second pad is apart from the first pad. The first pad or the second pad is coated with solder. After heated, the solder melts and spread to the second pad or the first pad, thereby connecting the first signal trace to the second signal trace.
    Type: Application
    Filed: November 24, 2011
    Publication date: February 28, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: CHENG-FEI WENG, ZHENG-HENG SUN
  • Patent number: 8384216
    Abstract: A manufacturing method of a package structure is provided. A metal substrate is provided. The metal substrate has a first surface where a first seed layer is formed. A patterned insulating layer is formed on the first seed layer and exposes a portion of the first seed layer. A patterned circuit layer is formed on the exposed portion of the first seed layer and covers a portion of the patterned insulating layer. A chip-bonding process is performed to electrically connect a chip to the patterned circuit layer. An encapsulant encapsulating the chip and the patterned circuit layer and covering a portion of the pattered insulating layer is formed. The metal substrate and the first seed layer are removed to expose a bottom surface of the patterned insulating layer and a lower surface of the patterned circuit layer. Solder balls are formed on the lower surface of the patterned circuit layer.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: February 26, 2013
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Publication number: 20130044470
    Abstract: The invention discloses a method for manufacturing a three-dimensional tensile and helical circuit board for a LED lamp comprises the steps of: forming a helical continuous carved wire slot on a circuit board; providing a patch light-emitting diode tube 4 to be welded in between the helical continuous carved wire slot; and directly tensioning a center of the circuit board and lifting the tensioned circuit board along the helical continuous carved wire slot to form as the three-dimensional tensile and helical circuit board. The invention enable the light to be uniformly projected on a lamp shade from the LED patches, realizing the LED lamp with a long life span, low manufacturing cost and excellent reliability.
    Type: Application
    Filed: October 22, 2011
    Publication date: February 21, 2013
    Inventors: Guang-Yi WU, Shao-Ai XIANG
  • Publication number: 20130036829
    Abstract: An optical shear sensor that includes a first and second outer surface at opposing sides and a sensing element is disclosed. In one aspect, the sensing element has an optoelectronic source for emitting light of a predetermined wavelength and having a source front surface where light exits the optoelectronic source, and a photodetector for detecting light of the predetermined wavelength and having a detector front surface where light of the optoelectronic source is received. The optoelectronic source is positioned along the first outer surface and emits light towards the second outer surface. A flexible sensing layer transparent to the predetermined wavelength covers the front surface of the optoelectronic source and the front surface of the photodetector. Upon application of a shear stress, the sensing layer deforms elastically and the outer surfaces are displaced along directions parallel to each other and the source front surface so the intensity of light detected by the photodetector changes.
    Type: Application
    Filed: October 2, 2012
    Publication date: February 14, 2013
    Applicants: Universiteit Gent, IMEC
    Inventors: IMEC, Universiteit Gent
  • Patent number: 8371005
    Abstract: A method of manufacturing a stacked piezoelectric element that can suppress periodic damping on miniaturization of a vibration wave motor and improve its performance. A stacked piezoelectric element comprises piezoelectric layers and electrode layers alternately stacked to have a shape of a cylinder. The electrode layers are divided into a plurality of electrode layer regions along a circumferential surface of the shape of a cylinder.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: February 12, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yutaka Maruyama, Kaishi Ohashi, Takayuki Tsukimoto
  • Publication number: 20130032388
    Abstract: The present invention relates to a method of making a cavity substrate. The method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier, an adhesive and an electrical pad, wherein the adhesive bonds the stiffener to the sacrificial carrier; forming a coreless build-up circuitry on the supporting board in contact with the bump and the stiffener; and removing the bump to form a cavity and expose the electrical pad from a closed end of the cavity, wherein the cavity is laterally covered and surrounded by the adhesive. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical pad. The coreless build-up circuitry provides signal routing for the semiconductor device while the built-in stiffener can provide adequate mechanical support for the coreless build-up circuitry and the semiconductor device.
    Type: Application
    Filed: June 26, 2012
    Publication date: February 7, 2013
    Inventors: Charles W.C. LIN, Chia Chung WANG
  • Patent number: 8365402
    Abstract: A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: February 5, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshiki Furutani, Takeshi Furusawa
  • Patent number: 8367939
    Abstract: Embodiments of the invention provide an interconnect substrate capable of improving the connection reliability and yield of a semiconductor device, a method of manufacturing the interconnect substrate, and a semiconductor device using the interconnect substrate. An interconnect substrate according to an embodiment of the invention includes: a substrate; an electrode pad formed over the substrate; an insulating film (solder resist film) formed over the substrate; an opening formed in the insulating film, in which the upper surface of the electrode pad is exposed on the bottom surface of the opening and a metal film formed over the upper surface of the electrode pad and side surface of the insulating film in the opening. At least a portion of the edge of an upper surface of the metal film is higher than the other portions of the upper surface of the metal film.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kiminori Ishido
  • Publication number: 20130025917
    Abstract: To prevent the breakage of the joint between a ceramic substrate and a glass epoxy substrate. The copper column is formed by a wiredrawing step for drawing a copper wire formed linearly to a predetermined diameter; a cutting step for cutting the copper wire, which has been drawn in the wire drawing step, in a predetermined length; a pressing step for pressing one end of the copper wire, which has been cut in the cutting step, in a longitudinal direction to form a copper column member; and an annealing step for annealing the copper column member, which has been formed in the pressing step, by maintaining a heating period of 60 minutes or longer at 600° C. or higher. Thereby, the Vickers hardness of the copper column becomes is 55 HV or less and the copper column is softened.
    Type: Application
    Filed: February 22, 2011
    Publication date: January 31, 2013
    Applicant: SENJU METAL INDUSTRY CO., LTD
    Inventors: Yutaka Chiba, Shinichi Nomoto, Koji Watanabe
  • Publication number: 20130020606
    Abstract: An LED device with improved circuit board LED support structure is presented. A top surface of a thermally-conductive substrate of this LED device comprises a thermally-conductive pillar. The pillar is not covered with a dielectric layer and an LED package is arranged directly on the pillar with the LED packages bottom thermally-conductive plate in direct contact with the pillar top surface.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Inventors: Chang HAN, Lac NGUYEN
  • Patent number: 8356407
    Abstract: Films and electronic devices can be released from metallic substrates by: (i) applying a coating of a polysilsesquioxane resin to a metallic substrate, (ii) heating the coated metallic substrate to a temperature sufficient to cure the polysilsesquioxane resin, (iii) applying a polymeric film to the cured coating on the metallic substrate, (iv) further heating the coated metallic substrate to a temperature sufficient to cure the polymeric film, (v) optionally fabricating electronic devices on the polymeric film, and (vi) releasing the polymeric film from the metallic substrate.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: January 22, 2013
    Assignee: Dow Corning Corporation
    Inventors: Nicole Anderson, Dimitris Elias Katsoulis, Bizhong Zhu
  • Patent number: 8356406
    Abstract: A method of manufacturing an electronic device includes: roughening an underside surface of a film made of a resin, opposite to a mounting surface of the film for mounting a circuit chip; forming a conductor pattern on the mounting surface of the film, thereby obtaining a substrate made of the film where the conductor pattern is formed; and attaching a thermoset adhesive to a conductor-pattern-formed surface of the substrate. The method further includes: mounting the circuit chip to be connected to the conductor pattern on the substrate via the thermoset adhesive; clamping the substrate by a heating apparatus having a presser section and a support section, the presser section abutting the circuit chip mounted on the substrate and the support section abutting the underside surface of the roughened film; and fixing the circuit chip to the conductor pattern by heating and hardening the thermoset adhesive using the heating apparatus.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: January 22, 2013
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Kobayashi
  • Publication number: 20130016480
    Abstract: A printed circuit board (PCB) having heat gathering structures is used for enabling electronic components with pins to be inserted thereon. The PCB includes a base, at least one insertion hole, and at least one heat gathering hole. The base has a first surface and a second surface. The insertion hole penetrates the base, and the base has soldering pad on the periphery of the insertion hole. A first electric conducting layer is disposed on the inner wall of each insertion hole. The heat gathering hole penetrates the base. A second electric conducting layer is disposed on the inner wall of each heat gathering hole. The temperature of the insert holes will be increased for improving soldering process. A manufacturing process of the PCB having heat gathering structures is also disclosed.
    Type: Application
    Filed: November 9, 2011
    Publication date: January 17, 2013
    Inventor: Wen-Ji SUN
  • Publication number: 20130014595
    Abstract: The force sensor assembly has axis of measurement along an axial direction of the force sensor assembly and comprises a force ring provided with at least two sensing elements, a printed circuit board having electronic components thereon, a covering plate for holding the printed circuit board onto the force ring, and a sensor cap covering the printed circuit board and covering plate and attached to the force ring. Manufacturing is easily accomplished using stacking, fixing and welding.
    Type: Application
    Filed: June 25, 2012
    Publication date: January 17, 2013
    Inventors: Alex Huizinga, Robert Zwijze, Martijn Pijpers, Bennie Berkel
  • Patent number: 8353101
    Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: January 15, 2013
    Assignee: Intel Corporation
    Inventors: Charan Gurumurthy, Sanka Ganesan, Chandrashekar Ramaswamy, Mark Hlad
  • Patent number: 8354596
    Abstract: A wiring board including a main substrate including a base material and having an opening portion, and a flex-rigid printed wiring board connected to the main substrate in the opening portion of the main substrate and including a rigid substrate and a flexible substrate, the rigid substrate including a non-flexible base material, the flexible substrate including a flexible base material.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 15, 2013
    Assignee: Ibiden Co., Ltd.
    Inventor: Michimasa Takahashi
  • Patent number: 8353103
    Abstract: A method of manufacturing multilayer printed wiring hoard in which electric connectivity and functionality are obtained by improving reliability and particularly, reliability to the drop test can be improved. In the inventive method, no corrosion resistant layer is formed on a solder pad on which a component is to be mounted so as to obtain flexibility. Thus, if an impact is received from outside when a related product is dropped, the impact can be buffered so as to protect any mounted component from being removed. On the other hand, a land in which the corrosion resistant layer is formed by the method is unlikely to occur contact failure even if a carbon pillar constituting an operation key makes repeated contacts.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: January 15, 2013
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasuhiro Watanabe, Michimasa Takahashi, Masakazu Aoyama, Takenobu Nakamura, Hiroyuki Yanagisawa
  • Publication number: 20130010432
    Abstract: Example printed board assembly (PBA) interfaces are described. In some examples, the disclosure relates to a printed board (PB) including a conductive layer, where the PB defines a first surface and a recess in the first surface, where a surface defining the recess is at least one of electrically or thermally connected to the conductive layer, and an electrical component body mounted on the PB. The electrical component body may be mounted on the PB such that a surface of the electrical component body extends over at least a portion of the recess, where the recess extends beyond the electrical component body such that the recess defines an aperture for introducing an interface material between the surface of the electrical component body and the surface of the recess.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Lance LeRoy Sundstrom, Michael Gillespie, Rainer Blomberg
  • Publication number: 20130008705
    Abstract: A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.
    Type: Application
    Filed: October 26, 2011
    Publication date: January 10, 2013
    Applicant: UNIMICRON TECHNOLOGY CORPORATION
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Publication number: 20130003292
    Abstract: A low profile heat removal system suitable for removing excess heat generated by an integrated circuit operating in a compact computing environment is disclosed.
    Type: Application
    Filed: August 31, 2011
    Publication date: January 3, 2013
    Applicant: Apple Inc.
    Inventors: Brett W. DEGNER, Gregory Tice
  • Publication number: 20130000966
    Abstract: A wire bonding joint structure of a joint pad in which electroless surface treatment plating layers of joint pads configured by a nickel layer/a palladium layer/a gold layer are connected to each other by a metal wire and when the metal wire is joined to the electroless surface treatment plating layer, a depth of the wire bonding pad formed by wedge deformation is 1.0 m or more. The electroless surface treatment layer of the joint pad can lower strength and hardness of the wire bonding pad of which the surface is treated to improve follow-up capability between a gold wire and the bonding pad, such that a joint area between the gold and the bonding pad is maximized, thereby increasing joinability at the wire bonding finish process by wedge pressure and greatly improving wire bonding workability.
    Type: Application
    Filed: May 15, 2012
    Publication date: January 3, 2013
    Inventor: Dong Jun LEE
  • Patent number: 8342652
    Abstract: An ink jet print head includes a molded nozzle plate, the molded nozzle plate further including molded die alignment features. The molded die alignment features can be registered to the apertures of the print head die.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: January 1, 2013
    Assignee: Xerox Corporation
    Inventors: Peter J. Nystrom, Scott Phillips, Mark Cellura
  • Patent number: 8344257
    Abstract: A flexible printed circuit and fabrication method thereof is provided. At least one signal wire is disposed on a plastic substrate. Two ground lines are disposed at both sides of the signal wire in parallel. A shielding layer is provided, contacting the plastic substrate to form a chamber, wherein the signal wire and ground lines are wrapped therein. A flexible dielectric layer is implemented between the signal wire and the shielding layer to provide electricity isolation.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: January 1, 2013
    Assignee: HTC Corporation
    Inventors: Chung-Lun Wu, Fu-An Chu, Ja-Ee Li
  • Publication number: 20120327626
    Abstract: One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 27, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Michio Horiuchi, Yasue Tokutake, Yuichi Matsuda, Tomoo Yamasaki
  • Publication number: 20120324723
    Abstract: The present invention has been made in an effort to provide a method of manufacturing a coreless substrate that forms an opening by patterning a dry film for forming the opening onto one surface of a carrier, separating the carrier from the substrate, and removing only the dry film for forming the opening. In the present invention, since the pad can be exposed by removing only the dry film for forming the opening, a process time for forming the opening can be reduced and since a process is simple, a cost is saved.
    Type: Application
    Filed: April 17, 2012
    Publication date: December 27, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myeong Ho Hong, Byung Moon Kim, Hyun Hee Ku, Soon Oh Jung, Jae Joon Lee
  • Publication number: 20120327583
    Abstract: A robust printed circuit board (PCB) that includes at least two power layers that are used in providing power to components connected to the PCB. The power layers may be a power plane layer and a ground plane layer. The power plane layer is situated such that its edge is pulled back a second distance from the planar edge of the PCB. The ground plane layer is situated such that its edge is pulled back a first distance from the planar edge of the PCB. The second distance and the first distance are different, and as a result, the planar edges of the power plane layer and the ground plane layer respectively do not coincide.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Ayers, Michael L. Scollard, Heidi D. Williams
  • Publication number: 20120318561
    Abstract: According to one embodiment, a pattern formation method includes: providing a first member; providing a second member; forming a third pattern; and removing a convex portion of a second pattern. The first member is provided on a major surface of a substrate and cured in a state of a template having a first pattern being brought into contact to form the second pattern including a convex portion in a first region on the major surface. The second member is provided in a concave portion adjacent to the convex portion of the second pattern. The third pattern is formed in the second member provided on a second region on the major surface. The removing the convex portion includes removing the convex portion of the second pattern to leave the third pattern and a fourth pattern formed by the second member provided in the concave portion on the major surface.
    Type: Application
    Filed: March 19, 2012
    Publication date: December 20, 2012
    Inventors: Kazuhiro TAKAHATA, Masafumi Asano, Yingkang Zhang, Tomoko Ojima
  • Publication number: 20120319724
    Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.
    Type: Application
    Filed: January 12, 2011
    Publication date: December 20, 2012
    Applicant: STC.UNM
    Inventors: James Plusquellic, Dhruva J. Acharyya, Ryan L. Helinski
  • Publication number: 20120318960
    Abstract: An image sensor includes a ceramic base with a cavity therein, the ceramic base including a sidewall forming a conductive layer embedded therein. A protrusion extends from the sidewall toward the center of the cavity. An infrared filter is mounted on the upper surface of the protrusion with a most upper surface of the infrared filter not higher than the upper surface of the ceramic base; and an image unit is mounted on the lower surface of the protrusion with a most lower surface not lower than the lower surface of the ceramic base.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Applicants: AMERICAN AUDIO COMPONENTS INC., AAC ACOUSTIC TECHNOLOGIES (SHENZHEN) CO., LTD.
    Inventor: Jongsoo Ha
  • Publication number: 20120320532
    Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.
    Type: Application
    Filed: March 27, 2012
    Publication date: December 20, 2012
    Inventor: James Jen-Ho Wang