Abstract: A synthetic gel for crystal growth, which induces only secondary growth from the surface of a silicalite-1 or zeolite beta seed crystal and cannot induce crystal nucleation in the synthetic gel for crystal growth or on the surface of the seed crystal. The synthetic gel contains fumed silica, tetraethylammonium hydroxide (TEAOH), [(NH4)2SiF6], KOH, and H2O, or contains tetraethylorthosilicate (TEOS), tetraethylammonium hydroxide (TEAOH), hydrogen fluoride, and H2O.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height.

Abstract: A method of manufacturing a dual-gate FinFET is provided. The method includes: forming a fin structure on the semiconductor substrate, depositing an oxide layer and planarizing until the top of the fin structure is exposed, depositing a hard mask layer and patterning, preforming a first etch back process to one side of the oxide layer, and then removing the rest of the hard mask layer, preforming a second etch back process to the oxide layers at both sides of the fin structure simultaneously, forming a gate dielectric layer on surface of the fin structure, then depositing gate material on the gate dielectric layer and patterning, removing gate material on top of the fin structure, forming a drive gate and a control gate at two sides of the fin structure respectively; wherein height of the control gate is higher than height of the drive gate.

Abstract: In accordance with one embodiment, a multi-reader can be manufactured so as to be able to read from multiple regions of a storage device contemporaneously during operation. Such a device can be configured, for example, by forming a first wall; forming a second wall; and utilizing the first wall and the second wall to form two adjacent reader stacks.

Abstract: A method of determining the charge of at least one test particle, comprising: applying one of an electric current or a voltage across an aperture connecting two chambers, whereby the chambers are at least partially filled with electrolyte and whereby the at least one test particle is suspended in the electrolyte of at least one of the chambers; measuring the other of the electric current or voltage across the aperture; varying a pressure differential between the two chambers; and determining the charge based on the measurements of the electric current or voltage.

Abstract: A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end.

Abstract: Disclosed is a method for processing GaN based substrate material for manufacturing light-emitting diodes, lasers, and other types of devices. In various embodiments, a GaN substrate is exposed to nitrogen and hydrogen at a high temperature. This process causes the surface of the GaN substrate to anneal and become smooth. Then other processes, such as growing epitaxial layers over the surface of GaN substrate, can be performed over the smooth surface of the GaN substrate.

Abstract: The present invention provides a phase-shift mask comprising a light shading region which is covered by a light shading pattern and a light transmission region which is not covered by the light shading pattern, the light shading pattern comprises a symmetrical part and an asymmetrical part provided outside the symmetrical part, wherein, an optical blocking unit is provided in a part of the light transmission region outside the symmetrical part away from the asymmetrical part, so that intensity of light transmitted through the part of the light transmission region provided with the optical blocking unit is reduced. During an exposure process using the phase-shift mask of the present invention, the obtained exposure intensity is more uniform.

Abstract: The present invention provides an array substrate and method of repairing broken lines therefor, by forming a via on the organic layer corresponding to each intersection of the gate scan lines and the source-drain data lines, and deposing the second passivation layer in the via to form an aperture, with the vias, a U shape long line can be directly laser welded between the apertures at two ends of a broken line position to recover a connection of the broken gate scan line or the source-drain data line as the gate scan line or the source-drain data line on the substrate of the present invention is broken. The method of repairing saves the process of removing the organic layer with laser and effectively reduces the machine laser loss as removing the organic layer to raise the repair efficiency and the repair success rate. Thus, the display quality of the liquid crystal panel product is promoted.

Abstract: A doped mold film is formed with a dopant concentration gradient in the doped mold film that continuously varies in a thickness direction and a portion of the doped mold film is etched in the thickness direction to form a hole so that an electrode can be formed along an inner wall of the hole. The electrode thus formed includes a first outer wall surface, a second outer wall surface, and a third outer wall surface wherein the first outer wall surface is in contact with a sidewall of an insulating pattern formed on a substrate within a through hole formed in the insulating pattern; the second outer wall surface is in contact with a top surface of the insulating pattern and extends in a lateral direction; the third outer wall surface is spaced apart from the first outer wall surface with the second outer wall surface therebetween; and the third outer wall surface extends on the insulating pattern in a direction away from the substrate.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.

Abstract: An apparatus for drying a substrate may include a spin chuck, a drying chamber and a drying fluid line. The spin chuck may be configured to support the substrate. The spin chuck may rotate the substrate. The drying chamber may be configured to receive the spin chuck. The drying chamber may have an inlet, an outlet and a vortex exhaust. A drying fluid may be supplied through the inlet into the drying chamber. The drying fluid may be drained through the outlet. A vortex of the drying fluid may be drained through the vortex exhaust. The drying fluid line may be connected to the inlet.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).

Abstract: A method of preparing semiconductor dies from a semiconductor wafer having a plurality of fabrication regions separated by dicing lines on the top side of the wafer, and an adhesive coating on the back side of the wafer, comprises applying a repellent material to the fabrication regions and dicing lines where the adhesive coating is not intended to be printed; applying the adhesive coating to the back side of the wafer; removing the repellent material; and separating the wafer along the dicing lines into individual dies.

Abstract: The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. The device may include source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film. The device may include interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film. The device may include a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round shape at a bottom of the slit adjacent to the pipe gate.

Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.

Abstract: A fabrication method of a semiconductor piece includes forming a groove that has a first groove portion, and a second groove portion which is a groove portion formed to communicate with a lower part of the first groove portion and extends toward a lower part at a steeper angle than an angle of the first groove portion, has a shape without an angle portion between the first groove portion and the second groove portion, is positioned on the front side, and is formed by dry etching; affixing a retention member including an adhesive layer to the surface in which the groove on the front side is formed; thinning the substrate from the back side of the substrate in a state in which the retention member is affixed; and removing the retention member from the surface after the thinning.

Abstract: The imprint apparatus of the present invention includes a holding unit configured to hold a mold; a particle inspection unit configured to inspect whether or not particle is present on an imprint area, in which the resin pattern is formed, of the substrate; a dispenser configured to apply an uncured resin to the imprint area; a movable unit configured to move the imprint area with respect to the holding unit; and a controller. The movable unit is capable of moving the imprint area to each of an inspection position by means of the inspection unit, an application position by means of the dispenser, and a contacting position by means of the holding unit. Also, the controller causes the inspection unit to perform inspection of the imprint area in association with the movement of the imprint area by means of the movable unit.

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: An object of the present invention is to provide a method which enable a material to be fully embedded into a recess portion with a deposition film left in the recess portion. A method in one embodiment comprises: a first irradiation step of irradiating a deposition film formed on an opening portion of a recess portion in a substrate with a particle beam in a direction at a first angle with respect to a substrate in-plane direction, to remove part of the deposition film in a thickness direction; and a second irradiation step of, after the first irradiation step, irradiating the deposition film with the particle beam in a direction at a second angle which is closer to perpendicular to the substrate in-plane direction than the first angle is, to remove part of the remaining deposition film in the thickness direction.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: A method of depositing a layer includes spraying a source gas and a reactant gas onto a substrate disposed on a susceptor unit using at least one source gas spray nozzle and at least one reactant gas nozzle to form a first source gas region and a first reactant gas region on the substrate, respectively, moving the susceptor unit by a distance corresponding to a width of the source gas spray nozzle or a width of the reactant gas spray nozzle in a first direction, and spraying the source gas and the reactant gas onto the first reactant gas region and the first source gas region using the source gas spray nozzle and the reactant gas nozzle, respectively, to form a first monolayer.

Abstract: An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Abstract: The present invention provides a method for selectively removing silicon carbide from the surface of a substrate in preference to silicon dioxide. The method comprises abrading a surface of substrate with a polishing composition that comprises a particulate abrasive, at least one acidic buffering agent, and an aqueous carrier.

Abstract: An etching method containing, at the time of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal, selecting a substrate in which a surface oxygen content of the first layer is from 0.1 to 10% by mole, and applying an etching liquid containing a hydrofluoric acid compound and an oxidizing agent to the substrate and thereby removing the first layer.

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Abstract: Provided is a method of manufacturing an organic light-emitting device including a graphene layer. The method of manufacturing an organic light-emitting device according to the present invention may include providing a graphene donor unit including a patterned graphene layer, providing a device unit, and attaching the graphene layer of the graphene donor unit to an organic part. The device unit may include a substrate, a lower electrode, and the organic part which are sequentially stacked, and the organic part may include a dopant. The graphene donor unit may include the graphene layer, a release layer, and an elastic stamp layer which are sequentially stacked.

Abstract: A Raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The Raman probe may be coupled to a targeting system of a laser thermal processing system. The Raman probe includes a laser positioned to direct probe radiation through the targeting system to the substrate, a receiver attuned to Raman radiation emitted by the substrate, and a filter that blocks laser radiation reflected by the substrate. The Raman probe may include more than one laser, more than one receiver, and more than one filter. The Raman probe may provide more than one wavelength of incident radiation to probe the substrate at different depths.

Abstract: High performance, high bandgap, lattice-mismatched, photovoltaic cells (10), both transparent and non-transparent to sub-bandgap light, are provided as devices for use alone or in combination with other cells in split spectrum apparatus or other applications.

Abstract: A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the ILOS layer, each pair of spacers having a first filler formed between adjacent spacers, and a second filler formed between each pair of spacers; forming and patterning a first OPL to expose one second filler, spacers on opposite sides of the one second filler, and a portion of the first filler adjacent each of the exposed spacers; removing the one second filler to form a SAV, and SAV etching into the ILOS layer; forming a second OPL over the first OPL and in the SAV to form a SAV plug; removing OPL layers and etching into the ILOS layer down to the dielectric layer; forming a third OPL layer in spaces between the TEOS layer; and removing the SAV plug.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: An image forming apparatus includes image carriers; an exposing unit that forms latent images on the image carriers; a developing unit that develops the latent images with toners of different colors from each other; a first transfer unit that forms a color image by superimposing and transferring the developed images onto a second image carrier; a test pattern forming unit that forms, on the image carriers, test patterns to be transferred onto the second image carrier; and test pattern detection units capable of detecting the test patterns transferred onto the second image carrier in different positions from each other in a main-scanning direction. The test pattern forming unit selectively switches, depending on a width of the test patterns in the main-scanning direction, whether to form each of the test patterns in a position detectable by the corresponding one of the test pattern detection units.

Abstract: Provided is a photo active layer for a solar cell or a light emitting diode and a fabricating method thereof. The photo active layer is formed by alternately stacking silicon quantum dot layers in which a plurality of silicon quantum dots containing conductive type impurities are formed in a medium, which is a silicon compound, and conductive layers, which are polycrystalline silicon layers, containing the same conductive type impurities as those of the silicon quantum dots.

Abstract: A three-dimensional (3D) light-emitting device may include a plurality of 3D light-emitting structures formed apart from one another, each 3D light-emitting structure including: a semiconductor core vertically grown on one surface and doped in a first conductive type; an active layer formed so as to surround a surface of the semiconductor core; and a first semiconductor layer formed so as to surround a surface of the active layer and doped in a second conductive type. The 3D light-emitting device may include: a first porous insulating layer formed between lower corner portions of the 3D light-emitting structures so as to expose upper end portions of the 3D light-emitting structures; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the semiconductor core.

Abstract: A thin-film transistor, method of manufacturing the same, and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the thin-film transistor includes an active layer including a channel region, a source region, and a drain region, wherein the active layer has a top surface. The transistor also includes a gate insulating layer formed over the active layer and a gate metal layer formed over the gate insulating layer and having a bottom surface. The area of the bottom surface of the gate metal layer is less than the area of the top surface of the active layer and the bottom surface of the gate metal layer overlaps the top surface of the active layer.

Abstract: Embodiments of the present disclosure relate generally to a method of passivating and/or removing oxides on a semiconductor surface by using ammonium sulfide, the ammonium sulfide is formed by reacting ammonia and hydrogen sulfide in a semiconductor processing chamber, therefore the ammonium sulfide can be used to clean and remove oxides on a semiconductor surface without the concern of ESH and storage, the ammonium sulfide can also be used to passivate a semiconductor surface by forming a layer of sulfur, and thus preventing the reformation of native oxides, the layer of sulfur can be optionally removed to reduce the thickness of the semiconductor material.

Abstract: A stack is formed over a substrate, which comprises an alternating plurality of first material layers including a first material and second material layers including a second material. A patterned hard mask is formed, which includes multiple laterally spaced apart strips. A trimming material layer is formed over the hard mask layer. At least one cycle of process steps is subsequent performed, which include etching the first material employing the second material and the trimming material layer as an etch mask, trimming the trimming material layer to expose a strip of the hard mask layer, etching the second material and the exposed strip of the hard mask layer employing the trimming material layer as an etch mask, and trimming the trimming material layer to expose an edge of a next strip of the hard mask layer. Stepped surfaces suitable for formation of contact via array can thus be formed.

Abstract: Methods of producing layers of patterned graphene with smooth edges are provided. The methods comprise the steps of fabricating a layer of crystalline graphene on a surface, wherein the layer of crystalline graphene has a crystallographically disordered edge, and decreasing the crystallographic disorder of the edge of the layer of crystalline graphene by heating the layer of crystalline graphene on the surface at an elevated temperature in a catalytic environment comprising carbon-containing molecules.

Abstract: A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, a first current controlling structure, and a first electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The second type semiconductor layer has a first region and a second region, in which the first region has a first threading dislocation density, the second region has a second threading dislocation density, and the first threading dislocation density is greater than the second threading dislocation density. The first current controlling structure is joined with the first type semiconductor layer and has at least one first current-injecting zone therein, in which the vertical projection of the second region on the first current controlling structure at least partially overlaps with the first current-injecting zone. The first electrode is electrically coupled with the first type semiconductor layer.

Abstract: A method for manufacturing a light transmissive optical component, includes a first etching process of forming a depressed portion by applying etching to a silicon region of a plate-shaped member, a thermal oxidation process of forming a silicon oxide film by thermally oxidizing an inner side surface of the depressed portion, and a nitride film formation process of forming a silicon nitride film that covers the silicon oxide film. Accordingly, it is possible to realize a manufacturing method for an optical component which is capable of uniformly forming a silicon oxide film on a semi-transmissive reflecting surface which is largely inclined (or nearly vertical) with respect to a substrate surface, and an optical component produced by this method.

Abstract: Exemplary embodiments of the present invention provide a substrate recycling method and a recycled substrate. The method includes separating a substrate having a first surface from an epitaxial layer, performing a first etching of the first surface using electrochemical etching, and performing, after the first etching, a second etching of the first surface using chemical etching, dry etching, or performing, after the first etching, chemical mechanical polishing of the first surface.

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract: A robot system includes: a robot including a hand configured to hold a thin plate-shaped workpiece and an arm configured to move the hand; and a robot controller configured to control the robot. The robot controller controls the robot to perform a transfer of the workpiece at a predetermined workpiece transfer position in such a way that the hand is moved in a horizontal direction while being moved in a vertical direction after the hand has reached the workpiece transfer position.

Abstract: A method of manufacturing a semiconductor device includes: forming an etching mask layer on a semiconductor substrate having an etching target layer, patterning the etching mask layer to form a plurality of etching mask patterns, and forming a subsidiary layer surrounding the etching mask patterns having a uniform critical dimension and gap to form hard mask patterns including the subsidiary layer and the etching mask patterns.

Abstract: The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high polishing speed. The present invention is a polishing slurry including a slurry containing a manganese oxide particle and a manganate ion for polishing high-hardness materials having a Mohs hardness of 8 or higher. In the present invention, the manganese oxide particle in the slurry is preferably 1.0 mass % or more; the manganese oxide is preferably manganese dioxide; and the manganate ion is preferably permanganate ion. The polishing slurry according to the present invention enables even high-hardness hardly-machinable materials such as silicon carbide and gallium nitride to be polished smoothly at a high speed.