Abstract: In a computing system environment, methods and architecture relate to debugging software programs. The programs, regardless of size, are culled for substantially all memory and register writes (and flow control). An indexing and compression occurs so that upon a later query, and decompression (and display), a user can find and diagnose defects in the software program. To efficiently reconstruct the contents of any memory location or register, backwards tracing of events is comprehensively known for all time, not just select periods. Efficiencies in the indexing function include bunching, replacing actual memory locations with pattern(s) representative of same and dividing an execution history of the software program into manageable sections. Nuances for memory or register effects are also contemplated. Still other embodiments contemplate stand-alone computer program products (on computer-readable media or as a download, or other) or those working in conjunction with other debugging programs.

Abstract: A method, apparatus and program storage device for providing automatic recovery from premature reboot of a system during a concurrent upgrade is disclosed. A concurrent code-load to a plurality of storage controllers of a storage system is initiated. A code-load failure is detected. The stage of the code-load failure is identified. A code-load recovery process based upon the identification of the stage that the code-load failure occurred is initiated.

Abstract: A method, apparatus and program storage device for performing fault tolerant code upgrade on a fault tolerant system by determining when functional code reaches a desired state before resuming an upgrade. A concurrent code-load to a plurality of storage controllers of a storage system is initiated. A role transition is detected. The storage system determines when the storage system returns to a desired state. The code-load is resumed when the storage system returns to the desired state.

Abstract: A solution is proposed for testing a software application. The test includes the execution of a series of test cases, each one involving the application of a predefined test input to the software application. The software application generates a corresponding output in response to this test input. A result of the test case is determined by comparing the actual output provided by the software application with an expected output thereof. The expected output of the test case is determined automatically. For this purpose, multiple auxiliary sources are exploited, such as other software applications different from the one under test. Each auxiliary source receives a corresponding input, derived from the test input, which is intended to cause the auxiliary source to provide the same expected output as the software application. The expected output is then estimated according to the actual outputs provided by the different auxiliary sources.

Abstract: Methods and apparatuses utilize test sequencing logic to bypass tests of a test program that provide statistically low test information.

Abstract: Embodiments of the invention include a novel testing apparatus and method that allows presentation and analysis of DUT test data collected over multiple test runs.

Abstract: Information on program flow and/or data associated with program execution is captured in a processor-based system. This information may be in XML format. Captured data that is not in XML format is serialized into XML. The captured data may be used to diagnose and analyze the system.

Abstract: A method for protecting private data from cache attacks is disclosed. One embodiment includes storing private data in a protected cache line to protect it from cache attacks, receiving a snoop request to the protected cache line, and responding to the snoop request with a miss.

Abstract: An improved error correction apparatus and method for a digital device are provided. An error correction apparatus includes at least one client module outputting an error detection signal, if an error is detected; and a controller for analyzing the error and controlling the client module to correct the error, if an error detection signal is received. An error correction apparatus and method of the present invention is provided with shadow registers or CRC registers for quickly detecting errors of status registers of a client module, whereby an error of the client module can be quickly detected and corrected.

Abstract: Storage stability is managed. It is detected that a disk drive is requesting to be taken offline. The disk drive is begun to be treated as being in a probation state. If within an acceptable period of time the disk drive requests to be put back online, treatment of the disk drive as being in a probation state is stopped, and only any portions of the disk drive data that were the subject of write requests involving the disk drive while the disk drive was being treated as being in a probation state are rebuilt.

Abstract: This invention relates to a diagnostic tool for networks that process messages in stages such as pipelined networks. In a pipelined network comprising tiers of servers, each tier of servers communicates only with adjacent tiers in a communications flow that processes messages in a sequence of tiers. The tool requires a controller located locally with respect to the pipelined network for generating messages to be processed by the pipelined network. Communication paths connect the controller to each tier of the pipelined network. A program executing at the controller detects a failure of the processing of the message by the pipelined network and receives diagnostic information from the tiers after the failure is detected. The diagnoses based on the retrieved information can proceed either manually or automatically, depending on how the information is collected.

Abstract: A method and system for handling errors and exceptions in an ERP environment are disclosed. According to one aspect of the present invention, a condition or event causes a script-engine associated with a particular ERP server to generate an error message. The error message is communicated to a centralized controller-node. The centralized controller-node analyzes the message and determines the best course of action for handling an error or exception related to the error message. Based on the controller node's analysis, the controller node communicates a response message, thereby enabling the process that caused the error to continue without terminating abnormally.

Abstract: A system for processing data captured from rendered documents is described.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A data decoding method judges a signal state where there is a transition from a low level to a high level or from a high level to a low level at the center portion of a bit interval as logical “1” or “0”, and a signal state where a low level continues or a high level continues over the entire bit interval as logical “0” or “1”. The method has the steps of: measuring a first time duration in which the bit series signal transitions from a low level to the next low level, measuring a second time duration in which the bit series signal transitions from a high level to the next high level, and deciding a logical “0” or “1” value for the target bit to be decided based on the combination of the first time duration and the second time duration measured for the target bit.

Abstract: A basic input/output system (BIOS) debugging system and method, which is applicable to a BIOS that has a debugging mechanism hidden by the BIOS in normal operation. The debugging method includes the following steps of (1) determining in a power on self test executed by the BIOS whether at least a preset input mode that is used for a user to enter the debugging mechanism is actuated or not, and proceeding to step (2) if the input mode is actuated, or continuing executing the POST; (2) entering the setting mode of the BIOS and displaying the hidden debugging mechanism; and (3) executing debugging functions provided by the debugging mechanism and/or resetting parameters provided by the debugging mechanism. Accordingly, the present invention allows the user to execute the hidden debugging mechanism after the completion of the BIOS initial setting, thereby, increasing the debugging efficiency.

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract: Provided are a fault model and rule based fault management apparatus and method for a home network. The fault management apparatus includes: a plurality of fault generation unit formed in a multilevel structure and generating fault notification when a fault is generated; a plurality of fault communication unit for transferring fault notification from one of the fault generation unit; a fault agent unit for transferring each fault notification from a plurality of the fault communication unit; and a fault diagnosis and process unit for receiving the fault notification from the fault agent unit, diagnosing a corresponding fault, and processing the corresponding fault using a fault model, a fault decision rule, and a fault process rule.

Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.

Abstract: A debugging apparatus and method for correcting errors in embedded systems are provided. More particularly, a non-stop debugging apparatus and method for correcting errors in embedded systems in a development environment configured of a host and a target are provided. With the non-stop debugging apparatus and method, application programs of the embedded systems can be easily debugged without the user having to frequently execute operation and stoppage of the application programs, in time-sensitive application programs and the application programs on which it takes a user much time to perform. Also, according to the non-stop debugging apparatus and method, commands for the non-stop debugging and information required for other debugging are stored in the host system, thus making it possible to minimize the load of the target system so as to conform to the characteristics of the embedded systems sensitive to resource limitations.

Abstract: A technique for controlling a system is provided in which a control-data table is employed for facilitating operation of the system, and an inject-fault-data table is selectively used during testing of the system. Pursuant to the technique, a security mechanism is provided to restrict the system's utilization of the inject-fault-data table. A security check by the security mechanism is to be satisfied for the system to access the inject-fault-data table. In an enhanced embodiment, the system is tested by substituting an inject-fault-data entry of the inject-fault-data table for a control-data entry of the control-data table as an input to the system. The testing verifies the response of the system to an emulated fault, which results from employing at least one inject-fault-data entry during testing of the system.

Abstract: Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.

Abstract: A method of recovering from an operating system crash or failure in a first memory. Upon detecting the crash or failure, a second memory provided as auxiliary memory to the first memory and being of equal size to the first memory is initialized, the operating system is booted in the second memory, content of the first memory is dumped to a dump storage device, and the first memory is prepared for use as auxiliary memory.

Abstract: A system and method for determining fault isolation in an enterprise computing system is disclosed. A method includes automatically troubleshooting errors in an enterprise computing system that receives at an analyzer engine a status notification from a first component. In response to receiving the status notification, the method automatically selects a first analyzer policy file from a set of analyzer policy files based on the status notification received at the analyzer engine, wherein the analyzer policy file contains troubleshooting logic for determining root causes for errors. The method automatically attempts to communicate with a second component based on the troubleshooting logic within the first analyzer policy file. The method automatically determines a root cause for the status notification based on the troubleshooting logic in the selected analyzer policy file and based on information obtained in connection with the attempt to communicate with the second component.

Abstract: Embodiments of the present invention relate generally to error reporting methods and systems. An error reporting application may be configured to be a stand-alone program, embedded within another application, or added as a plug-in application. The error reporting application may also be configured to provide a mechanism for a user to describe a problem with another application and send the problem description to a configurable, user defined location. The error report from the error reporting application may then be processed by an error processing system at the user-defined location.

Abstract: A common interface and communication methodology are provided for interaction between the components of a storage area network for them to activate “triggers” that cause actions to be taken by the devices to utilize copy service functions to create additional copies of data, and to potentially route load to other resources. The actions can be taken by any of the elements of the storage area network to mitigate the impact of the pending failure. The advantage of this system over current methods is that it can detect both failure and impending failure in any component in the system and use resources in any other component to mitigate the failure. This creates a much more comprehensive recovery strategy and the potential to save more data than in current systems.

Abstract: The memory control device according to the present invention reads data including an error correcting code from a memory and includes: an error correcting unit which detects an error in the data and corrects the detected error in the data, based on the error correcting code, and sends the error detected and error corrected data to the outside; and a selector which selects whether to send the data read from the memory to the error correcting unit or to the outside.

Abstract: If a failure occurs in any of a plurality of data disks, and if a controller receives a read request from a host computer for the RAID group including the failed data disk, the controller performs data recovery using data stored in the other data disks in the RAID group, and transmits the recovered data to the host computer and also writes the recovered data to a spare disk.

Abstract: A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two sets of write data by comparing respective checksums or the write data read back from the storage device by the second controller.

Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

Abstract: A method and data processing system for isolating a faulty component in a computer. A first microcontroller detects a fault in a component of a computer. Responsive to detecting the fault, the first microcontroller sets a first fault record for the component to pending fault, sets a second fault record for the first microcontroller to pending fault, and fails over to a second microcontroller. If the second microcontroller detects the fault in the component of the computer, then the first fault record for the component is set to permanent fault, and the second fault record for the first microcontroller is cleared. If the second microcontroller determines the component of the computer does not have the fault, then the first fault record for the component is cleared, and the second fault record for the first microcontroller is set to permanent fault.

Abstract: Certain exemplary embodiments can comprise a method, which can comprise providing a signal indicative of a set single bit flag. The flag can be set for a scan cycle responsive to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an I/O interface of the PLC system.

Abstract: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and outputs of the primary instance and gates those inputs to the backup instance once a given input has been processed. The outputs of the backup instance are then compared with the outputs of the primary instance to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup instance to take over for the primary instance in a fault situation wherein the primary and backup instances are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment.

Abstract: Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not received. This allows fast/complex ATE Rx memory to be replaced by slower and smaller MISR pattern memory. At the end of a test period, the LFSRs or MISRs generate signatures which are then compared to a set of possible valid signatures for non-deterministic data. A pass/fail result is produced. By masking indeterminate states, fewer valid signatures need to be stored. Masking of the MISRs or LFSRs may be based on the fact that indeterminate states and good data in a serial output data stream tend to occur in predictable patterns, or that good data may follow alignment characters. MISR or LFSR output signatures may also be employed to test individual pattern segments instead of the entire input test pattern.

Abstract: Apparatus and methods are provided for recovering from mismatching configuration data in a clustered environment having a plurality of storage devices coupled to a plurality of storage controllers. If a clustered environment has a first storage device of the plurality of storage devices that has first configuration data that does not match second configuration data of a second storage device of the plurality of storage devices, then the mismatch may be resolved through operation of the clustered environment rather than through operator intervention. Comparison of relevant attributes of the first and second configuration data determines whether a relevant difference between the first and second configuration data is a physical status of at least one of the plurality of storage devices.

Abstract: A method of implementing online maintenance in communication network, includes: recording, in any communication device of the communication network, communication data going through the communication device itself when the communication device has detected online a maintenance request; collecting, by an online maintenance server set in the communication network, online the communication data recorded in all the communication devices, and analyzing the communication data to find out a fault reason of the communication network. In the method, communication devices are triggered via a maintenance request to objectively record communication data, and an online maintenance server is set for analyzing the collected communication data to find out the fault reason. In this way, the communication procedure and maintenance procedure are separately performed, which is convenient for the communication service provider to solve problems.

Abstract: A technique for problem determination in a distributed application is provided. Testing results of the application are first obtained through execution of test cases of a test group in the application. The testing of the application is then adaptively refined when the testing results have one or more failures, to expose problems that caused the one or more failures.

Abstract: An apparatus (20) provides a dynamically-generated audio and/or video error file upon the occurrence of an error condition in a wireless virtual file system (100). According to an exemplary embodiment, the apparatus (20) includes a host interface (22) for connecting to a host device (10) and a network interface (30) for connecting to a wireless network (40). A controller (24) is coupled to the network interface (30) for retrieving a name of a file stored in a storage device (50) connected to the wireless network (40), and is coupled to the host interface (22) for transmitting the name of the file to the host device (10). If no name is retrieved, the controller (24) transmits a signal indicating an error condition.

Abstract: Embodiments of the present invention help improve the process for updating parities accompanied by the writing process. According to one embodiment, a host controller transmits a write command and new data to a hard disk drive (HDD). The HDD reads old data at a region where the new data are to be written. The HDD then XORs the new data and the old data to generate a pseudo-parity. The HDD sets the pseudo-parity in a data frame addressed to both of a horizontal parity disk drive HDD and a diagonal parity disk drive HDD and transmits it. The horizontal parity disk drive HDD and the diagonal parity disk drive HDD update the parities using the pseudo-parity.

Abstract: A communications method useable to safely communicate a message or a signal from a first safety approved entity (210) to a second safety approved entity (230) via a third, non-safety approved entity (220) comprising that each command is sent with the aid of a command message from the first to the second entity, an acknowledge message from the second to the first entity, and a go-ahead message from the first to the second entity.

Abstract: Provided are a data transmission apparatus and method which apply an appropriate coding rate according to significance of bits or bit groups included in uncompressed data and retransmit all or part of the data when a transmission error occurs in the data while the data is being transmitted over a wireless network. The data transmission apparatus includes a mode termination unit which determines a retransmission mode for an initial transmission packet which has a transmission error; a packet generation unit which generates a retransmission packet, which includes at least part of the initial transmission packet, according to the determined retransmission mode; and a communication unit which transmits the retransmission packet through a communication channel.

Abstract: Methods and apparatus for data analysis according to various aspects of the present invention identify statistical outliers in data, such as test data for components. The outliers may be identified and categorized according to the distribution of the data. In addition, outliers may be identified according to multiple parameters, such as spatial relationships, variations in the test data, and correlations to other test data.

Abstract: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32 and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLA65 and outputs defect information to a redundant signal line RA. The redundant memory macro 2A includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Abstract: A storage controller (104) for a storage system (100) in which there are multiple storage devices (109) and a method for recording diagnostic information are provided. The storage controller (104) includes a storage device manager (203) which has means for allocating a storage device (109) in the storage system (100) for storing diagnostic data. The storage controller (104) also includes means for generating diagnostic data regarding the operation of the storage controller (104). Two buffers (207, 208) are used for alternately recording and writing batches of diagnostic data to the allocated storage device (109). The allocated storage device may be a storage device which is normally reserved for disaster recovery in the storage system (100).

Abstract: A data processing apparatus which saves data in a volatile memory into a nonvolatile memory when power is off, the data processing apparatus including: a detecting circuit for outputting: a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage; and a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure detecting signal after the detecting circuit has output the momentary interruption detecting signal.

Abstract: Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of min-sum algorithm (MSA) and have almost the same performance under 5 bits fix-point realization as the float-point sum-product algorithm (SPA).

Abstract: Example embodiments are directed to a parallel bit test device and method using error correcting code. The parallel bit test device may include an error detecting and correcting unit configured to count the number of fail bits in an m-bit data signal, for example, by comparing bits of the m-bit data signal with corresponding bits of expected data, where m is a positive integer, and to output correction signals. The error detecting and correcting unit may be further configured to perform at least one logic operation on a correction control signal and comparison signals. The correction control signal may be generated in response to a test mode register set (TMRS) signal set and input by a user such that the logic level of the correction control signal may vary according to the counted number of fail bits. Each comparison signal may include information about a fail bit and the address of the fail bit.

Abstract: A computer program product and computer system for error monitoring partitions in a computer system. Provided to each partition is a partition status indicator (PSI) denoting a RUNNING or FAIL status of the partition, and an error log area (ELA) for storing partition error entries. The ELA includes a partition identifier, an entry status indicator (ESI) indicating READ/UNREAD status for the error entry, and an error identifier. An error procedure performed for each first partition whose partition status indicator indicates the FAIL status includes: copying each error entry in the ELA of the first partition whose ESI indicates the UNREAD status into the ELA of a second (running) partition; setting the ESI to the READ status for each copied error entry in the ELA of the first partition; and having the ESI set to the UNREAD status for each copied error entry in the ELA of the second partition.

Abstract: A method for testing a semiconductor device having a detection unit to detect a faulty point by a BIST, a redundant circuit and a replacing unit includes a first step to detect the faulty point by the detection unit under a first test condition and replace the faulty point with the redundant circuit by the replacing unit, a second step to detect the faulty point by the detection unit again under the first test condition for the semiconductor device keeping state after completing the first step, a third step to detect the faulty point by the detection unit under a second test condition for the semiconductor device not having the faulty point detected in the second step where the semiconductor device keeping the state after completing the first step and a fourth step to evaluate the defectiveness of the semiconductor device according to the third step result.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.