Abstract: There is provided a probability density function separating apparatus that separates a predetermined component in a given probability density function. The probability density function separating apparatus includes a domain transforming section that is supplied with the probability density function and transforms the probability density function into a spectrum in a predetermined variable axis, and a deterministic component computing section that multiplies a multiplier coefficient according to a type of distribution of a deterministic component included in the given probability density function by a value, in the variable axis, of a first null of the spectrum and computes a peak to peak value of the probability density function with the deterministic component.

Abstract: A headend transmitter that transmits 1024 QAM including a 256 QAM modulator which has been modified to have more aggressive forward error correction processing. The 256 QAM modulator outputs 256 QAM points to a summer. Another data modulator receives additional data to be transmitted in a separate, substantially less complex constellation. This modulator processes the additional data to do forward error correction thereon and then maps the encoded data into a less complex constellation such as QPSK, 16 QAM etc. The additional data constellation points are then amplified in a variable gain amplifier and fed to a summer where each additional data point is added by vector summation to one 256 QAM point. The output 1024 QAM point is filtered and shifted to the desired transmission frequency. Legacy cable modem receivers can still receive the 256 QAM point since the addition of the new data just appears to be noise which they can overcome using the parity bits encoded in the transmitted symbols.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis.

Abstract: A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.

Abstract: A wireless communication apparatus having a retransmission control unit configured to refer to identification information added to received retransmit data when a second retransmit request is performed after the first transmit request is performed, and not to use the received retransmit data for forming data when the received retransmit data corresponds to the first retransmit request based on the identification information, and to use the received retransmit data for forming data when the received retransmit data corresponds to the second retransmit request based on the identification information.

Abstract: An OFDM receiving apparatus has N sets of reception and demodulation units which input one segment broadcasting signals of ground digital broadcasting received with N sets of antennas and demodulate the signals; a buffer unit which includes N sets of buffers which hold temporarily N sets of demodulated data, which are demodulated in the N sets of reception and demodulation units, respectively, and reads the N sets of demodulated data, which are written in the N sets of buffers, in time division; and an error correction unit which inputs N sets of demodulated data read from the buffer unit in time division, performs error correction one by one, and in the process of the error correction, multiplexes the N sets of demodulated data, which have been error-corrected, in a period not used by one segment reception to output the data as one TS multiplex data.

Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Abstract: A semiconductor memory device having a mount test circuit and a mount test method thereof are provided. The test circuit for use in a semiconductor memory device including a plurality of memory blocks may include a comparison unit for comparing test data of at least two memory blocks selected from the plurality of memory blocks, deciding whether or not the test data of the selected memory blocks are identical, and outputting a pass signal or fail signal as a flag signal; and an output selection unit for selecting any one of the selected memory blocks as an output memory block, and changing the output memory block whenever the fail signal is generated from the comparison unit, thus forming it as a data output path, which may lessen error occurrence.

Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

Abstract: A memory 2 is formed having an array of memory cells 4 arranged in rows 14. An address decoder 6 generates a word line signal WL in response to an input address to select one of the rows of memory cells for access. The word line signal also accesses address identifying data associated with the row of memory cells being accessed. This address identifying data is compared with the input address by fault detection circuitry 10. If a mismatch is detected, then this indicates a fault within the address decoder 6.

Abstract: A digital VSB transmission system and enhanced data multiplexing method are disclosed. When ½ enhanced data coded at a rate of ½ and ¼ enhanced data at a rate of ¼ are transmitted, timing jitter in MPEG of VSB receiver can be reduced and the size of input buffer in MPEG decoder of the VSB receiver can be reduced by multiplexing the ½ enhanced data packet and the ¼ data packet at predetermined intervals. Multiplexing the ½ enhanced data packet and the ¼ data packet by grouping increases the reception performance of the ¼ enhanced data. Multiplexing the ½ enhanced data packet and the ¼ data packet alternatively reduces the MPEG timing jitter in the VSB receiver and increases the reception performance of the ¼ enhanced data.

Abstract: An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

Abstract: Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.

Abstract: A method, system and diagnostic tool for diagnosing a problem in CSPF and non-CSPF MPLS networks, including problems with LDP tunnels. This includes one or more of the following: hopping from network element to network element; determining whether an LSP between elements is operational; determining whether the hop was strict or loose; evaluating whether there is an existing path between the elements; finding and remembering an IGP link between the elements; recognizing whether the LSP is an FRR LSP; diagnosing a cause of the LSP between the elements being down; and altering a display of a topology map of the network to indicate the cause of the problem.

Abstract: An information communication terminal performs communications with another information communication terminal over a radio communication network system. In the information communication terminal, a receiving unit receives an externally transmitted frame. In a state where error correction is to be performed, a correction processing unit outputs data after performing error correction according to correction information in the frame on data in the frame received by the receiving unit. In a state where the error correction is not to be performed, the correction processing unit outputs the data without performing the error correction on the data in the frame received by the receiving unit. A determining unit determines whether the error correction is to be performed by the correction processing unit or not.

Abstract: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

Abstract: An encoder employs a trellis coded quantization (TCQ) unit and a compression unit. The TCQ uses a set of polynomials that have been selected to maximize granular gain. The TCQ unit operates on a block of samples from a source. The compression unit compresses bit planes of the TCQ output, using parity check matrices of corresponding LDPC codes, to obtain corresponding syndromes. The parity check matrices are selected so their compression performance approaches close to the limit for Slepian-Wolf coding. A decoder employs a decoding unit and an estimation unit. The decoding unit decodes the syndromes using side information to produce an estimate for the TCQ output. The side information is correlated with the source. The estimation unit estimates the block of source samples using the estimated TCQ output and the side information. Trellis coded vector quantization may be used as an alternative to TCQ.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: An apparatus and method of diagnosing whether a program executed in a computer system is malware and repairing the computer system infected by malware. The apparatus includes a receiving unit which receives a first behavior vector for the malware from a malware control server; a determination unit which determines whether a diagnostic target program corresponds to malware based on the received first behavior vector and a second behavior vector for the diagnostic target program; and a repair unit which repairs the computer system based on a result of the determination. A behavior of a computer program executed in the computer system may be modeled in real time.

Abstract: There is provided an error factor measurement device for measuring an error factor in a switch branch signal source including a signal source and a switch, and the error factor measurement device includes a reference error factor component recording unit which records respective components E12a, E21a of a frequency tracking error factor when a predetermined output terminal is connected to a signal source, a derived error factor product recording unit which records an error factor product E12b×E21b which is a product of respective components of a frequency tracking error factor when respective multiple output terminals other than predetermined output terminal are connected to the signal source, an error factor ratio deriving unit which derives an error factor ratio E21a/E12a, and a frequency tracking error factor deriving unit which derives E12b, E21b based on the error factor product and the error factor ratio, where E21a/E12a=E21b/E12b holds.

Abstract: A method of encoding data operates on an ordered set of input symbols and includes generating redundant symbols from the input symbols, and includes generating output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols. The redundant symbols are generated from an ordered set of input symbols in a deterministic process such that a first set of static symbols calculated using a first input symbol has a low common membership with a second set of static symbols calculated using a second input symbol distinct from the first input symbol.

Abstract: An apparatus, system, and method are disclosed for responsive acquisition of remote debug data. The apparatus for responsive acquisition of remote debug data is provided with a plurality of modules configured to detect an error on a local device, trigger a remote device to generate a remote debug data set in response to the error, and generate a local debug data set in response to the error. These modules in the described embodiments include a detection module, a trigger module, and a collection module.

Abstract: A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.

Abstract: A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements may be provided in antenna output channels, or with suitable code construction delay may be omitted. n signals represent n symbols of a codeword are transmitted with n different transmit antennas. At the receiver MLSE or other decoding is used to decode the noisy received sequence. The parallel transmission and channel coding enables an increase the data rate over previous techniques, and recovery even under fading conditions. The channel coding may be concatenated with error correction codes under appropriate conditions.

Abstract: Apparatus and methods allow users of software testing applications to obtain auto-generated reports. During use, one or more software test cases of a feature of a software target are identified for execution. A template, common to the software cases, autogenerate a first report in a first computing language, e.g., XML, based on test results obtained from the execution. A transformation into one or more second reports in a second computing language, e.g., HTML, occurs so that users can visually understand the report. Preferred aspects include utilizing an existing Java-based JUnit testing framework and an API of Apache Ant. Retrofitting existing software testing applications contemplates inserting executable code, in the form of a template, to obtain auto-generated reports. Executable code is available as a computer program product in the form of a download or on a computer-readable medium. Overall architecture in a virtual machine is another noteworthy aspect.

Abstract: During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.

Abstract: Disclosed are redundant data path(s) for transmission of graphical data between components in a graphical display system. The redundant data path(s) are used to transmit graphical data by at least two independent means, so that if a failure in one data path occurs, a data transmitted via a separate data path can be used for display. The system is particularly advantageous for multiple-serial-module configurations. The redundant data path(s) minimize disruption of data display and make repair and maintenance of the display system more efficient. The invention includes apparatus for graphical display systems, and also includes methods of data transmission for graphical display systems, and methods of maintenance of graphical display systems.

Abstract: In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to software functional testing and provide a method, system and computer program product for automated software functional testing via multi-channel remote computing. In one embodiment of the invention, an automated software functional testing data processing system can be provided. The system can include a multi-user operating platform supporting multiple different user sessions configured for communicative coupling to corresponding remote desktops, and a test driver disposed in at least one of the remote desktops. In particular, the test driver can include program code enabled to forward test inputs to an application under test (AUT) executing in one of the user sessions, and to log received test outputs resulting from the test inputs.

Abstract: A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value.

Abstract: LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at least one portion of the variable/bit node processing functionality is actually integrated into the check node processing functionality (e.g., distributed variable/bit node embodiment). In even other embodiments, some check node processing functionality is moved and integrated into the variable/bit node processing functionality, and some variable/bit node processing functionality is also moved and integrated into the check node processing functionality (e.g., combined distributed embodiment).

Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Abstract: Machine-readable media, methods, apparatus and system for flash memory reclaim are described. In some embodiment, a system may comprise a flash memory having a plurality of flash memory blocks, and a managing logic to manage a file operation on the flash memory. The managing logic may, during a foreground reclaim of the flash memory which is triggered by the file operation, select a foreground reclaim block from the plurality of flash memory blocks; search the foreground reclaim block for valid data; and copy the valid data from the foreground reclaim block to a flash memory block of the plurality of flash memory blocks, if the valid data is found. The managing logic may further erase the foreground reclaim block during a next reclaim of the flash memory.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: In a system for parity encoding data using a low density parity check (LDPC) code, a rate-compatible, irregular LDPC code is generated by extending a base code using a constrained edge growth operation and a parity splitting operation. The base code is a “daughter” code having an encoding rate higher than a designated rate of the LDPC code. The daughter code is progressively extended to lower and lower rates such that each extension code (including the target LDPC code) is compatible with the previously obtained codes. The extension operation may involve introducing a set of new code symbols to the daughter code, by splitting check nodes of a base graph associated with the daughter code, and through constrained edge growth of the base graph. The LDPC code is used to parity encode a data message as a means for forward error correction across a communication channel.

Abstract: Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates such failed component. Further, after invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting itself.

Abstract: The present invention relates to a method for providing an equal error protection to data packets in a burst transmission system. The data packets are grouped based upon respective priority levels and error protection is provided to each group of data packets based upon the respective priority level. The error protection codes for each group of data packets depending on the respective priority level is created using data of data packets of the group which are contained in the data section (20) of two or more bursts (10) forming a first set of bursts (50, 50.B, 50.E, 55) and the created error protection codes are transmitted in the error protection section (30) of one or more bursts (10) forming a second set of bursts (60, 60.B, 60.E, 65). The invention further relates to a burst transmission system for performing said method.

Abstract: During operation of a transmitter a circular buffer is created where only column tops of the circular buffer are defined as a starting position for a redundancy version. Where the circular buffer is in sequence format, all possible redundancy versions are at positions ?Kstream/32?(12×i+?), i=0, 1, . . . , 7 where ? indicates the column index of the starting position of the first RV (RV0).

Abstract: In a decoder having a predetermined decoder structure for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes is provided. An associated method is provided. The method comprises the steps of: providing a memory for the decoding with the memory size proportional to the number of circularly shifted-identity matrices I (t); and providing a number M for both row update unit numbers and column-update unit numbers. Whereby an improved architecture having an improved logic and the memory is provided such that an improved throughput, power consumption, and memory area are achieved.

Abstract: A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host.

Abstract: Various example embodiments are disclosed relating wireless networks and relating to context transfers and multi-band operation in wireless networks. In an example embodiment, a multi-band scheduler may be provided for use in a wireless node. The multi-band scheduler may be configured to: receive one or more data units of a flow; assign each received data unit of the flow to a first frequency band of a plurality of frequency bands; determine a band transfer condition for the flow; and perform a context transfer from the first frequency band to a second frequency band for the flow based on the determined band transfer condition.

Abstract: A method to perform launch-on-shift scanning for integrated circuits having multiple clock domains is presented. An integrated circuit includes both capture clock domains and non-capture clock domains. The portions of the test vectors for non-capture clock domains are shifted into the scan chains of the non-capture clock domains and allowed to settle prior to the last shift launch cycle and the capture cycle of the capture clock domains. Thus, the ambiguity of the timing between the non-capture domains and the capture domains caused by asynchronous clock signals is eliminated.

Abstract: A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.

Abstract: Systems and methods for testing uniform resource identifier protocols, comprising a fuzzer that can accept an input, and produce a fuzzed uniform resource identifier (URI), and a debugger that monitors effects of invoking the fuzzed uniform resource identifier. The input can comprise a directory containing a plurality of valid uniform resource identifier bodies, which can be fuzzed and invoked. The debugger can monitor a target application as well as other applications and/or processes affected by the uniform resource identifier as invoked.

Abstract: Cyclic redundancy check processing can be applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already known before the unknown data portion becomes available. A syndrome contribution that the already-known data portion contributes to a syndrome for the set of input data can be determined before the unknown data portion becomes available. When the unknown data portion becomes available, the syndrome for the set of input data can be determined based on the unknown data portion and the syndrome contribution.

Abstract: A data-transmission device dividing video data into packets and transmitting the packet to a data-reception device requesting the video data includes a unit generating transmission packets based on the video data, a unit setting importance for each of the generated packets, a unit storing information about the set importance in a first storage unit, a communication unit transmitting the generated packet to the data-reception device and receiving a packet-retransmission request from the data-reception device, a unit saving the transmitted packet in a second storage unit, a unit calculating the packet-loss rate based on the received packet-retransmission request, a unit determining a packet retransmitted to the data-reception device based on the calculated packet-loss rate and the packet importance, and a retransmission unit reading the determined retransmission packet from the second storage unit and transmitting the retransmission packet to the data-reception device.

Abstract: A testing device for testing a motherboard is provided to include a server, a client terminal computer, a debug card and a receiving device. The server is connected to the client terminal computer, for inquiring test results. The debug card is attached to the motherboard, for getting test data. The receiving device connecting with the debug card transmits the test data to the server via a network. A testing method for testing a motherboard is provided to include the following steps: a debug card getting the test data from the motherboard; sending the test data to a receiving device, the receiving device transmitting the test data to a server, the server collating and analyzing the test data; and a client terminal computer inquiring test results via the server.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: In a transmitter (2001), when generating a transmission frame having no limitation to a window size, a batch-transmission-end flag generating circuit (2004) and a sequence number generating circuit (2005) respectively adds a batch-transmission-end flag and a sequence number to the transmission frame. In a receiver, if an omission of a sequence number is detected as a result of analyzing sequence numbers of frames having received from the transmitter (2001), retransmission request is made when receiving a frame whose batch-transmission-end flag indicates the end. In this way, retransmission is possible in data transmission using UI frames, and the communication efficiency can be improved.