Abstract: Techniques for transmitting data with hybrid automatic retransmission (HARQ) and interference mitigation are described. In one design, a transmitter processes a packet of data in accordance with a rate and sends at least one transmission of the packet to a receiver with HARQ. In one design, the transmitter sends a trigger message to the receiver to trigger the receiver to send a request to reduce interference to interfering station(s). The transmitter may send a first transmission of the packet (i) after the trigger message, e.g., in consecutive frames of a single HARQ interlace, or (ii) along with the trigger message in the same frame. The number of transmissions to send for the packet may be dependent on whether the interfering station(s) reduce interference to the receiver. The packet transmission may terminate early if interference mitigation is successful or may terminate late if interference mitigation is unsuccessful.

Abstract: An acknowledgement method in a wireless communication system. Initially, a reverse supplemental channel (R-SCH) frame is received at a base station. The base station then transmits an acknowledgement (ACK) signal if quality of the received R-SCH frame is indicated as being good. A negative acknowledgement (NAK) signal is transmitted only if the received data frame is indicated as being bad but has enough energy such that, if combined with energy from retransmission of the data frame, it would be sufficient to permit correct decoding of the data frame. If the best base station is known, the acknowledgement method may reverse the transmission of the acknowledgement signals for the best base station so that only NAK signal is sent. A positive acknowledgement is assumed in the absence of an acknowledgement. This is done to minimize the transmit power requirements.

Abstract: A receiving system and data processing method therein are disclosed, by which mobile service data is received and processed.

Abstract: Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to identify elements of the circuit which are related to a fault, a circuit pruner to separate the related elements from other elements of the circuit and correlate the related elements to a physical layout of the elements, and a probe tool to locate one or more of the related elements which cause or contribute to the fault. Alternative embodiments may comprise computer programs for simulating operation of a circuit to determine related elements of a fault, correlating the related elements to a physical layout or arrangement of the elements in the circuit, and testing the related elements via the physical layout to determine which elements contribute to the fault.

Abstract: Administering a system dump on a redundant node controller including detecting a communications failure between a system controller and the redundant node controller; generating a unique identifier for the communications failure; instructing a primary node controller to provoke a system dump on the redundant node controller; provoking the system dump on the redundant node controller including suspending a processor of the redundant node controller and storing during the suspension of the processor the unique identifier for the communications failure and an instruction to execute the system dump on the redundant node controller; releasing the processor of the redundant node controller from suspension; in response to releasing the processor from suspension, identifying the unique identifier for the communications failure and the instruction to execute the system dump; and executing the system dump including associating the system dump with the unique identifier.

Abstract: A frame format used to send a command in which high-reliability transmission is demanded includes an SFD area, an inverted header area, a normal data area, a normal check area, an inverted header area, an inverted data area, and an inverted check area. Command data and data obtained by inverting the command data are stored in the normal and inverted data areas, respectively. Similarly, pieces of response data (normal/inverted) are stored in each data area. Check codes used to check the header area and the data area is stored in the normal and inverted check areas, respectively. A receiving device performs a check by the normal and inverted check codes, compares the normal header area with the inverted header area, and compares the normal data area with the inverted data area. The receiving device normally performs reception when all the comparison results are correct.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.

Abstract: An apparatus, system, and method are disclosed to failover to a standby server when a primary server is under broadcast storm or denial-of-service (“DoS”) attack. A primary attack sensing module is included to monitor a rate of incoming data from a computer network to a primary server and to determine if the rate of incoming data is above a primary data rate threshold. A standby contact module is included to request a standby data rate status from a standby server in response to the primary attack module determining that the rate of incoming data to the primary server is above the primary data rate threshold. The standby server is connected to the primary server over a private network. The standby data rate status includes a determination by the standby server of whether a rate of data received by the standby server is above a standby data rate threshold. A standby receiver module is included to receive a standby data rate status from the standby server over the private network.

Abstract: An approach is provided for acknowledgement signaling. A determination is made whether an error control mechanism is enabled for transmission of a data frame. The data frame is fragmented into a plurality of coding blocks. A frame check sequence is appended to one or more sequences of the coding blocks, wherein each of the sequences associated with the frame check sequence is to be acknowledged separately.

Abstract: A bit-level turbo code encoder is provided. The bit-level turbo code encoder is configured to receive a first input data sequence and generate a first output data sequence. The bit-level turbo code encoder includes a first non-binary convolutional code encoder, a bit-level interleaver, and a second non-binary convolutional code encoder. The first non-binary convolutional code encoder is configured to process the first input data sequence and generate a second output data sequence. The bit-level interleaver is configured to receive the first input data sequence as a first sequence and interleave the first sequence at bit level to generate a fourth sequence. The second non-binary convolutional code encoder is coupled with the bit-level interleaver and configured to receive the fourth sequence and process the fourth sequence to generate a third output data sequence.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

Abstract: A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system. To enable blocks of data to be properly checked when read from memory, the storage subsystem stores ECC metadata indicating the particular error correction setting used to store particular blocks of data. The storage subsystem may be in the form of a solid-state non-volatile memory card or drive that attaches to the host system.

Abstract: In a decoder having an improved LLR (log-likelihood-ratio) update method is provided. The method comprising the steps of: providing a parity check matrix; and using merely a set of parameters on a row of the parity check matrix instead of data of the whole non-zero elements of the parity check matrix free from at least one shifting action after each row updating; thereby saving memory space and process time.

Abstract: Aspects of a method and system for a transmitting antenna selection failure recover mode are presented. Aspects of the system may include a transmitting mobile terminal that enables selection of a sequence of protocol data units (PDU), for example a sequence of sounding frames, which may be transmitted during an antenna selection procedure. During transmission of the selected PDU sequence, the transmitting mobile terminal may receive an antenna selection failure indication frame. The transmitting mobile terminal may enable retransmission of at least one previously transmitted PDU in the PDU sequence based on the failure indication. Transmission of subsequent PDUs in the PDU sequence may resume after the retransmission. Alternatively, upon receipt of the failure indication frame the transmitting mobile terminal may restart the selected frame sequence from the beginning, or may select a subsequent PDU frame sequence.

Abstract: Systems and methods of providing test result management are disclosed herein. A first configuring command to trace a test event data stream can be received. The test event data stream comprises test messages produced from execution of a test application. A second configuring command to trace a debug event data stream can be received. The debug event data stream includes debugging messages produced from execution of a tested application. A third configuring command to trace an execution event data stream can be received. The execution event data stream includes function invocation messages produced from execution of the tested application. The test event data stream, the debug event data stream, and the execution event data stream can be received and interleafed into a collated data stream log.

Abstract: A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.

Abstract: A method for improving the performance for a streaming service by link-adaptation and power-control in a wireless packet network such as an Enhanced General Packet Radio Services (EGPRS) cellular network is described. In particular, the effects of a combined link adaptation and power control scheme (referred to as an error-based scheme) for achieving a target error rate, which is non-zero but low enough so that limited retransmission and error concealment techniques are effective, is presented.

Abstract: A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

Abstract: A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises error correction logic integrated in the memory hub device and coupled to the link interface. The error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

Abstract: Systems, methods, devices, and processors are described for a wireless receiver. The receiver may be configured to receive signals transmitted according to various mobile digital television standards. The receiver may include a number of hardware engines. The hardware engines may be individually controlled in a number of aspects. Power to particular hardware engines may be controlled, and the speed of the different hardware engines may vary. The receiver may include a novel multi-function decoder engine. The receiver may be configured to dynamically avoid problems related to harmonics, and may include a novel tap configuration with taps at different locations in the data flow.

Abstract: In digital broadcast receiver (100), when a bit error rate (BER) is larger than a threshold in BER determining part (109), power is supplied to tuner (103) and tuner (104) for diversity reception. When the BER is smaller than the threshold, power supply to one of tuner (103) and tuner (104) is stopped for single reception. This structure allows power supply to one of the tuners to be stopped in excellent reception environments, thus reducing power consumption.

Abstract: Memory objects associated with a portion of a cache (e.g., data blocks of a media file) are assigned a value based on their importance to an application that is consuming memory objects. The values are used to assign the data blocks to purge groups. The purge groups are a labeling mechanism for determining a purge order. A memory object associated with a first data block assigned to a first purge group may be purged before a memory object associated with a second data block assigned to a second purge group. As new data blocks are received by the application (e.g., from disk or a network connection), the blocks are assigned a value and added to a purge group. In some cases, the data blocks arrive out of order (e.g., order of consumption). Memory objects can be reassigned to a different purge group when new data blocks are added or reclaimed.

Abstract: An apparatus and method for transmitting/receiving a Hybrid Automatic Repeat reQuest (HARQ) Acknowledge/Negative acknowledge (ACK/NACK) signal in a mobile communication system. The present invention distributes a CDM segment, to which an ACK/NACK signal is mapped, in the frequency domain of an OFDM symbol, and repeatedly transmits the CDM segment, thereby providing diversity gain in the time-frequency domain. Further, the present invention provides a mapping rule for distributing transmit power between OFDM symbols to which the ACK/NACK signal is mapped and transmitted, thereby preventing the case where a particular OFDM symbol is power-overloaded, and thus contributing to improvement of the entire system performance.

Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.

Abstract: A system for problem resolution in network and systems management includes a database of trouble ticket data including information fields for checked components and affected components, an automated model builder system that processes the trouble ticket data to construct a causality model to represent causality information between system components identified in the checked component and affected component fields of the trouble ticket data, and an automated problem analysis system that receives information indicative of a problem event and determines a cause of the problem event using the causality model.

Abstract: A method and apparatus to determine a binary signal of a memory cell capable of decreasing an error rate of binary signal determination that occur due to neighboring cells and noise, the apparatus including: a data collection unit to collect target data stored in a target cell in a memory and binary neighboring data of data stored in at least one neighboring cell that neighbors the target cell; a data correction unit to correct the target data collected from the target cell by using the target data and the binary neighboring data collected by the data collection unit and a parameter; and a binary signal determination unit to determine a binary signal of a corrected signal output from the data correction unit.

Abstract: In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.

Abstract: A method of handling and storing data in a computer by establishing a plurality of zones or sessions with different levels of write protection, writing attempted changes to data stored in a protected zone to a temporary zone, creating representative maps of some or all of the zones or sessions to track such attempted changes, reading the changes from the temporary zone such that it seems as though the changes were successful, and erasing the temporary zone when the computer is restarted, thereby allowing for “restoring” the data, or, more generally, the computer's configuration, to a state prior to the attempted change. One of the zones may contain working files which are relatively frequently changed, and such changes are treated, e.g., saved, in a substantially conventional manner and not affected by restarting the computer. Access to specific non-temporary zones may be restricted.

Abstract: An apparatus and method measures the skew between signals on data and clock channels using a bit pattern matching technique for any given protocol in Serial data communication. In one embodiment, the method of finding the pattern comprises of importing the waveform data from the oscilloscope and converting the waveform into bit patterns, finding the pattern index on the converted bit stream using a pattern based on the TMDS channel combination, and then measuring the skew.

Abstract: An apparatus and method for receiving data when an HS-SCCH is not used in a mobile communication system are provided. In the apparatus and method, retransmission data is received, parameters including information about initial transmission data are acquired from the retransmission data, the initial transmission data is retrieved from a second-rate dematching input buffer based on the information about the initial transmission data, second-rate dematching is performed on the initial transmission data and the retransmission data, and first output data is generated by soft-combining the second rate-dematched initial transmission data with the second rate-dematched retransmission data. Accordingly, memory usage can be reduced.

Abstract: Recovery of a redundant node controller in a computer system including determining a loss of a heartbeat for a predefined period of time between a system controller and the redundant node controller; in response to determining the loss of the heartbeat for the predefined period of time, checking network connectivity between the system controller and the redundant node controller; if there is network connectivity between the system controller and the redundant node controller, determining whether an application on the redundant node controller is running; and if an application on the redundant node controller is running, resetting the redundant node controller through a primary node controller.

Abstract: A digital broadcast transmitter/receiver, and a signal processing method thereof, includes a randomizer randomizing a dual transport stream which includes a normal data packet and a robust data packet and into which stuff bytes are inserted, a stuff-byte exchanger replacing the stuff bytes of the randomized data with known data, a first RS encoder performing RS-encoding of data output from the stuff-byte exchanger, a packet formatter performing an interleaving of the robust packet of the data output from the first RS encoder and reformatting the packet, an interleaver interleaving data output from the packet formatter, a trellis encoder performing a trellis encoding of interleaved data, a second RS encoder changing a parity by performing an RS encoding of the robust data of the trellis-encoded data, and a modulator modulating data output from the trellis encoder and RF up-converting the modulated data.

Abstract: A digital broadcasting transmission and/or reception system having an improved reception performance and a signal-processing method thereof. A digital broadcasting transmitter comprises a TRS encoder for to TRS-encode a MPEG-2 transmission stream having null data for inserting a Known data and a TRS parity at predetermined positions, randomizer to input and randomize data stream from the TRS encoder, a null packet exchanger to replace the null data for inserting the Known data to the known data, and an encoder for encoding a data streams to which the Known data is inserted. Accordingly, the present invention detects the known data from a signal received from a reception side and uses the detected known data for synchronization and equalization and further uses the TRS parity for correcting error of the received signal, so that the digital broadcasting reception performance can be improved at poor multipath channels.

Abstract: A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.

Abstract: For use in a communication system, an apparatus that, in one embodiment, includes a band flipping module configured to renumber physical resource blocks for a retransmission of data from physical resource blocks associated with a previous transmission of the data. The apparatus also includes a transceiver configured to retransmit the data in accordance with the renumbered physical resource blocks.

Abstract: A method of virtually removing field replaceable units (FRUs) from a computer system during concurrent maintenance operations. Firmware within a flexible service processor (FSP) assigns unique resource identification (RID) numbers to each FRU in the computer system. The firmware collects vital product data (VPD) for each FRU and generates a duplicate test shared library, which is stored in a memory directory corresponding to the FSP. When the firmware receives input from a graphical user interface (GUI) that includes at least a first FRU selected for virtual removal from the computer system, the firmware adds the RID number of the selected FRU to the memory directory and recollects VPD. The FSP subsequently ignores any FRUs corresponding to RID numbers stored in the memory directory during operation of the computer system.

Abstract: A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.

Abstract: A transceiver with a plurality of components coupled to one another to form a transmit path and a receive path for multi-tone modulation of user data across a communication medium. The transceiver includes a framer and a deframer. The framer is configured to momentarily suspend framing of user data before processing bits associated with tones targeted for reference data transport and injects the pre-agreed reference pattern therein, after which framing of user data resumes. The deframer is configured to momentarily suspend deframing of received user data bits before processing bits associated with tones targeted for transport of pre-agreed reference data and extracts the received reference bits thereof for comparison with the corresponding pre-agreed reference bits to determine errors therein, after which deframing of user data resumes.

Abstract: High speed differential copy can be implemented in the fail-back after disaster recovery when the data of the primary site is protected safely. When a restore command is issued, the common snapshots of the snapshots of the primary site and the secondary site are extracted as the base snapshot by comparing the log tables of the primary site and secondary site. The volume of the primary site is rolled back with the extracted snapshots. The latest snapshot of the volume of the secondary site is transmitted to the primary site and it is applied to the volume of the primary site to synchronize the volumes of the primary site and the secondary site.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a under test (DUT) is coupled to both the gold processor and the TAP. Test signals are simultaneously provided to both the gold processor and the DUT such that the gold processor and the DUT operate in synchronous functional lockstep. The TAP may also input test signals into the gold processor and DUT simultaneously and access data from each of these processors through separate test data out (TDO) connections. Test output data accessed from the gold processor may be compared to test output data accessed from the DUT to determine if any differences are present. The comparison data generated may then be used for analysis purposes.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: A method for counting correctly substantial transmission times of a data unit such as an RLC-PDU even if the data unit is divided before being transmitted is provided. The method includes the steps of preparing a counter for the RLC-PDU (#503), making a storage portion store a pointer indicating a position of a division PDU of the RLC-PDU to be transmitted every time when the division PDU obtained by dividing the RLC-PDU is transmitted (#504), determining whether or not the transmission times should be counted along with a transmission of the division PDU to be transmitted based on the pointer of the division PDU to be transmitted and the pointer of a division PDU that was transmitted last time (#505, #506 and #507), and making the counter perform the count process when it is determined that the transmission times should be counted (#508).

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract: A broadcast receiver and a method of processing data are disclosed. The broadcast receiver includes a signal receiving unit, a RS frame decoder, a decoding unit, a text-to-speech (TTS) module, a voice output unit, and a control unit. The signal receiving unit receives broadcast signal multiplexed mobile broadcast service data including text information and main broadcast service data. The RS frame decoder performs decoding on the RS frame, thereby correcting errors occurred in the corresponding mobile broadcast service data. The decoding unit decodes the text information included in the error-corrected mobile broadcast service data. The text-to-speech (TTS) module converts the text information to a voice signal. The voice output unit outputs the converted voice signal. The control unit controls the voice output unit.

Abstract: A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.

Abstract: A method for guiding to solve system errors is applied to a computer system. The method of the invention includes the step of calling a debugging application software to check a system state of the computer system when a request for detecting errors inputted by a user is received. When a system error occurring in the computer system is detected, a client database is connected to determine whether a corresponding solution for the user to debug the computer system exists. When the solution corresponding to the system error is not searched out from the client database, a network is connected to transfer a detected error message to a client service terminal.

Abstract: Provided are a scan path circuit and a semiconductor integrated circuit that can reduce time necessary for shift operation. The scan path circuit includes: a first scan FF group (7) including serially connected three scan FFs (21) and connected to a test input terminal (3); a second scan FF group (8) including three scan FFs (21) that receive an output signal of the first scan FF group (7); a third scan FF group (9) including serially connected three scan FFs (21) and connected to a test output terminal (6); and a skip circuit (22) that inputs, in a shift operation mode of the scan FF (21), the output signal of the first scan FF group (7) to the second scan FF group (8) as well as to the third scan FF group (9).