Abstract: When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the servers boot an operation system from the external disk device, task processing is taken over from the primary server to a server that is not executing a task in accordance with the following method. The method for taking over a task includes the steps of detecting that the primary server fails; searching the computer system for a server that has the same hardware configuration as that of the primary server and that is not running a task; enabling the server, searched for as a result of the search, to access the external disk device; and booting the server from the external disk device.

Abstract: The present invention improves the stability of a Web browser by identifying plug-in modules that cause failures. Data in memory at the time of a failure is analyzed, and a failure signature is generated. The failure signature is compared to a database of known failure signatures so that the source of the failure may be identified. If a plug-in module to a Web browser is identified as the source of a failure, options are presented to the user who may update the plug-in module with code that does not produce a failure or disable the plug-in module altogether.

Abstract: An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data.

Abstract: Aspects described a low receiver complexity approach for reliable packet decoding when Hybrid ARQ protocol is employed with persistent assignment and potentially an erasure sequence transmission. Multiple hypotheses packet decoding performance is achieved while mitigating multiple hypotheses receiver complexity. A reference number is utilized to perform hypotheses. The reference number is independent of a start of packet. A sequence of reference numbers can be utilized, which may not necessarily be sequential numbers. The reference numbers are pre-defined.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: A restoration device for restoring a system when the BIOS falls in a stall failure includes a first watchdog timer and a second watchdog timer, a setter for setting timer values respectively in the first watchdog timer and in the second watchdog timer, a suspender for suspending the decrement of the timer value of the first watchdog timer when the BIOS is started and also execution of a BIOS process is started, a switch for switching the BIOS data region for starting when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a resetter for resetting the system when the timer value of the first watchdog timer becomes equal to 0 or a prescribed number, a suspender for suspending the decrement of the timer value of the second watchdog timer when the BIOS of the system starts and a resetter for resetting the system when the timer value of the second watchdog timer becomes equal to 0 or a prescribed number.

Abstract: The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the main memory and execute the debugging program. After execution, an execution result of the debugging program is stored into the main memory. The execution result is read and output via the debugging interface for further analysis. Because the architecture does not require a scan chain of ITR 104, the circuit requirement is reduced while performance is increased.

Abstract: When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In particular, for each particular error detected, the parity generating information is analyzed to determine if each error involves a common disk index. If so, the data can be corrected on that disk; if not other corrective procedures are implemented.

Abstract: According to an aspect of an embodiment, a data relay apparatus for transferring writing data and an associated check code sequentially sent from a host into a memory device, said writing data containing a plurality of fields classified by the kind of information in said writing data, comprising: a memory for storing said writing data and said check code for checking an error of said writing data; a calculating module for calculating said check code to determine whether the writing data sent from the host contains an error; a transfer module for transferring the writing data into the memory, the transferring of the writing data into the memory being initiated before determination by the calculating module.

Abstract: an apparatus comprises a data display unit which causes a display device to output display data that indicates a drawing screen complying with the display request, a reliability decision unit which decides a legality of a transmission source of the display request, and which makes an output request for information capable of confirming a reliability of the display data that the data display unit causes the display device to output, on the basis of a result of the decision, and an output unit which outputs the information capable of confirming the reliability of the display data as complies with the output request from the reliability decision unit, separately from the display data that is caused to be outputted by the data display unit.

Abstract: A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a server's sub-systems and deployed applications. The SHM may make health check inquiries to server sub-systems periodically or based on external trigger events. The sub-systems perform self health checks on themselves and provide sub-system health information to requesting entities such as the SHM. Sub-systems self health updates may be based on internal events such as counters or changes in status or based on external entity requests. Corrective action may be performed upon sub-systems by the SHM depending on their health status or the health status of the server. Corrective action may also be performed by a sub-system upon itself.

Abstract: Hardware component failure diagnosis of an information handling system is verified with a hardware diagnostics code generated by a diagnostics module integrated with an information handling system and sent from the information handling system to a diagnostics engine of a service center. The hardware diagnostics code includes a unique identifier for the information handling system and a hardware component failure code that identifies the type of hardware and type of failure. The diagnostics engine analyzes the hardware diagnostics code to confirm that diagnostics were run on the information handling system and, for authentic hardware failures, automatically initiates the sending of a replacement hardware component to the information handling system.

Abstract: A method and apparatus for a template based parallel checkpoint save for a massively parallel super computer system using a parallel variation of the rsync protocol, and network broadcast. In preferred embodiments, the checkpoint data for each node is compared to a template checkpoint file that resides in the storage and that was previously produced. Embodiments herein greatly decrease the amount of data that must be transmitted and stored for faster checkpointing and increased efficiency of the computer system. Embodiments are directed to a parallel computer system with nodes arranged in a cluster with a high speed interconnect that can perform broadcast communication. The checkpoint contains a set of actual small data blocks with their corresponding checksums from all nodes in the system. The data blocks may be compressed using conventional non-lossy data compression algorithms to further reduce the overall checkpoint size.

Abstract: A test device for testing startup performance of a computer comprises a setting circuit for recording triggering times for triggering startup of the computer and a time interval between two successive startups of the computer, a monolithic chip (10) comprising an input pin connected to the setting circuit, and an output pin for connection to the computer, the input pin being configured for receiving signals containing therein from the setting circuit, the output pin being configured for sending a computer startup signal, at the time interval, to the computer in response to the received signals; and a display device (20) electronically connected with the monolithic chip, the display device being configured for displaying at least one of the triggering times and the time interval.

Abstract: A computer system includes a CPU, a memory circuit storing at least instruction codes, an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU, a code storing circuit storing data to be outputted to the CPU instead of data from the memory when an error occurs, a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, and selectively outputting data from the code storing circuit when an error is detected by the error checking circuit, a bus connecting the selection circuit to the CPU, and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit.

Abstract: An integrated circuit and related method for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and a plurality of latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for generating a first output signal that is active for a period from a predetermined time, which is after the integrated circuit is powered on and before an operating clock signal for the At Speed Test is generated, to a time when the operating clock signal is generated.

Abstract: A data processing system 2 has a memory 6 with a memory address space incorporating a plurality of domains, each domain comprising a set of memory addresses as defined by programmable domain specifying data 32. A processor core 8 executes program instructions fetched from the memory 6. Diagnostic control circuitry 20 is responsive to the domain in which a currently executing program instruction is stored to selectively disable diagnostic circuitry 14, 16, 18 used to perform diagnostic functions upon the data processing system 2. The diagnostic control circuitry 20 is responsive to diagnostic-capability-defining data 36 associated with the domains to indicate which diagnostic circuitry 14, 16, 18 is enabled for which domains.

Abstract: Errors which may be detected by an error detection unit may occur during execution of a computer program which runs on a computer system and includes at least one run-time object. In order to handle a detected error particularly flexibly and to keep the computer system available as much as possible, an error handling routine is selected from a pre-selectable set of error handling routines as a function of an identifier assigned to the run-time object and the selected error handling routine is executed.

Abstract: According to an aspect of an embodiment, a method of storing user data (UD) with parity data (PD) for correcting the UD in a storage apparatus comprising disk units, each of the disk units storing data in data blocks(DBs), each of the DBs storing the UD or associated PD and position information(PI) indicative of the location of the DBs, comprising: obtaining the UD, dividing the UD into UD blocks (UDBs) which are adapted to be stored in the DBs, and determining which UDBs are to be stored into which DBs, respectively; determining PI of the DBs for storing the UDBs; generating PD for a group of UDBs and associated PI by parity operation using a weighting function to the UDBs and the PI; determining PI for the PD for said group by modifying a part of the PD; and storing the group of the UDBs, associated PI, and the PD.

Abstract: In one embodiment of the invention, a forward error correction system comprises a client device having a FEC encoder module generating FEC encoded data based on input data and a selector module forwarding either the input data or the FEC encoded data as transmission data. The system further comprises a host device having a splitter module routing the transmission data via two data paths, a decoder module generating decoded data by decoding the transmission data and a comparator module forwarding either the transmission data or the decoded data as output data based on analyses of the transmission data and the decoded data, where the forwarding is determined by a degree of channel connectivity between the client device and the host device and where each of the two data paths lead to the decoder module and to the comparator module.

Abstract: A test pattern generation apparatus extracts processing that coincides with input combinational test confirmation processing from program test patterns stored in a file, extracts execution conditions of the extracted processing from program test pattern lists, rearranges the execution conditions, generates one test pattern, extracts data handling processing that satisfies conditions in the test pattern lists, and generates and displays a combinational test pattern list.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A repairable semiconductor memory device including a memory cell array having a first block to store first system data and a second block to store second system data identical to the first system data. A controller transmits the first system data to a memory unit in response to a reset signal output from a host and the second system data to the memory unit based on a fail detection signal generated by an ECC detection block. The ECC detection block determines whether the first system data is defective. When a defect is generated in the first system data during resetting of the semiconductor memory device, the first system data is repaired by supplying the second system data.

Abstract: A data error measuring circuit for a semiconductor memory apparatus includes a data error correction unit that compares data with parity data to correct data, a data selection unit that outputs the data or the corrected data as selected data in response to a test selection signal, and a test result output unit that receives the selected data and the parity data to output a test result signal in response to the test selection signal.

Abstract: Methods, systems, and computer-readable media for troubleshooting a problem associated with a communication system are provided. First information regarding the communication system is retrieved, and a determination is made whether the first information indicates a probable cause of the problem associated with the communication system. If the first information does indicate a probable cause of the problem, then a probable solution is provided based on the indicated probable cause. If, on the other hand, the first information does not indicate a probable cause of the problem, then information regarding the problem is retrieved. The retrieved information regarding the problem is used to determine a probable cause of the problem and a probable solution to the problem.

Abstract: A method, system and computer program product for responding to error events are provided. The method includes: detecting a detected error event while executing a computer readable program; looking for a predefined response to the detected error event in a modifiable error event response data structure; validating the modifiable error event response data structure; and responding to the detected error event according to the predefined response if the modifiable error event response data structure is valid and if the modifiable error event response data structure includes the predefined response.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically identify a characteristic of a component fabrication process guided by characteristics of the test data for the components.

Abstract: There is provided a semiconductor testing system capable of achieving a higher speed in transmission of signals while holding back an increase in the number of transmission paths, and preventing occurrence of a delay time difference between the respective transmission paths. Processing is executed in the semiconductor testing system whereby upon generation of pattern signals by the pattern generator, the pattern signals are subjected to the serial conversion to be transmitted to the test head, while the pattern signals transmitted via the transmission cables subjected to parallel conversion. Another processing is executed whereby the plural kinds of the pattern signals are allocated one by one on an address-by-address basis to be stored in the respective phase control memories to thereby detect the start address storing the pattern signal matching the first pattern signal at the start of the reading, in respect of phase.

Abstract: There is provided a probability density function separating apparatus that separates a predetermined component in a given probability density function. The probability density function separating apparatus includes a domain transforming section that is supplied with the probability density function and transforms the probability density function into a spectrum in a frequency domain, and a deterministic component computing section that multiplies a multiplier coefficient according to a type of distribution of a deterministic component included in the given probability density function by a first null frequency of the spectrum in the frequency domain and computes a peak to peak value of the probability density function with the deterministic component.

Abstract: A data communication apparatus determines whether the error type is a burst error or not based on an error occurrence state of the data received from a data transmitting apparatus and transmits error type-basis error information. The data communication apparatus receives the error type-basis error information and sets the redundancy degree of an FEC processing section based on the error rate of the errors other than a burst error.

Abstract: A power on self test (POST) method is provided. The method is a hardware detecting program applicable for a BIOS of a computer, which requires loading a detecting firmware. The method includes steps (a) running a POST program; (b) testing a hardware device by a first sequence of detecting firmware when running to a hardware detecting program of the POST program; (c) when the hardware testing program sends back an error value, outputting an error message corresponding to the hardware testing program to a memory; (d) re-booting the computer, loading next sequence of detecting firmware to the BIOS, and running the hardware testing program by the next sequence of detecting firmware; and (e) continuing to run the POST program when the hardware testing program sends back a correct value, if the hardware testing program still sends back an error value in Step (e), the process goes back to Step (c).

Abstract: In a data relay device, it is judged whether a destination address of data received from an adapter matches with an address specified for an interruption process. Only data that is judged appropriate is sent to a controller.

Abstract: Computing environments, each executing at least one software program, are monitored for failures occurring during execution of the software program. Information associated with the failure, such as an identification of the software program and a failure type describing the failure, is recorded. The failure information is quantified to report the number of times the software program has failed or the number of times a particular failure has occurred. The quantified data may provide help in prioritizing what program or what failures merit investigation and resolution. Reports may be received from failing computing systems stopped at a state following the occurrence of the failure. In response, hold information is checked to determine whether to instruct the failing computing system to hold a state existing upon the occurrence of the failure.

Abstract: A network interface unit of a server determines whether the transmission method of transmitting a packet is multicast transmission or unicast transmission; adds to the packet a second FEC when the transmission method of the packets is determined to be multicast transmission and adds to the packet an error detection code for ARQ when the transmission method of the packets is determined to be unicast transmission; and transmits the packet to clients. Each client determines whether the transmission method of the received packet is multicast transmission or unicast transmission; corrects the error on the basis of the second FEC when the transmission method is determined to be multicast transmission; and detects the error on the basis of the error detection code and generates a retransmission request signal when the transmission method is determined to be unicast transmission.

Abstract: A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.

Abstract: A software test system includes: a terminal device in which software to be tested is installed; and a software test device that stores a test driver for testing the test-target software according to test data and a test procedure of the test-target software, wherein the test driver is transmitted to the terminal device and tests the test-target software by combining the test data and the test procedure within the terminal device. A test-target program can be tested within a short time at a relatively low cost, and the reliability of the testing can be improved.

Abstract: An arrangement is provided for a data manipulation device disposed in a low profile form factor housing. A data manipulation device includes a memory configured to provide data storage and a backup storage configure to provide backup space when the memory is being backed up.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: A method and system utilizing backup disk drives in disk array systems. In one aspect, a disk array system includes one or more disk arrays, each including two or more disk drives. The system includes a spare disk drive, and a controller operative to assign the spare disk drive to a particular one of the disk arrays having a type different than the type of the spare disk drive in response to a failure of a disk drive of the particular disk array, such that the spare disk drive stores data from and operates in place of the failed disk drive.

Abstract: Embodiments disclosed herein relate to preamble configuration in wireless communication systems (e.g., UHDR-DO type systems). Disclosed embodiments disclose receiving a plurality of information bits, generating a plurality of preamble codewords based on a determined a set of monitored MAC_IDs, correlating the information bits with each of the plurality of preamble codewords, determining if a maximum correlation value exceeds a threshold, and transmitting at least one of the preamble codewords if the threshold is exceeded.

Abstract: Basic matrix based on irregular LDPC codes, codec and generation method thereof. The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: mod(i?j+k?l, z)?0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z?1} to obtain the basic matrix Hb, which is made to satisfy the above-mentioned inequality. The basic matrix Hb obtained by storing, which is configured with corresponding encoding/decoding operation module, constitutes the desired encoder/decoder.

Abstract: Error correction is tailored for the use of an ECC for correcting asymmetric errors with low magnitude in a data device, with minimal modifications to the conventional data device architecture. The technique permits error correction and data recovery to be performed with reduced-size error correcting code alphabets. For particular cases, the technique can reduce the problem of constructing codes for correcting limited magnitude asymmetric errors to the problem of constructing codes for symmetric errors over small alphabets. Also described are speed up techniques for reaching target data levels more quickly, using more aggressive memory programming operations.

Abstract: A website image capturing method includes the steps of: receiving at least one network address from a predetermined website information management system; accessing a website corresponding to the received at least one network address and determining whether a predetermined webpage error occurs in the website; generating image information through a capturing operation with respect to the website, when the webpage error does not occur in the website; generating predetermined access result information in association with the generation of the image information; and transmitting the access result information to the website information management system.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction.

Abstract: Systems and methods for improving serviceability of a memory system including a method for identifying a failing memory element in a memory system when two or more modules operate in unison in response to a read request. The method includes receiving syndrome bits and an address associated with an uncorrectable error (UE). In response to a previous correctable error (CE) having occurred, the location of the previous CE is retrieved. The location of the CE specifies a memory device position of the CE. A location of the UE is determined using the location of the previous CE and the syndrome bits of the UE as input. The location of the UE specified a memory device position. A failing memory element associated with the location of the UE is identified.

Abstract: A method for diagnosing devices via a remote testing device which is connectable to devices to be diagnosed via a communication network. Diagnosing is performed by exchanging diagnostics information between the remote-testing device and the devices to be tested via the communication network. The process of exchanging diagnostics information is at least partially done by using a communication protocol being based on XML-scripts which include the diagnostics information. The advantage of this method is a lean and platform-independent way of diagnosing devices, which enables to avoid unnecessary efforts and costs.

Abstract: A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M?1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.

Abstract: A semiconductor memory device with redundant memory cells and a method for operating a semiconductor memory device is disclosed. One embodiment provides at least one memory cell and at least one redundant memory cell. The method includes reading out data written in the memory cell; determining whether the read-out data concur with target data; reprogramming or reconfiguring, respectively, the semiconductor device, so that the redundant memory cell replaces the memory cell if the read-out data do not concur with the target data; and writing the target data in the redundant memory cell already during the reprogramming or reconfiguring, respectively.

Abstract: The present invention discloses a method of updating a dual redundant chassis management system, and the method is applied in a server. If the server obtains a change message, it creates a virtual channel between an active chassis management system and a standby chassis management system, so that the active chassis management system can be updated according to the change message, and the change message can be sent to the standby chassis management system through the virtual channel. After the active chassis management system and the standby chassis management system are updated, the virtual channel is closed to provide sufficiency transmission bandwidth and stability for data transmissions, when the server synchronously updates the active chassis management system and the standby chassis management system.