Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.

Abstract: A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.

Abstract: Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.

Abstract: Methods and apparatus for transmitting data via multiple antennas by using antenna diversity. A transmission diversity scheme is established such that two transmission matrices that are in accordance with the space frequency block code combined with Frequency switched transmit diversity (SFBC+FSTD) scheme, are alternatively applied in either the frequency domain, or the time domain, or both of the frequency domain or then time domain. The symbols in the transmission matrices may be transmitted either as one burst in a primary broadcast channel (PBCH), or as discrete bursts in the primary broadcast channel.

Abstract: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based.

Abstract: A method and apparatus for indicating a temporary block flow (TBF) to which a piggybacked acknowledgement/non-acknowledgement (PAN) field is addressed are disclosed. A sequence may be generated from a temporary flow identity (TFI) to which the PAN field is addressed and masked with a PAN check sequence (PCS). A radio block including a PAN field and a masked PCS is transmitted. The PCS may be masked with one of TFIs which is selected in accordance with a rule pre-agreed. A secondary identifier may indicate a TBF to which the PAN field is addressed. A special value may be used to represent all TBFs assigned and a secondary identifier may indicate a TBF to which the PAN field is addressed. A special value on the PAN field may be used for control purposes for indicating an action affecting a group of receiving stations listening to the radio block.

Abstract: Systems and media for generating an improved regression suite by applying harvesting models and/or regression algorithms to tests utilized in verification of a system are disclosed. In one embodiment, a regression manager responsive to user input may be coupled to a harvester module, an analysis module, and a management module. In one embodiment, the harvester module is responsive to harvesting models defined in a modeling language, where the harvester module is coupled to a regression suite database. In another embodiment, a regression methodology may be defined from a collection of regression strategies and each regression strategy may be defined from a combination of harvesting models and/or regression algorithms. A regression generator to receive tests, to apply one or more regression strategies to the tests, to provide reports, and to allow user control may also be provided.

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract: A system, a testing apparatus, and a method for testing at least one device with a connection interface are provided. The system comprises a host, a testing apparatus, and a power supply. The testing apparatus further comprises a microprocessor and at least one current limit module. The host sending a test signal. The power supply provides a voltage to the testing apparatus. The at least one current limit module of the testing apparatus, which is electrically connected to the microprocessor, the at least one device, and the power supply, provides the voltage to the at least one device. When the current passing through the at least one device is greater than the predetermined value, the at least one current limit module of the testing apparatus stops providing the voltage to the at least one device and sends an over current signal to the host via the microprocessor.

Abstract: A method and device for retransmitting data is provided. A receiving end receives a data unit, and checks whether a Negative Acknowledgement NACK->Acknowledgement, ACK, error occurs. If the NACK->ACK error occurs, the receiving end transmits an Automatic Repeat Request ARQ request message to a transmitting end, for requesting the transmitting end to perform an ARQ retransmission. Therefore, by adopting the technical solutions of the embodiment of the invention, Hybrid Automatic Repeat Request HARQ NACK->ACK errors are avoided from being missed, the complexity of ARQ operation is lowered, and the ARQ retransmission feedback time is reduced.

Abstract: A check matrix generation method for generating a check matrix H1 of a code H1 from a check matrix H0 of a code C0, where codes C0 and C1 are LDPC systematic codes having different encoding ratios in a rate-compatible relationship and information bit sizes of the systematic codes C0 and C1 are K, and parity bit sizes thereof are M0 and M1 (M1?M0=L) respectively.

Abstract: Disclosed is a method of improving iterative decoding of short codes within a demodulator. The vector of metrics of the bits considered at the output of the demodulator is decoded. The value of the check code of the CRC of the decoded word is compared with a predetermined value. If the value of the CRC is considered to form an acceptable message for the decoding step, the decoded word is transmitted to the recipient. If the value of the CRC is incompatible with a correctly decoded message, then the parameters for iterative decoding of the initial message are modified that were received from the demodulator and executing at least one new iterative decoding step with these new parameters.

Abstract: An error control method and a cooperative transfer system are provided. The method comprises: each node acting as a transfer node in a cooperative node group codes an acquired distributed information code block to obtain a corresponding distributed check code block and transmits the corresponding distributed check code block to a destination node; the destination node combines a received distributed check code block to generate a check code block and combines the distributed information code block transmitted by each node acting as a source node in the cooperative node group to generate an information code block; and the destination nod decodes the check code block and the information code block. The embodiment of the present invention may increase farthest the throughput of the transfer system and obtain additional cooperative path diversity and linear block code gain.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A quorum-based server power-down mechanism allows a manager in a computer cluster to power-down unresponsive servers in a manner that assures that an unresponsive server does not become responsive again. In order for a manager in a cluster to power down servers in the cluster, the cluster must have quorum, meaning that a majority of the computers in the cluster must be responsive. If the cluster has quorum, and if the manager server did not fail, the manager causes the failed server(s) to be powered down. If the manager server did fail, the new manager causes all unresponsive servers in the cluster to be powered down. If the power-down is successful, the resources on the failed server(s) may be failed over to other servers in the cluster that were not powered down. If the power-down is not successful, the cluster is disabled.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: A method and apparatus for channel coding and rate matching of the Physical Uplink Control Channel (PUCCH) and the Physical Downlink Control Channel (PDCCH) is disclosed that uses convolutional encoding to code the control channels. Rate matching is performed using a circular buffer based rate matching algorithm. A rate matching module may contain a single interleaver or may alternatively comprise a plurality of sub-block interleavers. Interleaved coded bits may be stored in the circular buffer in an interlaced format, or output streams from separate sub-block interleavers may be stored contiguously. When a plurality of sub-block interleavers are used, different interleaving patterns may be used. Rate matching may use bit puncturing or repetition to match the rate of the available physical channel resource. Rate matched output bits may be interleaved using a channel interleaver.

Abstract: Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all having the linear minimum distance property, and structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero.

Abstract: A serial advanced technology attachment (SATA) interface tester includes a memory, a signal converter, at least one SATA interface, and an indicator. The at least one SATA interface is adapted to connect with SATA interfaces of a motherboard, and is electrically connected to the memory via the signal converter. The signal converter receives serial signals from the motherboard via the at least one SATA interface and converts them to parallel signals and then passes the parallel signals to the memory to perform a writing process. The signal converter receives parallel signals from the memory and converts them to serial signals and passes the serial signals to the motherboard via the at least one SATA interface to perform a reading process. The indicator is electrically connected to the memory for indicating testing result of the SATA interfaces of the motherboard.

Abstract: Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the protocol tester also comprising a device for measuring the bit error rate. A corresponding method for performing a protocol test is also provided.

Abstract: A method (which can be computer implemented) for assisted remediation of at least one problem with a computer system includes the steps of obtaining data from the computer system, the data being indicative of the at least one problem; hypothesizing at least a first candidate remediation process for the problem from among a plurality of annotated remediation process descriptions, based at least in part on the data; associating at least a first attribute with the at least first candidate remediation process; and facilitating presentation of the at least first candidate remediation process with the associated attribute to a remediation agent.

Abstract: An integrated circuit device contains a flash memory, a flash control unit for controlling the rewriting and reading on the flash memory, and a processor unit. The processor unit includes a normal mode and a fail-safe mode as the operating states. In normal mode, when a defect is detected during the verify operation after writing data onto the flash memory then any further use of the flash memory is stopped. In fail-safe-mode, when a defect is detected during the verify operation after writing data onto the flash memory, the error is corrected and flash memory usage continues. The operating state is normal mode, and when the verify operation detects a defect after normal mode erase operation, the operation shifts to fail-safe mode.

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract: A reading apparatus reads data from a storage device based on which an error correcting code is to be generated. An error determining unit reads the data from the storage device, and determines whether a read error has occurred in the data. A reading unit re-reads, when the error determining unit determines that a read error has occurred in the data, the same data from the storage device.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.

Abstract: Read disturb in a flash memory destroys data that is not requested to be read, and an efficient read disturb check method is therefore needed. In addition, data may be destroyed beyond repair by error correction before a read disturb check is run. Thus, this invention provides a non-volatile data storage apparatus including a plurality of memory cells and a memory controller, in which the memory controller is configured to: count how many times data read processing has been executed in memory cells within the management area; read, when the data read processing count that is counted for a first management area exceeds a first threshold, data and an error correction code that are stored in the memory cells within the first management area; decode the read error correction code; and write the data corrected by decoding the error correction code in other management areas than the first management area.

Abstract: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same.

Abstract: A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.

Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

Abstract: A memory structure is provided. The memory structure includes a memory array, an error correct code (ECC) unit, and a comparator. The memory array includes at least one memory cell being written and storing at least one original data. The ECC unit is for reading at least one tested data from the at least one memory cell, correcting the at least one tested data when there is an error occurred in the at least one tested data and outputting at least one ECC data accordingly. The comparator is for determining whether the at least one original data is substantially the same as the at least one ECC data or not and outputting an output signal indicating whether the at least one memory cell passes or fails.

Abstract: Various example embodiments are discloses. According to one example embodiment, a method may include sending a packet to both a relay station and a destination station in a wireless network, receiving a relay station acknowledgment (ACK) or negative acknowledgment (NACK) from the relay station during an ACK/NACK frame, and receiving a destination station ACK or NACK from the destination station during the ACK/NACK frame. The relay station ACK or NACK may either acknowledge or negatively acknowledge successful receipt of the packet by the relay station. The destination station ACK or NACK may either acknowledge or negatively acknowledge successful receipt of the packet by the destination station.

Abstract: A digital broadcasting system and a data processing method are disclosed. Herein, additional encoding is performed on mobile service data, which are then transmitted, thereby providing robustness in the processed mobile service data, so that the mobile service data can respond more strongly against fast and frequent channel changes. The data processing method of a digital broadcast transmitting system includes the steps of forming a RS frame by grouping a plurality of mobile service data bytes that is being inputted, and performing error correction encoding in RS frame units, forming a super frame by grouping a plurality of the error correction encoded RS frame, performing row permutation in super frame units, and dividing the super frame back to RS frames, and dividing the RS frame into a plurality of data groups.

Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.

Abstract: A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the SAN manager outputs a corresponding relationship between virtual and real volumes. Meanwhile, the failure notification messages received from the in-SAN devices are construed to detect and output an influence of the failure upon the access to a real or virtual volume. Furthermore, when receiving a plurality of failure notifications from the devices connected to the SAN, the plurality of failure notifications are outputted with an association based on the corresponding relationship between real and virtual volumes.

Abstract: It is determined that a write access is executed to a stack area of a main memory. It is then determined whether another write access to a corresponding access destination address in the stack area occurred in the past by referring to an access flag table. In contrast, it is determined that a write access is executed to a global area of the main memory. It is then determined whether another write access to a corresponding access destination address in the global area occurred in the past with referring to an access list. Such a configuration can efficiently provide individual advantages of the determination methods using both the access flag table and the address list. The presence or absence of the past saving execution can be efficiently determined at the time of write access.

Abstract: A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.

Abstract: The test case manager interfaces with an application under test via an automation tool manager and is automation tool independent. Scripts are installed from a library based on the automation tool and the application type. The scripts perform the actions of learning the application objects, play back/validation, and automate test case creation. In a preferred embodiment, the test case manager drives the actions of the scripts. Scripts can be modified by customizing application specific actions and invoking them through the test case manager format.

Abstract: The present invention relates to a method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform. The method for verification comprises a transmission mode and a verification mode. In the transmission mode an autonomous circuit emulator (1), is created or obtained by replacing the model in a low level programming language physically describing the circuit under design to be validated with a high level (for example C++) abstract description generating response data structures in accordance with the functional specification (20) of the design as a function of the stimuli received.

Abstract: A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process.

Abstract: A software service running in the background of an operating system and used by a user to record metadata and screen shots of the user interface screens in an operating system whenever errors occur in the operating system or in any application running on the operating system. The software service also manages the recorded data to ensure resources are used efficiently to minimize the use of storage space in the recording location or buffer. The software running in the background monitors, filters and logs programs and user actions, and if a problem occurs within the monitored software, a problem report can be created for a support team to analyze and include corresponding recorded data. The suggested selection of recorded data can be displayed and edited by the user.

Abstract: A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a temporal storage memory which stores the digital data, a buffer manager which successively reads the digital data m bytes at a time from said temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the digital data m bytes at a time as the m bytes are supplied from said buffer manager so as to generate a PI sequence parity based on the digital data for one row extending in the main scan direction, and a PI parity unit which includes m operation units, each of which processes a corresponding one byte of the digital data as m bytes of the digital data are supplied from said buffer manager so as to generate a PO sequence parity based on the digital data for one column extending in the sub-scan direction.

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract: An apparatus diagnosing method is a method in which, in an apparatus including a control apparatus and a control board for controlling the control apparatus, on the controlling board, an error occurrence at the control apparatus and the control board is detected, an error signal is outputted, sensor data outputted from a sensor acquiring data about operation environments of the control apparatus and the control board is collected, and an environmental factor causing a failure or an error of the control apparatus and the control board is specified based upon the error signal and the sensor data, and the sensor data is collected in association with the error signal when the sensor data is collected.

Abstract: Upon detecting existence of characteristic information of a failure, of which search is requested, a mobile terminal device 102 notifies a failure management server 104 of the detected location information and time information together with the characteristic information of the failure, and the failure management server 104 notifies a terminal device 1022 of the location information of the failure to be estimated on the basis of the detected location information, time information, and the characteristic information of articles and allows the terminal device 1022 to output this location information. Thereby, even in the case that no communication apparatus is provided to a target apparatus, a failure can be detected and a probability of notification can be improved.

Abstract: In a storage system performing remote copy, when a failure occurs in a storage apparatus, optimum redundancy configuration is reestablished promptly. In the storage system performing remote copy, when a storage apparatus detects a failure in its disk drive, a storage apparatus capable of providing a logical unit that can be a replacement for the logical unit affected by the failure in the disk drive is searched for based on storage apparatus performance, and a redundancy configuration is reestablished using a new logical unit the found storage apparatus provides.

Abstract: Input CAD data and run-length data obtained by performing a RIP process on the input CAD data are acquired. A predetermined conversion process is performed on at least one of the input CAD data and the run-length data to make the data formats of both data comparable and then both data are compared with each other to detect an area having a difference as a defect area in the run-length data. This provides a technique to detect a defect in the run-length data to be used for drawing of a figure before the execution of drawing with a simple structure.

Abstract: Even if failure probabilities are different for hard disks due to the individual specificity such as a hard disk manufacturer, model number or the like, a disk with high failure probability is reliably determined and removed from the operating RAID to be kept in a standby state as a hot spare disk, thereby keeping a low failure probability of the disk array device. In order to realize this, the disk array device includes a disk controlling unit for, based on S.M.A.R.T. information of each of the hard disks read by a S.M.A.R.T. information reading unit, assigning a predetermined number of hard disks to the hot spare disk in descending order of failure probability of the hard disks.

Abstract: A transmitter/receiver device includes: a transmitter unit including a parallel/serial converting circuit, a waveform deteriorating circuit, and a transmitter circuit; and a receiver unit including a receiver circuit, a serial/parallel converting circuit, and an error detecting circuit. The parallel/serial converting circuit converts a transmitter-side parallel signal to a transmitter-side serial signal. The waveform deteriorating circuit deteriorates a signal waveform of the transmitter-side serial signal. The transmitter circuit transmits to the receiver unit the signal whose waveform is deteriorated. The receiver circuit receives, as a receiver-side serial signal, the signal transmitted from the transmitter circuit. The serial/parallel converting circuit converts the receiver-side serial signal to a receiver-side parallel signal. The error detecting circuit detects a bit error rate of the receiver-side parallel signal.