Abstract: A method and correct apparatus for correction of at least one digital information item which is transmitted by at least one information source to at least one information sink is provided. The information source can be connected both to an information sink and also to a correction apparatus by means of a data transmission medium.

Abstract: Interference cognitive devices are described. An interference cognitive device can be collocated with a transmitter of an interference cognitive transmitter (ICT), as receive chains or portions thereof at the ICT. An interference cognitive device can also be remote with respect to the transmitter, which operates in an interference cognitive network and receives data directly or indirectly from the interference cognitive device. The ICT uses the data to mitigate interference while continuing to operate in accordance with a performance metric.

Abstract: A protocol for optimizing the use of coded transmissions such as over wireless links. In this technique, interframes are split into segments selected to be an optimum size according to transmission characteristics of the radio channel. The inverse process is applied at the receiver. Using this scheme, segments containing erroneous data may be resent.

Abstract: A storage management program is provided with a function of determining a suspension/continuation of a remote backup based on an operation-at-failure management table, and accomplishes the suspension/continuation of the backup based on the application in which a failure has occurred and the mode of this failure. The storage management program is also provided with a function of computing a change in the quantity of data from the last backup before the occurrence of the failure until the first backup after the occurrence of the failure, and determining the suspension/continuation of the backup, enabling to suspend/continue the backup in line with the operating status of the application.

Abstract: A test and measurement instrument including an input configured to receive a signal and output digitized data; a memory configured to store reference digitized data including a reference sequence; a pattern detector configured to detect the reference sequence in the digitized data and generate a synchronization signal in response; a memory controller configured to cause the memory to output the reference digitized data in response to the synchronization signal; and a comparator configured to compare the reference digitized data output from the memory to the digitized data.

Abstract: A method and apparatus are disclosed for forming a frame of interleaved information bits in a communication system, where the decoding of the frame of interleaved information bits may begin before all of the bits in the frame are received. An exemplary interleaved frame is formed by receiving a frame of N information bits within the communication system; encoding the information bits at a code rate R to provide encoded bits; and arranging the encoded bits into a frame of N/R coded bits, wherein a plurality of puncturing patterns pi are applied to the frame of N/R coded bits such that a code rate of R/ai is produced for each of the plurality of puncturing pattern pi. The arrangement of encoded bits involves applying a puncturing pattern pj to the encoded bits; and applying a permutation function to the punctured encoded bits to generate a fractional section of the frame of N/R coded bits. The fractional section of the frame of N/R coded bits comprises N/R*aj bits.

Abstract: Data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a data input, a data output and a processing path arranged between the data input and the data output. The processing path comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal; and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data.

Abstract: A signal processing apparatus according to the present invention includes: a built-in self test device dividing a digital reference clock signal to output an I division signal and a Q division signal, shifting the I division signal and the Q division signal by predetermined angles, converting the shifted I and Q signal into analog signals to output an I testing signal and a Q testing signal; and a signal processing receiving and processing the I testing signal and the Q testing signal.

Abstract: An interleaver is constructed based on the joint constraints imposed in the channel and the code domains. A sequentially optimal algorithm is used for mapping bits in the inter-symbol interference (ISI) domain to the code domain by taking into account the ISI memory depth and the connectivity of the nodes within the parity check matrix. Primary design constraints are considered such as the parallelism factor so that the proposed system is hardware compliant in meeting high throughput requirements.

Abstract: A method of error control in a wireless access system is disclosed. More particularly, a method of error control using a random liner coding method is disclosed. A method of error control in a wireless access system comprises receiving code blocks generated as data blocks included in a data block set are randomly linear-coded; decoding a predetermined number of code blocks to a first data block set, wherein the predetermined number of code blocks are selected from the code blocks; replacing one or more code blocks among the predetermined number of code blocks with code blocks other than the predetermined number of code blocks selected from the code blocks and decoding them to a second data block set; and comparing the first data block set with the second data block set.

Abstract: Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness.

Abstract: An input estimator is based on a combined MFDQ-DF and trellis for use in, for example, an ADSL environment. In particular, for an ADSL implementation, the system will have one feedback tap for the decision feedback. However, it should be appreciated that the idea and basic concept of using the structure of a trellis to aid in determining the feedback point can be extended to any system using a feedback equalizer to estimate input to a trellis decoder.

Abstract: According to one embodiment, an error correcting circuit includes: a marker decoder configured to sample 2-bit markers from a data string and, from a plurality of sample values of the 2-bit markers, determine whether there is an occurrence of an error on the 2-bit markers, of an insertion error, or of a deletion error; and an error correcting module configured to perform first error correction on the data string received from the marker decoder by using an error correcting code in the data string. When either one of the insertion error and the deletion error is determined to have occurred, the marker decoder is configured to perform second error correction on the either one of the insertion error and the deletion error, and output the data string from which the 2-bit markers are removed.

Abstract: Methods and devices are provided for intersymbol interference encoding in a solid state drive. In an illustrative embodiment, an nth data signal is received as input to a processing component. An intersymbol interference signal applicable to the nth data signal is provided, based on a set of prior-written data in a data storage array and a set of intersymbol interference behavior of the set of prior-written data in the data storage array, the data storage array being communicatively connected to the processing component. The nth data signal and the intersymbol interference signal applicable to the nth data signal are combined into an intersymbol-interference-corrected encoding of the nth data signal. The intersymbol-interference-corrected encoding of the nth data signal is provided as output from the processing component.

Abstract: In a method for detecting anomalies in a sensor-networked environment, packages of data are received from a plurality of sensors located in the environment. At least one candidate problem location in the environment is identified based upon data contained in the packages. A principal components analysis is performed on the data collected from sensors associated with the identified at least one candidate problem location to identify a number of hidden variables and the number of hidden variables are analyzed to detect anomalies in the environment. In addition, detected anomalies are outputted. An analyzer for performing the method is provided.

Abstract: An input estimator is based on a combined MFDQ-DF and trellis for use in, for example, an ADSL environment. In particular, for an ADSL implementation, the system will have one feedback tap for the decision feedback. However, it should be appreciated that the idea and basic concept of using the structure of a trellis to aid in determining the feedback point can be extended to any system using a feedback equalizer to estimate input to a trellis decoder.

Abstract: A digital broadcasting system comprising of a digital broadcasting station, a set of digital broadcast receivers, and a switched network, wherein the digital broadcasting station transmits a digital signal to the set of digital broadcast receivers, and the digital broadcast receivers exchange error correction information with each other using the network to compensate errors in local receptions of the digital signal at each digital broadcast receiver location.

Abstract: There is provided a correcting apparatus for correcting a PDF obtained from a measurement result of measuring a characteristic of a measurement target at strobe timings including errors with respect to ideal timings at predetermined intervals, the correcting apparatus including: an interpolation section that is supplied with a CDF of the measurement result, interpolates a value between each strobe timing of the CDF, calculates a value of the CDF at each of the ideal timings, and calculates a corrected CDF at the ideal timings; and a corrected function generating section that generates a corrected PDF in which the errors of the strobe timings for the PDF have been corrected, based on the corrected CDF calculated by the interpolation section.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output.

Abstract: Techniques for accessing a memory cell in a memory circuit include: receiving a request to access a selected memory cell in the memory circuit; determining whether the selected memory cell corresponds to a normal memory cell or a weak memory cell in the memory circuit; accessing the selected memory cell using a first set of control parameters when the selected memory cell corresponds to a normal memory cell, wherein the selected memory cell provides correct data under prescribed operating specifications when accessed using the first set of control parameters; and accessing the selected memory cell using a second set of control parameters when the selected memory cell corresponds to a weak memory cell, wherein the selected memory cell provides correct data under the prescribed operating specifications when accessed using the second set of control parameters and provides incorrect data under the prescribed operating specifications when accessed using the first set of control parameters.

Abstract: A communications system for reducing bit errors in a received data sequence provides a method for generating candidate code-word sequences for evaluation by a CRC decoder. The system may determine a most-likely received sequence using the probable code-word list of candidate sequences. The number of candidate sequences may be reduced using computational complexity reduction methods. A communications device also provides a candidate sequence generator for use with a CRC decoder to determine a most-likely received sequence and to reduce bit errors in a received sequence.

Abstract: Executing a plugin includes obtaining a stability level of the plugin to be executed, determining a plugin execution mode based at least in part on the stability level, and executing the plugin according to the plugin execution mode determined. The plugin execution mode is selected from a plurality of available plugin execution modes.

Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

Abstract: An address generator of a communication data interleaver and a communication data decoding circuit are provided. The address generator includes a first operation unit and a second operation unit. The first operation unit receives a first parameter and a first operation result. The first operation unit performs a recursive operation according to the first parameter and the first operation result and outputs the first operation result. The second operation unit receives the first operation result, a second operation result, and a second parameter. According to a transmission mode signal, whether the second operation unit generates a second operation result is determined by performing a recursive operation according to the first operation result, the second parameter, and the second operation result, or by calculating the first operation result and the second parameter.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Abstract: A decoding device is provided, which can minimize the number of coded data addition requests by the decoding device, reduce processing time to prevent delay, and minimize frame rate reduction. The decoding device performs data reproduction by performing error correction of data of a predicted image using coded data which is an error correction code generated based on original data. The decoding device includes a coded bit receiving part, a preset value generating/updating part, a decoding part that performs a decoding process based on a preset value or a predicted value, and coded bits, and a bit addition request determining part that determines whether or not there is a need to request additional coded bits from decoding process results from the decoder. When it is determined to perform a decoding process with additional coded data, the preset value generating/updating part updates the preset value based on previous decoding process results.

Abstract: An estimating unit includes: an error detecting unit which detects an error among a plurality of frames received from an interface unit of a transmission device; a request sending unit which produces a first frame including a data collection request for requesting data collection upon the error detecting unit detecting the error, and which sends the first frame to the interface unit; an extracting unit which extracts, from the plurality of frames received from the interface unit, a second frame including the error detected by the error detecting unit and a third frame including a reply of the interface unit to the data collection request; and a saving unit in which the second frame extracted by the extracting unit is saved.

Abstract: Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits.

Abstract: The present invention, in preferred aspects, provides a communication method using a network coding packet in a wireless network, with reduced occurrence of negative acknowledgements, between a access point and plural mobile terminals.

Abstract: A method of identifying a parallel recovery plan for a data storage system comprises identifying base recovery plans for symbols of an erasure code implemented across a plurality of storage devices in a data storage system, generating a list of first recovery plans for a first symbol by manipulating the base recovery plans, and combining selected first recovery plans from the list to generate a set of parallel recovery plans to reconstruct a failed storage device.

Abstract: According to an aspect of the invention, an information processing apparatus includes a main body having a top face, a display connected to the main body by a hinge and pivotally moves between a first state where the top face is covered with the display and a second state where the top face is exposed, a counter which stores a number of times the state has changed between the first state and the second state, a monitor which detects a malfunction in the hinge when the number of times reaches a given number, and a data transmitter which sends data corresponding with the detected malfunction.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: A data storage medium may have data stored on one physical portion of the medium and error correction and recovery data stored on a second physical portion of the medium. In one embodiment, a write once, read many medium may be written with data and the remaining capacity of the medium may be filled with error correction and recovery data. If a portion of the main data is corrupted, the error correction and recovery data may be used to recreate the corrupted data. The error correction and recovery data may be created to fill the unused capacity of the medium by prioritizing and selectively backing up the data when the data use more than half of the medium's capacity, or may create one or more redundant copies of the data if the data consume less than half of the medium's capacity, for example.

Abstract: A method, node, and system are provided that overcome problems with using inaccurate estimates of a current round trip time RTT for verifying the ACK/NACK information received in an ACK/NACK report, e.g., a piggy-backed ACK/NACK (PAN). This is accomplished by de-coupling the RTT from the ACK/NACK analysis performed in the sending node that receives the ACK/NACK report. As a result, unnecessary re-transmissions are avoided, communication delays are decreased, and s spectrum and other system resources are used more efficiently.

Abstract: A method of processing a DAB audio stream, the method comprising: receiving a compressed and modulated DAB audio stream comprising a plurality of audio frames encoded with scale factors and a DAB-CRC error detection code for indicating errors in the scale factors; demodulating the DAB stream; and processing the demodulated and still compressed DAB stream responsive to the DAB-CRC of at least one audio frame of the plurality of audio frames; by determining a trend in values of scale factors and repairing or concealing the error in the scale factor responsive to the trend.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: A voice activity detection (VAD) dependent retransmission scheme is described that mitigates the effect of packet loss on an audio signal transmitted between terminals in a wireless communication system in a manner that is generally more robust than conventional state-of-the art packet loss concealment algorithms but that consumes less terminal power as compared to conventional retransmission schemes. In one implementation, this is achieved by allowing retransmissions to be requested by a terminal only when a packet received by the terminal is deemed bad and when a portion of an audio signal currently being received by the terminal is deemed to comprise active speech. In other implementations, the processing of retransmission requests received by a terminal is inhibited or turned off entirely during periods when a portion of an audio signal currently being transmitted by the terminal is deemed not to comprise active speech.

Abstract: A transmitting device and method enabling improvement of the reception quality on the receiving side when the LDPC-CC (Low-Density Parity-Check Convolutional Codes) encoding is used. The transmitting device (100) comprises an LDPC-CC encoding section (102), a sorting section (121) for sorting the encoded data (120) acquired by the LDPC-CC encoding section (102) into a first encoded data set (103_A) corresponding to the column number of the column containing “1” in a part of an LDPC-CC check matrix H from which a protograph is excluded and a second encoded data set (103_B) corresponding to the column numbers of the columns other than that, and a frame constructing section (a control section (106)) for constructing a transmission frame where the first and second encoded data sets (103_A, 103_B) are arranged in positions different in time or frequency in the transmission frame.

Abstract: An apparatus and method of supporting the backup and recovery of a computing device. The computing device typically includes both a user computing environment and a supporting environment which enhances the stability and functionality of the user computing environment.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: A plurality of catalogs are maintained, and wherein each catalog of the plurality of catalogs includes data sets and attributes of the data sets. An indication that a new data set is to be defined is received. A selected catalog is determined from the plurality of catalogs, wherein the selected catalog is suitable for including the new data set and attributes of the new data set. An entry that indicates a data set name corresponding to the new data set and an index to the selected catalog is inserted in a group table.

Abstract: The invention provides a topology collection method and dual control board device applicable to a stacking system comprising dual control board devices. A master control board of a dual control board device advertises through a stack port the topology information of the member device in which the master control board resides, including information about the master control board and, if a slave control board is present, information about the slave control board; and stores the topology information or updates the existing topology information upon receiving the topology information of the stacking system through the stack port, and backs up the stored topology information of the stacking system to the slave control board after the slave control board is inserted. This invention is applicable for collecting the topology information of a stacking system comprising distributed dual control board devices.

Abstract: Provided is a united Adaptive Forward Error Correction (U-AFEC), including: an automatic gain control unit for controlling a gain of forward/backward relay signals; a switching unit for switching the forward/backward relay signals; a forward feedback signal detecting unit for detecting and updating a phase and a size of a feedback signal; a backward feedback signal detecting unit for detecting and updating the phase and the size of the feedback signal; a reverse feedback signal synthesizing unit for generating a reverse feedback signal based on the phase and the size of the feedback signal; a feedback signal removing unit for removing the feedback signal in the forward/backward relay signals and transmitting the forward/backward relay signals to the automatic gain control unit; and a control unit for removing the feedback signal in the forward/backward relay signals and controlling each constituent element.

Abstract: A process for verifying computers is provided. The process characterizes a golden sample computer preconfigured to customers' configuration preferences, and stores the results and links the results to the specific customers. The process then checks output computers by retrieving the appropriate characterization results and verifying the output computers based on the characterization results. If the output computer passes, it is shipped, but if it fails, it can be easily reconfigured based on the results of the verification phase.

Abstract: A channel interleaver comprises a novel constellation-based permutation module. The channel interleaver first receives a plurality of sets of encoded bits generated from an FEC encoder. The encoded bits are distributed into multiple subblocks and each subblock comprises a plurality of adjacent bits. A subblock interleaver interleaves each subblock and outputs a plurality of interleaved bits. The constellation-based permutation module rearranges the interleaved bits and outputs a plurality of rearranged bits. The rearranged bits are supplied to a symbol mapper such that a plurality of consecutively encoded bits in the same set of the encoded bits generated from the FEC encoder is prevented to be mapped onto the same level of bit reliability of a modulation symbol. In addition, the plurality of adjacent bits of each subblock is also prevented to be mapped onto the same level of bit reliability to achieve constellation diversity and to improve decoding performance.

Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.

Abstract: In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

Abstract: The present invention determines an incorrect packet from a faulty partition quickly and reliably and prevents the packet from flowing into normal partitions through simple control actions. The multi-partition computer system is a multi-partitioned computer system in which a plurality of nodes are logically divided into a plurality of partition, and each node contained in the partitions includes a packet identification unit which, upon receiving a packet, compares the partition identification information uniquely assigned to own partition against the partition identification information contained in the receive packet, and if these pieces of information do not match each other, judges and discards the receive packet as an incorrect packet.

Abstract: A receiving system and data processing method therein are disclosed, by which mobile service data is received and processed.