Abstract: A system for implementing self aggregating communication operations. Wireless communication transports may utilize basic radio transmission units for communication (e.g., such as a symbol, groups of symbols, etc.). Radio transmission units may comprise, for example, one or more message packets. The one or more message packets may be added to a radio transmission unit in preparation for wireless transmission. If unused space exists in the radio transmission unit after the one or more packets have been added, copies of the one or more the packets may also be inserted into the radio transmission unit. Any unfilled space remaining in the radio transmission unit that cannot accommodate complete copies of the one or more message packets may be filled utilizing zero padding. Radio transmission units composed in this manner (e.g., including multiple occurrences of each packet) may be deemed “self aggregated.

Abstract: Embodiments disclosed herein are configured for retransmission above the gamma (?) interface. At least one embodiment of a method includes receiving data from an Ethernet layer, the data being identified as eligible for retransmission or not eligible for retransmission; in response to a determination that the data is eligible for retransmission, storing a copy of at least a portion of the data in a retransmission queue; and transmitting the data across a gamma (?) interface to a packet transfer mode transmission convergence layer.

Abstract: A system and methods for detecting an operational problem on a mobile device and automatically resolving the problem with a coordinated execution of repair tasks on the mobile device and on the plurality of servers communicatively connected to the mobile device providing for a complex solution to an operational problem. The system can archive a history of corrective actions and their outcome for later analysis and reporting.

Abstract: A resizable cache memory is disclosed. In a particular embodiment, a system is disclosed and includes a Built-In Self Test (BIST) circuit configured to test a cache memory. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit.

Abstract: A system-on-a-chip (SOC) includes a memory system, a data processor and a read only memory (ROM). The memory system includes random access memory and a memory controller. The data processor includes at least one functional block that communicates data with the memory system via the memory controller. The ROM stores data and one or more parity bits for detecting and correcting errors in the data. The data includes chip information and/or security information for the SOC. A method of using the SOC includes storing data in the ROM that includes chip information and/or security information for the SOC; storing in the ROM the one or more parity bits for the data; reading the data and the one or more parity bits from the ROM; detecting and correcting errors in the data using the one or more parity bits; and outputting the corrected data.

Abstract: A system locates a user in a remote troubleshooting environment. An office device is utilized to perform at least one of a copy, a facsimile, a print, and an email. A headset facilities audio communication between the user and a remote troubleshooter. A compass is located proximate to the office device wherein the headset is placed in a predetermined location proximate to the compass to establish a datum point such that movement from the datum point is recognized as a location proximate to the office device. A remote processing component displays the location of the headset relative to the office device based on information provided by the compass.

Abstract: In a generic Media Access Control (MAC) protocol, the retransmission of a dropped MAC frame is independent of the payload. Methods, systems, and computer products defining a mechanism of retransmission of one or more frames based on content of the payload are provided. The system identifies the content as text or video and retransmits if the content is text. The one or more frames may be retransmitted using a specific retransmission scheme. The retransmission is checked again to determine if it is was dropped, and transmitted again if it was dropped.

Abstract: A VSB communication system comprises a VSB transmission system and a VSB reception system. The VSB transmission system multiplexes a coded MPEG data and a coded supplemental data having a null sequence inserted therein, with required multiplexing information included in a field synchronization signal or in a supplemental data according to a number of the supplemental data packets being transmitted. The VSB reception system detects the required multiplexing information from the field synchronization signal or the supplemental data and decodes the multiplexed data by using the null sequence and the detected multiplexing information, as well as demultiplexes the multiplexed data into the MPEG data and the supplemental data.

Abstract: A system and method are described for aggregating management of devices connected to a server. In one embodiment, devices connected to a server may be identified by an operating system of the server. The devices may be in communication with one another through a network. The operating system may communicate a network identifier of each device to a service processor of the server. The service processor may aggregately manage the devices independent from the operating system. The service processor may receive management commands from an external source. Each of the management commands may be associated with one of the connected devices, but the connected devices may be incapable of communicating directly with the external source. The service processor may communicate each management command to the device associated with the management command using the network identifier of the associated device. The management command can then be performed on the associated device.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: In a wireless communication system (200), a compact control signaling scheme is provided for signaling the selected retransmission mode and codeword identifier for a codeword retransmission when one of a plurality of codewords (CW1, CW2) being transmitted over two codeword pipes to a receiver (201.i) fails the transmission and when the base station/transmitter (210) switches from a higher order channel rank (231) to a lower order channel rank (241), either by including one or more additional signaling bits in the control signal (240) to identify the retransmitted codeword, or by re-using existing control signal information in a way that can be recognized by the subscriber station/receiver to identify the retransmitted codeword. With the compact control signal, the receiver (201.i) is able to determine which codeword is being retransmitted and to determine the corresponding time-frequency resource allocation for the retransmitted codeword.

Abstract: A method of recovering data in a line signal which is predicted to be subjected to repetitive noise impulses, the line signal comprising a series of data frames, the method comprising the steps of: predicting a group comprising one or more frames in said line signal which are expected to be corrupted by a noise signal; blanking said group of one or more frames which are predicted to be corrupted; determining the preceding and succeeding frames adjacent to said group; and including in each said group or more frames one or more parity blocks wherein if said noise signal deviates from its predicted timing interval or duration and corrupts the data carried in one or more of said frames adjacent to said group, the corrupted data is recovered using one or more of said parity blocks of said group of blanked frames and the other one of said adjacent frames.

Abstract: A method of data mirroring in a serial-connected memory system between a first and a second memory device. A bypass command is issued to the first memory device, then a write data packet is provided to the first and second memory devices, and then a write data packet command is provided to the first and second memory devices by wherein the write data packet is passed to the second memory device through the first memory device. Mirroring of the write data packet into the first and second memory devices is thereby achieved. ECC (error correction codes) within spare fields provide means for recovering data after failure. The serial-connected memory system is especially useful for implementing SSD (solid-state disk) memory systems.

Abstract: In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.

Abstract: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection check; calculate a false detection variable for hypothetical trellis paths that passed the forward check; and determine the end point of the received frame in response to the calculations. Wherein the calculation of the forward detection check is much faster than the calculation of the false detection variable.

Abstract: Embodiments of the invention are generally related to retrieving debug data from a plurality of nodes of a parallel computer system. To retrieve debug data, a message may be broadcast from a service node of the system to each of the plurality of nodes via a first network, the message indicating a debug operation that is to be performed. A node of the plurality of nodes may transfer an interrupt signal to the rest of the plurality of nodes via a second network. Upon receiving the interrupt signal, the plurality of nodes may perform the debug operation comprising transferring the debug data to the service node via a third network.

Abstract: A method of handling a message in a messaging system is provided. The messaging system comprises a message source, a message receiver and a message service.

Abstract: Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, a

Abstract: An information system includes a housing with a plurality of units mounted thereon, a communication path built in the housing to take charge of information communication between a plurality of the units mounted on the housing, an information unit mounted on the housing to provide and process the information, a plurality of communication units each mounted on the housing to independently relay the information communication between the information unit and a device external to the housing, and a management unit for accessing the whole or a part of the plurality of the units mounted on the housing and acquiring internal information of the units accessed, wherein in the case where all the plurality of the communication units accessed are incommunicable, the internal information acquired from the plurality of the communication units is reported to the device external to the housing without passing through the plurality of the communication units.

Abstract: Embodiments disclosed herein include systems and methods of packet retransmission. More specifically, at least one nonlimiting example of a method includes receiving data from above a ? (gamma) interface, the data being identified as protected or not protected data; and storing the protected fragment in a retransmission queue included in a transport protocol specific transmission convergence layer.

Abstract: Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.

Abstract: A system includes: at least one managed resource having an agent for collecting and transmitting performance information; an integrated management server for receiving the information and managing it in an integrated manner; a statistical information generating module for extracting previously set performance items and automatically generating statistical information for each performance item; and a fault management server for receiving the information from the integrated management server in real time, performing statistical analysis on current performance information, comparing the analysis results with the information generated by the statistical information generating module to determine whether a fault is likely to occur, generating a fault event according to the determination result, and transmitting the fault event to the integrated management server.

Abstract: A security processor integrated within a system may be securely shut down. The security processor may receive shut down requests, and may determine components and/or subsystems that need be shut down during shut down periods. The security processor may determine when each of the relevant components is ready for shut down. Once the relevant components are shut down, the security processor may itself be shut down, wherein the shut down of the security processor may be performed by stopping the clocking of the security processor. A security error monitor may monitor the system during shut down periods, and the security processor may be powered back on when security breaches and/or threats may be detected via the security error monitor. The security error monitor may be enabled to power on the security processor by reactivating the security processor clock, and the security processor may then power on the system.

Abstract: A terminal device includes: a time information receiving unit which receives measured time and an estimated error of another terminal device; an estimated error calculating unit which calculates an error containing the estimated error of another terminal device received by the time information receiving unit as an updating-use estimated error; and a time updating unit which, when the updating-use estimated error calculated by the estimated error calculating unit is smaller than an estimated error stored in an estimated error memory unit, stores the updating-use estimated error calculated by the estimated error calculating unit in the estimated error memory unit thus updating the estimated error stored in the estimated error memory unit, and adjusts a measured time measured by a time measuring unit in response to the measured time of another terminal device received by the time information receiving unit.

Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.

Abstract: The invention relates to a method for replacing a device in a network comprising a plurality of devices. The method includes a step of storing (132) replicated data of a first device in a storage means, a step of removing (352) the first device from the network, a step of connecting (354) a second device to the network, a step of providing (262) a replacement information comprising the first identifier and a step of providing (272) the replicated data of the first device from the storage means to the second device.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: Techniques for supporting high decoding throughput are described. A transmitter may encode a code block of data bits with a Turbo encoder. A receiver may perform decoding for the code block with a Turbo decoder having multiple soft-input soft-output (SISO) decoders. A contention-free Turbo interleaver may be used if the code block size is larger than a threshold size. A regular Turbo interleaver may be used if the code block size is equal to or smaller than the threshold size. The contention-free Turbo interleaver reorders the data bits in the code block such that information from the multiple SISO decoders, after interleaving or deinterleaving, can be written in parallel to multiple storage units in each write cycle without encountering memory access contention. The regular Turbo interleaver can reorder the data bits in the code block in any manner without regard to contention-free memory access.

Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Abstract: Systems and methodologies are described herein that facilitate techniques for managing respective original transmissions and re-transmissions of information within a wireless communication system. Various mechanisms are described herein for processing a new data indicator (NDI) associated with respective transmissions conducted for one or more Hybrid Automatic Repeat Request (HARQ) processes. For example, for a HARQ process shared between distinct scheduling schemes, an NDI associated with a latter transmission can be regarded as toggled irrespective of the value of the NDI upon recognizing that a utilized scheduling scheme (e.g., as indicated via a radio network temporary identifier (RNTI) or the like) has changed between successive transmissions (e.g., from semi-persistent scheduling to dynamic scheduling), thereby allowing processing of the latter transmission as a transmission of new data.

Abstract: The present invention relates to the communication field, and discloses a method and an apparatus for encoding, decoding, receiving and transmitting data to improve the encoding gain of the FEC encoding without increasing transmission overhead. In the present invention, no FEC encoding is performed for the minor bits in the block header of the information blocks. The block header may be a sync header. The bit indicative of the data type serves as a major bit, and is protected through FEC encoding; the bit for the only purpose of block synchronization serves as a minor bit, which is not involved in the FEC encoding and decoding. When the buffered data are deficient, padding blocks are padded into the buffer to trigger the FEC encoding in time; after the FEC encoding, the padding block is removed from the encoding result, thus avoiding transmission of unnecessary data.

Abstract: An event data transmission scheme is provided for reducing positron emission tomography event losses. The event data transmission scheme employs a more effective use of available data bandwidth. Each of a plurality of detector data slots is connected directly to a data aggregation control interface, and the control interface is connected to a coincidence processor.

Abstract: There is provided a system and method for detecting an ignoring an invalid channel map feature. More specifically, in one embodiment, there is provided a method, comprising receiving an initial channel map feature, determining a cyclic redundancy check value for the initial channel map feature, receiving a subsequent channel map feature, determining a cyclic redundancy check value for the subsequent channel map feature, and processing the initial or the subsequent channel map feature if the cyclic redundancy check values for each of the initial and subsequent cyclic redundancy check values match.

Abstract: Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described.

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: In a clustered processing system, replication logic controls replication of object data to one of more replica instances. Correction logic generates correction data based on the object data and generates code words by combining the object data and the correction data. The code words are transmitted to the one or more replica instances such that correctable errors in the object data can be corrected without re-transmission of the object data.

Abstract: An apparatus of generating the optimum reference level of a Viterbi decoder for an input signal includes: a first reference level detection unit detecting a first reference level using a delayed input signal from the Viterbi decoder and an output signal of the Viterbi decoder; a second reference level detection unit detecting a second reference level using input signals input after and before one clock cycle with respect to the delayed input signal and the output signal; and a control unit controlling one of the first reference level and the second reference level to be the reference level of the Viterbi decoder by using a result of comparison between a first square level error for the first reference level calculated in the first reference level detection unit and a second square level error for the second reference level calculated in the second reference level detection unit.

Abstract: A method of diagnosing a fault condition within software can include, responsive to a fault condition within a computing system belonging to an organization, automatically sending call-stack information for the fault condition to a first server within the organization. Within the first server, the call-stack information for the fault condition can be compared with call-stack information from prior fault conditions that occurred within the organization to determine whether the call-stack information for the fault condition matches call-stack information from one of the prior fault conditions. The method further can include sending the call-stack information to a second server for comparison with call-stack information from prior fault conditions that occurred within at least one different organization if the call-stack information for the fault condition does not match.

Abstract: In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable.

Abstract: Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is composed of a symbol injection part for an active element 5 and a symbol injection part for a passive element 7, an occurrence probability providing part 9, an equal occurrence probability providing part 11, and a switching part 13. A per-test X-fault diagnosis flow by the diagnostic device 1 consists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element 7, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution.

Abstract: A method of detecting a network hang and restoring an application that communicates on a connection giving rise to the network hang. A user experience may be improved by providing the user with an option to restore the hung application without losing unsaved data or state information. The network hang may be detected when the user tries to terminate the application. The method may include determining whether the network hang is recoverable, which may involve diagnosing a type of the hang. If recoverable, a network connection reset mechanism may be triggered by instructing a network stack of the computer to terminate the network connection.

Abstract: A method for re-transmission in a multiple-input multiple-output (MIMO) communication system, the method comprising: performing spatial mapping of one or more retransmitted data streams and one or more newly transmitted data streams, wherein the spatial mapping comprises switching bits between the re-transmission data streams and the new transmission data streams.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: A context analyzer may be configured to receive, from a software support system associated with a software application associated with multiple architectural layers, an incident report associated with a software incident of the software application. The incident report may include context information associated with the software application at the time of the software incident, the context information being received from a plurality of context providers. An incident model generator may be configured to determine, from parsed context information output by a first context parser and a second context parser, a plurality of entities and links therebetween associated with the software application, and configured to display an incident model that includes the entities and the links and that provides access to the parsed context information on an entity-specific basis.

Abstract: A method and apparatus for power control of the re-transmission data packet in a wireless communication system is disclosed. A first wireless communication device is provided that receives (210) a data packet from a second wireless communication device and determines (220) if the data packet is correctly decoded. If the data packet is not correctly decoded, the first wireless communication device calculates (230) a first re-transmission power required for correctly decoding the data packet based on a signal to noise ratio (Eb/No) versus frame error rate (FER) relationship. And further calculates a power difference (240) between the calculated re-transmission power and the power of the received data packet and transmits the power difference (250) to the second wireless communication device. The second wireless communication device calculates (340) a second re-transmission power based on the received power difference and re-transmits (350) the data packet at the calculated re-transmission power.

Abstract: An apparatus for wireless communications is disclosed that includes a processing system configured to generate a first data packet and thereafter a second data packet, wherein each of the first and second data packets including a header and data, the processing system being further configured to generate an error correction code associated with the first data packet and embed the error correction code in the header of the second data packet.

Abstract: A digital broadcasting system and a data processing method are disclosed. A receiving system of the digital broadcasting system includes a receiving unit, a demodulator, an equalizer, a block decoder, and a RS frame decoder. The receiving unit receives a broadcast signal including mobile service data and main service data. The mobile service data may configure a RS frame. The RS frame includes at least one data packet for the mobile service data, RS parity generated based on the at least one data packet, and CRC checksum generated based on the at least one data packet and the RS parity. The demodulator converts RS frame data included in the broadcast signal received by the receiving unit into a baseband RS frame data. The equalizer performs channel equalization on the data demodulated by the demodulator. The block decoder performs symbol-decoding on the data channel-equalized by the equalizer in block units.

Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.

Abstract: An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic path. In turn, the LBIST tests one or more timed signal transitions that are dependent upon the stabilized untimed logic path.

Abstract: An apparatus and method for measuring frame loss in multicast service traffic are provided. The method of measuring frame loss includes: counting the number of data frames of a predetermined multicast service flowing into an object network of frame loss measurement; counting the number of data frames of the predetermined multicast service flowing out of the network; and measuring frame loss by comparing the counted number of incoming frames and the counted number of outgoing frames. According to the method and apparatus, in a multicast service environment which is dynamically changing, frame loss of a predetermined multicast service can be conveniently and easily measured.