Abstract: Embodiments of a system and methodology are disclosed for enabling a network to manage threshold values provided to UEs for use in decoding ACK-NAK signals. In various embodiments described herein, a base station signals an actual fixed threshold value in a semi-static manner for use by UEs to decode ACK/NAK signals. In these embodiments, the threshold value is part of a semi-static but UE-specific threshold value. This allows the base station to accommodate varying UE geometries, and optimize power savings for ACK-NAK transmissions. Embodiments of the invention also allow the base station to enforce a desired quality of service (QoS) without excessive power variations across ACK/NAK which are limited by the transmit power dynamic range.

Abstract: An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by ‘b’, has a length of Lb+N, wherein Lb is the length of the storage branch prior to appending N.

Abstract: A method, apparatus, and article of manufacture to dynamically address and resolve an improper shut-down of an application. Internal state data of the application is stored in persistent memory. New internal state data is dynamically created and authenticated following an improper shut-down of the application. Responsive to the authentication, the application is re-started with the authenticated new internal state data, without being subject to an immediate improper shut-down.

Abstract: An apparatus or method for testing of a SOC processor device may minimize interference that is caused by interfacing a comparatively low-speed testing device with the high-speed processor during testing. Implementations may gate the input clock signal at the clock input to each domain of the SOC processor device rather than at the output of the PLL clock. The gating of the clock signal to each domain may then be controlled by clock stop signals generated by the testing device and sent to the individual domains of the processor device. Gating the clock signal at the domain may provide a more natural state for the circuit during testing as well as allow the test control unit to test the different domains of the SOC device individually.

Abstract: A method according to one embodiment includes monitoring a data transfer operation for detecting temporary errors; determining whether art error burst has occurred based on the monitoring; if an error burst has occurred, altering a condition of the data transfer operation; monitoring the data transfer operation having the altered condition for detecting temporary errors; determining whether another error burst has occurred based on the monitoring of the data transfer operation having the altered condition; and if another error burst has occurred; altering another condition of the data transfer operation. Additional systems and methods are also presented.

Abstract: A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system.

Abstract: Embodiments of the present invention provide a system for executing program code on a processor. In these embodiments, the processor is configured to start by using a primary strand to execute program code. Upon detecting a predetermined condition, the processor is configured to instantaneously checkpoint an architectural state of the primary strand and then use the subordinate strand to copy the checkpointed state to memory while using the primary strand to continue executing the program code without interruption.

Abstract: Various methods for data transmission based on signal priority and channel reliability are provided. One example method includes encoding a number of bits into coded bits including systematic bits and respective associated parity bits, the bits being encoded for transmission via channels of a multi-channel communications system including a more reliable channel and a less reliable channel. The example method also includes allocating the systematic bits to bit locations within a first stream corresponding to the more reliable channel, allocating the systematic bits to bit locations having a higher signal priority within a second stream corresponding to the less reliable channel, and allocating the parity bits to bit locations within the second stream. Similar and related example methods and apparatuses for allocating the systematic and parity bits to the respective bit locations in both the more and less reliable channels are also provided.

Abstract: A detection apparatus detecting an error component contained in two signals (A, B) approximated by a cosine and sine functions representing an object position, the detection apparatus including an arithmetic portion (3, 4) which reduces an error contained in the signals (A, B) based on an error prediction value to output two error correction signals (A*, B*), a phase arithmetic portion (5) which calculates a phase (?) based on the error correction signals (A*, B*), an arithmetic storage unit (9, 10) which stores the error correction signals (A*, B*) and a plurality of sampling values of the phase (?), and a Fourier transform portion (11, 12) which obtains coefficients ?k, ?k, ?k, and ?k in the following two expressions: A*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? B*=?0+?1 cos ?+?1 sin ?+ . . . +?k cos k?+?k sin k? (k?2) wherein the arithmetic portion (3, 4) updates the error prediction value using the coefficients.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Abstract: Disclosed is a display device including a first storage unit having driving data for driving a display panel and a first check SUM data on the driving data stored therein, a second storage unit for retrieving the driving data and the first check SUM data from the first storage unit and storing the driving data and the check SUM data in response to the instruction of a ROM interface, and a data error detection/correction unit generating a second check SUM data with reference to the driving data stored in the second storage unit.

Abstract: A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first measuring operating mode using a controllable integrated multiplexer to measure an asymmetrical signal lag of a measuring path, which includes the integrated signal path and the integrated multiplexer, and a measuring signal being able to be decoupled in a second measuring operating mode using the controllable integrated multiplexer to measure the asymmetrical signal lag of the integrated multiplexer.

Abstract: The present invention pertains to the field of data communications and is directed to providing ways and means for flexible receipt reporting. A transceiving unit (1) is operated (61) to receive at least one sequence of data blocks (9) where the data blocks each have a respective sequence number (31). The receipt of the data blocks is monitored (63) to establish whether the data blocks have been successfully received or not. A receipt report is selectively generated (65) based at least in part on the performed monitoring.

Abstract: According to methods and apparatuses for performing error detection and error correction for a synchronization frame in embodiments of the present invention, a transmitter acquires a transmitter check sequence according to contents of a synchronization frame sequence; and a receiver acquires a receiver information sequence related to the check sequence. When performing error detection, the receiver acquires a receiver check sequence according to the receiver information sequence and a generator polynomial and determines whether the synchronization frame transmission is valid according to the receiver check sequence and the transmitter check sequence; when performing error correction, the receiver acquires a syndrome sequence according to the receiver information sequence, acquires an error pattern according to the syndrome sequence and acquires a result of error correction according to the error pattern and the receiver information sequence.

Abstract: A series of pulses may be driven down each drive channel, which creates a series of composite pulses at the output of the buffer. Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels, and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels.

Abstract: A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data.

Abstract: To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.

Abstract: A protocol for optimizing the use of coded transmissions such as over wireless links. In this technique, interframes are split into segments selected to be an optimum size according to transmission characteristics of the radio channel. The inverse process is applied at the receiver. Using this scheme, segments containing erroneous data may be present.

Abstract: A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices.

Abstract: A communication method according to an automatic repeat request scheme in a mobile communication system includes transmitting a retransmission packet per certain time period (periodically) in response to NACK of a first user equipment related to a first packet transmitted within a frame group consisting of a plurality of successive frames, and transmitting a retransmission packet non-periodically in response to NACK of a second user equipment related to a second packet transmitted within the frame group.

Abstract: A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and a second symbol stream using minimum mean squared error with ordered successive interference cancellation (MMSE-OSIC) based detection. When the decoded signal associated with the first symbol stream fails the cyclic redundancy check, the channel-coded signals in the first and second symbol streams are detected using neighbor search algorithm (NSA) based detection.

Abstract: A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.

Abstract: A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

Abstract: The error correction capability for wireless communication carried out involving propagation path fluctuation in time and frequency selectivity can be improved. A soft decision likelihood value inputted to an error correction decoder is multiplied by a weight determined according to the distance between the data symbol and pilot symbol corresponding to the soft decision likelihood value. Namely, the soft decision bit likelihood value corresponding to the data symbol is weighted according to the distances in time or frequency between the pilot symbol and data symbol. The weight is made smaller when the distance in time or frequency is larger.

Abstract: According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal over the power line. The spectral shaped module is adapted to compensate for amplitude distortion and further compensates for attenuations that will be realized during propagation of the transmitted signal over the power line.

Abstract: An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: Various technologies and techniques are disclosed for using historical trends from prior tests to prioritize how failures are reported in later tests. After a user changes a software development project, one or more tests are run to detect failures during execution of the tests. Any detected failures are analyzed in comparison with historical failures for the software development project across tests run for multiple users. Any detected failures are categorized as new or old. New failures are reported with a different emphasis than old failures, such as with new failures being reported as a higher priority than old failures.

Abstract: Various technologies and techniques are disclosed for dynamically determining test platforms. A test platform matrix is generated for use with a test run. The test platform matrix is generated based on a combination of test coverage specifications and a history of test coverage from prior runs. Machines are provisioned for executing the test run according to the test platform matrix. Different system configurations are tested than prior system configurations that were tested in a most recent prior run.

Abstract: Techniques for finding an optimized local repair path that may be used to signal a local repair connection for a protected connection. The optimized local repair path starts at a node in the path associated with the protected connection and ends at a merge point node in the path associated with the protected connection that is downstream from the start node. Various techniques may be used for finding an optimized local repair path.

Abstract: Techniques for configuring a local repair connection for a protected connection including determining a path for the local repair connection. The path traversed by a local repair connection starts at a node in the path associated with the protected connection and ends at a merge point node in the path associated with the protected connection that is downstream from the start node. In one embodiment, the merge point node may even be more than two hops downstream from the start node in the path associated with the protected connection. The local repair path may include zero or more nodes that are not included in the path associated with the protected connection. Techniques are also described for optimizing the path associated with a local repair connection.

Abstract: Systems and methods for transmitting and receiving additional data, such as video data, over legacy satellite digital audio radio signals are provided. In exemplary embodiments, hierarchical modulation can be used to transmit secondary information over a legacy signal. For example, the Sirius Satellite Digital Audio Radio Service (“SDARS”) system may use a second layer of modulation to transmit video data on top of its regular audio signal. In order to support such future services within the original system design, sometimes referred to herein as a “legacy” system, additional information bandwidth can be acquired, for example, by using hierarchical modulation to overlay data for such new services on top of the legacy transmission. In such a system, for example, overlay data can be transmitted by applying a programmable angular offset to legacy QPSK symbols, for forming a new constellation similar to 8PSK.

Abstract: This disclosure provides a method of routing communications over a network through an intermediate destination, and it also provides a “universal proxy” that may be used for this purpose. A host wishing to deliver information to a client sends packets as part of a first exchange or “session” to the intermediate destination, which performs error detection and recovery for received packets. The intermediate destination then (if desired) masks the source and transmits the information to the client in a second session, with the intermediate destination controlling transmission (e.g., specifying transmission protocol) and performing loss recovery as appropriate. This methodology enables a number of applications, including masquerading of source identity through the intermediate destination, and TCP acceleration (e.g., by subscribing to a service where the intermediate destination is used to accelerate communications or offer special types of processing or services).

Abstract: Apparatus, systems and methods are described that facilitate the detection of errors within a remote control for a controlled device. A remote control detects an error condition during operation and transmits information regarding the error to a controlled device. The information regarding the error may be analyzed to determine the source of the problem in the remote control and/or possible solutions.

Abstract: An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.

Abstract: A method is disclosed for correcting misdirected Advanced Shipping Notices (ASNs). In one embodiment, the method receives, from a product supplier, a first set of data associated with an ASN, where the first set of data includes an ASN receiving facility identifier. The method also determines a Purchase Order (PO) that is associated with the ASN, where the PO includes a second set of data. The method further compares one or more fields of the first set of data with one or more fields of the second set of data. In addition, the method determines if the ASN was misdirected based on the comparison, and corrects the ASN, when it is determined that the ASN was misdirected.

Abstract: Apparatus, system and method of efficiently utilizing hardware resources for a software test in system having at least one redundant component, at least a part of which is used for the software test.

Abstract: A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.

Abstract: A steady state value of each parameter in a set of one or more parameters of a computer system under test is defined, and acts related to the parameter are performed while the system under test is processing one or more test workloads. The acts can include comparing a working value of the parameter with the steady state value of the parameter, as well as operating on one or more workloads to bring the working value closer to a steady state value. This can include increasing or decreasing the working value of the parameter, such as by admitting one or more workloads to the system under test or cancelling one or more workloads from the system under test.

Abstract: A storage control apparatus includes a plurality of temporary storage units that are managed in a redundant manner by data mirroring, and temporarily store data input from an outside source; a temporary-storage control unit that controls input and output of the data to the temporary storage units; and a mirroring control unit that controls the data mirroring between the temporary storage units, checks, when performing the data mirroring, validity of the data stored in a temporary storage unit of a mirroring source, and executes, when the validity of the data has been confirmed, the data mirroring.

Abstract: Systems and methods for redundancy management in fault tolerant computing are provided. The systems and methods generally relate to enabling the use of non-custom, off-the-shelf components and tools to provide redundant fault tolerant computing. The various embodiments described herein, generally speaking, use a decrementer register in a general purpose processor for synchronizing identical operations across redundant general purpose processors, execute redundancy management services in the kernels of commercial off-the-shelf real-time operating systems (RTOS) running on the general purpose processors, and use soft coded tables to schedule operations and assign redundancy management parameters across the general purpose processors.

Abstract: A failsafe recovery capability for a Coordinated Timing Network. The recovery capability facilitates recovery when communication is lost between two servers of the coordinated timing network. The capability includes checking another system's status in order to determine what action is to be taken. The status includes the stratum level of the servers and a version number indicating the code level of the servers.

Abstract: An automotive system has a primary control module, such as an engine control module (ECM) configured for connection to a malfunction indicator lamp (MIL), and a secondary control module, such as a transmission control module (TCM), each in communication with each other over a bus. Each control module includes a respective diagnostic data status record. Each record includes a pending fault field, a confirmed fault field and an MIL control status field. An improved method for synchronizing the diagnostic data contained in the respective status records includes an extended status signal set that is used to communicate over the bus. The set includes a diagnostic testing complete signal, a fault present signal and a MIL request signal indicative of a request to illuminate the MIL. Logic in the receiving control module (ECM) interprets the extended status signal set to properly synchronize its diagnostic data status record with the TCM's, including both pending and confirmed faults.

Abstract: A very coarse quantization exceeding the measure determined by the masking threshold without or only very little quality losses is enabled by quantizing not immediately the prefiltered signal, but a prediction error obtained by forward-adaptive prediction of the prefiltered signal. Due to the forward adaptivity, the quantizing error has no negative effect on the prediction on the decoder side.

Abstract: An apparatus, a base station and user equipment are provided. The apparatus is configured to code a first given number of symbols from the beginning of a transmission period and/or a second given number of symbols from the end of the transmission period with a stronger error correcting code than the rest of the symbols in the transmission period.

Abstract: Considering both performance and cost of an iterative receiver, the present invention provides an iterative signal receiving method for a wireless communications system. The iterative signal receiving method includes utilizing a channel estimating (CE) process to perform channel estimation for a received signal according to first log-likelihood ratio (LLR) data to generate second LLR data, and then generating the first LLR data according to an error correction code (ECC) decoding process and the second LLR data. When the ECC decoding process is a convolutional decoding process, the CE process is a zero-forcing process, a minimum mean square error (MMSE) process or an interpolation-based process. When the ECC decoding process is a low density parity check code (LDPC) decoding process, the CE process is a maximum likelihood (ML) process or a maximum a posteriori (MAP) process.

Abstract: In a method for the serial, asynchronous and character-by-character data transmission of a data stream having multiple data words Z to Z, an additional parity data word D is generated and transmitted. The parity data word D is generated such that in a data block formed from the data words Z to Z and the additional parity word D a pre-determined parity is produced, wherein for calculating the parity different bit positions, and thus varying priorities are selected each in the data words adjacent to each other in the data stream. Further, the vertical parity is generated and transmitted for the parity data word, and for each data word Z to Z. The method substantially increases the probability that transmission errors of various origins are detected in a receiver.

Abstract: A system of determining unknown symbols of an error correcting code using the Discrete Fourier Transform (DFT) with arithmetic corresponding to the number field of the error correcting code, including complex numbers. Encoder and decoder configurations are described. Parallel generation of independent parity check equations, simultaneous solution of unknown symbols generating, or regenerating a codeword of the error correcting code.

Abstract: Systems and methods for protecting DSL systems against impulse noise are provided. Disclosed herein are example embodiments of a retransmission technique located above the gamma interface (i.e., in the network processing layer). Such a retransmission technique can be combined with standard RS coding with standard erasure-decoding & triangular interleaving at the PMS-TC layer. Example embodiments of the technique involve using the RS code to protect against REIN noise, and using ?-layer retransmission for protecting against error events not corrected by the RS code, e.g. a SHINE noise in the presence of REIN. Both techniques are used jointly in the case of combined REIN and SHINE noise.