Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: Switching is provided in a transducer array of medical diagnostic ultrasound imaging. The switching controls the formation of macro elements or aperture for scanning a plane or volume. The switches are implemented with one or more transistors. The control causes the gates of the transistor to float during the “on” connection. While on, the switch connects, allowing ultrasound signals to pass through the switch.

Abstract: A reconfigurable Wilkinson power divider, methods of manufacture and design structures are provided. The structure includes a first port, and a first arm and a second arm connected to the first port. The first arm and the second arm each include one or more tunable t-line circuits. The structure also includes a second port and a third port connected to the first port via the first arm and second arm, respectively.

Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

Abstract: The present invention provides a timing device, especially a timing device for use in mass spectrometers, for example TOF mass spectrometers, for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event, the timing device having: a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data, and wherein suitably the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data.

Abstract: Apparatus, computer readable medium, circuits, and method of reducing power in sending signals over two or more wires are disclosed. The method includes receiving two or more signals at a first end of the two or more wires. The method includes determining that the two or more signals should be encoded based at least on a previously received two or more signals. The method includes encoding the two or more signals. Additionally, the method includes sending the encoded two or more signals over the two or more wires. The method may include receiving the sent two or more signals at a second end of the two or more wires, and if the sent two or more signals were encoded, then decoding the two or more signals back to the values of the received two or more signals.

Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Abstract: An apparatus includes a capacitance-to-voltage converter circuit configured to be electrically coupled to a micro-electromechanical system (MEMS) sensor circuit. The capacitance-to-voltage converter circuit includes a differential chopping circuit path configured to receive a differential MEMS sensor output signal and invert a polarity of the differential chopping circuit path, and a differential sigma-delta analog to digital converter (ADC) circuit configured to sample the differential MEMS sensor output signal and provide a digital signal representative of a change in capacitance of the MEMS sensor.

Abstract: In a transmitter of an orthogonal frequency division multiple access (OFDMA) system, a subchannelization module generates an OFDMA symbol with data on multiple subcarriers, from received incoming data packets. An input controller applies a first formula to determine a first index of each received data packet, and stores each received data packet at an address in memory according to its first index. An output controller applies a second formula to determine the nature of the data to be carried by each subcarrier in the OFDMA symbol and, if said second formula indicates that a data subcarrier should be output, reads the data from said memory, wherein said data packets are stored in said memory at addresses such that the data can be read out at least piecewise sequentially when generating the OFDMA symbol.

Abstract: In a method for transmitting channel feedback data from a receiver to a transmitter, channel data for a plurality of orthogonal frequency division multiplexing (OFDM) tones for one or more spatial streams corresponding to a communication channel is determined. A plurality of angle values associated with the one or more spatial streams and one or more OFDM tones is determined. For each of the one or more spatial streams, a per-tone signal to noise ratio (PT-SNR) associated with one or more OFDM tones is determined, and an average signal to noise ratio (avg-SNR) is determined by averaging the signal to noise ratio (SNR) values. A feedback report is generated to include at least i) the plurality of angle values, ii) the PT-SNRs, and iii) the avg-SNR. The feedback report is included in a data unit to be transmitted from the receiver to the transmitter.

Abstract: A system can include a phase detector configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms.

Abstract: A signal averaging circuit includes a plurality of switched weighted current sources to generate a total amount of charge. The total amount of charge is representative of a weighted sum of a plurality of input signal samples during an active period of a read enable signal. A timing control signal generator is coupled to receive an input signal and the read enable signal and sequentially switch the plurality of switched weighted current sources to adjust the total amount of charge in response to the input signal during the active period of the read enable signal. A storage circuit is coupled to the plurality of switched weighted current sources to convert the total amount of charge into a voltage representative of an output signal.

Abstract: A user equipment (UE) performs a transform domain (DFT) based method to detect the cyclic prefix (CP) length that is being used by a base station for cellular communications. The detected CP length is then used to reduce the amount of time required to complete the synchronization and cell search procedures. In particular, the UE uses the detected CP length information to obtain Cell Identification parameters (NID1, NID2) along with information including a Maximum energy Tap location and a reference signal receive power (RSRP) while completing the synchronization and cell search procedures.

Abstract: A system and method for receiving a plurality of pilot tones, generating an analytic signal in a frequency domain, the analytic signal including frequency components that when converted to a time domain include a preamble having a first half containing only non-zero data and a second half containing only zero data, converting the analytic signal from the frequency domain to the time domain, resulting in the preamble having the first half containing only non-zero data and the second half containing only zero data, generating a cyclic prefix based on the second half of the preamble, and attaching the cyclic prefix to the preamble to form a pilot signal, the cyclic prefix including only zero data.

Abstract: A radio frequency (RF) generation module includes a power control module that receives first and second desired amplitudes of an output of the RF generation module in first and second respective states, and that outputs, based on the first and second desired amplitudes, input power setpoints corresponding to a transition from the first state to the second state. A frequency control module receives the input power setpoints and outputs frequency setpoints corresponding to the input power setpoints. A pulse shaping module receives the input power setpoints, the frequency setpoints, and an indication of when to transition from the first state to the second state, and transitions the output of the RF generation module from the first state to the second state based on the input power setpoints, the frequency setpoints, and the indication.

Abstract: A device includes a first hybrid, where a first input of the first hybrid is coupled to an output of a first amplifier configured to receive a first input signal. A first input of a second hybrid is coupled to an output of a second amplifier configured to receive a second input signal. The device includes a first phase shifter configured to receive the first input signal and a second phase shifter configured to receive the second input signal. An output of the first phase shifter is coupled to an input of a third amplifier, and an output of the third amplifier is coupled to a second input of the second hybrid. An output of the second phase shifter is coupled to an input of a fourth amplifier, and an output of the fourth amplifier is coupled to a second input of the first hybrid.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value xt—k and transfer the input signal to the second delay unit. The second delay unit includes a converter and a second shift register. The converter is connected to the second shift register by n leads. The value xt—k and a value xt—k?1 are present at the converter, where xt—k?1 is the input signal delayed by k?1 cycles of the first clock signal, The converter is configured such that the value xt—k?1 is present on leads 1 to m and the value xt—k is present on leads m+1 to n. The second shift register is configured to successively output values present on leads 1 to n.

Abstract: A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit.

Abstract: The present invention discloses a circuit and a method for providing absolute information for floating grounded integrated circuit. The method includes: receiving an absolute information sense signal carrying absolute information; converting the absolute information sense signal to a current signal; and generating an internal reference signal according to the current signal, wherein the internal reference signal or a relationship between the internal reference signal and a floating ground level is related to the absolute information.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: A method for generating a signal is provided, the method including: providing a first signal having a first signal frequency; providing a second signal having a second signal frequency or a third signal frequency, wherein the second signal frequency is higher than the third signal frequency; switching the second signal having the second signal frequency to the third signal frequency based on a predefined first signal event of the first signal; and returning the second signal having the third signal frequency to the second signal frequency in response to a predefined second signal event.

Abstract: An apparatus includes a voltage source, voltage measurement means and a processing means, and connects to a line to apply and monitor a voltage between the line and earth. The processing means controls the voltage source to transmit and receive communications from the line, via the voltage measurement means. The apparatus also has a first and second current measurement means. The voltage source is connectable to a wire under test to inject a predetermined test voltage on the wire. The wire extends in a first and second direction from the test location. The first current measurement means measures the leakage current from the voltage source flowing along the wire in a first direction, and the second current measurement means determines the leakage current along the wire in a second direction, and the processing means uses the current flows measured by both current measurement means to determine wire insulation properties.

Abstract: A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal.

Abstract: Various embodiments provide a method for processing a stimulation signal. The method may include monitoring an output voltage on an electrode, the electrode being provided with the stimulation signal; determining whether the output voltage is lower than a threshold voltage; if it is determined that the output voltage is lower than the threshold voltage, modifying the waveform of the stimulation signal; and providing the modified stimulation signal to an object via the electrode.

Abstract: A laser source assembly (210) for generating an assembly output beam (212) includes a first laser source (218A), a second laser source (218B), and a dispersive beam combiner (222). The first laser source (218A) emits a first beam (220A) having a first center wavelength, and the second laser source (218B) emits a second beam (220B) having a second center wavelength that is different than the first center wavelength. The dispersive beam combiner (222) includes a common area 224 that combines the first beam (220A) and the second beam (220B) to provide the assembly output beam (212). The first beam (220A) impinges on the common area (224) at a first beam angle (226A), and the second beam (220B) impinges on the common area (224) at a second beam angle (226B) that is different than the first beam angle (226A). Further, the beams (220A) (220B) that exit from the dispersive beam combiner (222) are substantially coaxial, are fully overlapping, and are co-propagating.

Abstract: Techniques are disclosed to provide a reference signal via a switched capacitor filter for image detector arrays in accordance with one or more embodiments. For an example embodiment, a method of providing a sampled and filtered reference signal to an image detector array includes receiving a reference signal; sampling the reference signal with a first capacitor to store a sampled reference signal based on the reference signal; coupling a second capacitor to the first capacitor to share charge stored on the first and second capacitors to generate the sampled and filtered reference signal to store on the second capacitor; and decoupling the second capacitor from the first capacitor, wherein the sampled and filtered reference signal is stored on the second capacitor to provide for one or more image detectors within the image detector array.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: A method and an apparatus to drive an analog signal into a sensory tissue. The apparatus includes an analog-to-digital converter converting an original analog signal to a digital signal at an analog-to-digital converter sample rate. The apparatus includes a digital transceiver communicating wirelessly with the analog-to-digital converter to receive the digital signal. The apparatus includes a digital data buffer receiving the digital signal from the digital transceiver. The apparatus includes a digital-to-analog converter communicating with the digital data buffer and converting the digital signal into a reconstructed analog signal at a digital-to-analog converter sample rate faster than the analog-to-digital converter sample rate, the analog signal comprising a plurality of intensity values. The apparatus includes a pixel clock matching the digital-to-analog converter sample rate. The apparatus includes a bio-interface array comprising a plurality of electrodes and operably proximate to the sensory tissue.

Abstract: A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load impedance, an energy-storing element being connected to the second terminal of the load impedance and providing an output signal, and a measuring unit that measures the output signal or compares the output signal with a reference.

Abstract: The present invention provides a timing device, especially a timing device for use in mass spectrometers, for example TOF mass spectrometers, for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event, the timing device having: a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data, and wherein suitably the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data.

Abstract: A protection circuit includes a digital-to-analog (D/A) converter unit, a comparison unit and a processing unit. The D/A converter unit outputs an analog reference signal. The comparison unit compares a sensing signal with the analog reference signal and outputs a comparison signal when a level of the sensing signal is higher than or equal to a level of the analog reference signal. The processing unit receives the comparison signal to output an interrupt signal for temporarily deactivating a control circuit. When the control circuit is activated by an enable signal after being temporarily deactivated, the processing unit outputs a level modulation signal to the D/A converter unit, and the D/A converter unit modifies the outputted analog reference signal according to the level modulation signal. A method for protecting an electrical apparatus is also provided herein.

Abstract: An AC electric motor, an inverter and a controller are mounted on an electric powered vehicle. The controller includes a voltage deviation calculating unit, a modulation factor calculating unit, and a mode switching determination unit. The voltage deviation calculating unit calculates a voltage deviation between a first voltage command when the rectangular wave voltage control is executed and a second voltage command when pulse width modulation control is executed, by inputting a current deviation to a voltage equation of the AC electric motor. Modulation factor calculating unit calculates the modulation factor based on the first voltage command and the voltage deviation. The mode switching determination unit determines whether or not control mode of the AC electric motor from the rectangular wave voltage control to the pulse width modulation control is necessary, based on the modulation factor.

Abstract: The present invention is directed to systems and methods for monitoring characteristics of a subject. A system according to an exemplary embodiment of the invention includes a sensor subsystem including at least one respiratory sensor disposed proximate to the subject and configured to detect a respiratory characteristic of the subject, wherein the sensor subsystem is configured to generate and transmit at least one respiratory signal representing the respiratory characteristic, and at least one physiological sensor disposed proximate to the subject and configured to detect a physiological characteristic of the subject, wherein the sensor subsystem is configured to generate and transmit at least one physiological signal representing the physiological characteristic, and a processor subsystem in communication with the sensor subsystem, the processor subsystem being configured to receive at least one of the at least one respiratory signal and the at least one physiological signal.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal.

Abstract: A clock source generates a first clock signal for clocking a first clocked module and a rate adapting module produces an operation dependent clock signal from the first clock signal for clocking a second clocked module that is rate dependent. The first clock signal has a rate such that frequency dependent noise components associated with the first clock signal are outside a given frequency range that causes adverse performance in the first clocked module.

Abstract: An image sensor includes: a plurality of image pixels providing a reset signal and a data signal; a signal providing apparatus generating a ramp signal, and sequentially providing the reset signal, the data signal, and the ramp signal; and an analog-to-digital converting apparatus converting the data signal into a digital signal by using a first timing at which the amplitude of the ramp signal is changed based on the amplitude of the reset signal and a second timing at which the amplitude of the ramp signal is changed based on the amplitude of the data signal, wherein the reset signal used to generate the ramp signal and the data signal which has been converted into the data digital signal may be output from the same image pixel.

Abstract: A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract: A single ended to a differential signal converter. The single ended signal is passed through a high pass filter to block DC components. A positive and a negative version of the filtered signal are used collectively as the differential output of the converter. To allow accurate measurements on the input signal without waiting for the output of the high pass filter to settle, the differential outputs are offset by a dynamically generated signal representative of the midpoint of the filtered signal. That offset is generated by capturing a value representing the midpoint when a signal is first applied. This captured value is allowed to change with a time constant matching a time constant of the high pass filter. The converter may be used to connect a test instrument to a unit under test that generates test signals in a format that the test instrument is not specifically configured to measure.

Abstract: Aspects of a method and system for an integrated LC resonant current gain boosting amplifier may include amplifying within a chip, via an on-chip LC current gain circuit, an alternating current (AC) generated by an on-chip voltage-to-current converter, and converting within the chip, via an on-chip current-to-voltage circuit; the amplified alternating current to an output voltage. The on-chip LC current gain circuit comprises only passive components, which may include one or more resistors, one or more capacitors, and one or more inductors.

Abstract: A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT) variation, as well as other sources of variation, occur over time. Multiplexing techniques are utilized within each transmission lane to allow programmably adaptive use of phase alignment circuitry for various modes of operation. As a result, power consumption and semiconductor die area are reduced because multiple copies of phase alignment circuitry within each transmission lane are not required. Also, injection of additional jitter on the serial outputs due to continuous operation of phase alignment circuitry is prevented. Rather, multiplexers within the phase alignment circuitry selectively adapt the timing architecture to that required by the selected mode of operation.

Abstract: Apparatus and methods are provided for calibrating and operating a receiver circuit. An exemplary method comprises the steps of applying a first voltage offset to a first input of an amplifier circuit, generating an output signal at an output of the amplifier circuit based on the first voltage offset and a second voltage offset at a second input of the amplifier circuit, adjusting the second voltage offset based on the output signal, and maintaining the second voltage offset at a constant voltage when the output signal is indicative of the second voltage offset cancelling the first voltage offset.

Abstract: An electronic integrated-circuit device is described in which mode control commands are stored. Mode parameters are also stored in the device. One or more inputs are used according to a predetermined process as determined by the stored parameters according to the stored commands and current mode. One or more output signals are produced. In various applications an output signal may be input to a sound amplifier, a lamp, a motor, a servo, etc. One application is a variety of sensor fusion. Procedural programming is avoided. The device operates with more speed and flexibility than other available configurations. Higher level supervisory management and control is useful for setup and initialization and is optional during operation. Selected platforms include microcontrollers; field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs).

Abstract: An electronic load for a semiconductor element is provided. The electronic load includes at least two slope generating circuits, each of which generates a current according to a current for the electronic load corresponding to an output voltage of a power supply. Each slope generating circuit comprises at least a first slope generating circuit that simulates a first slope when the output voltage of the power supply is between 0V to a rated voltage, and a second slope generating circuit that simulates a second slope when the output voltage of the power supply is higher than the conducting state voltage of the semiconductor element by subtracting the forward bias voltage from the output voltage of the power supply.

Abstract: A reconfigurable semiconductor device is disclosed. The semiconductor device includes a substrate, a first insulating material formed on the substrate, two channels having different polarities, a plurality of terminal electrodes formed on the insulating material and coupled in common with the channels at their opposite ends, a second insulating material formed on the terminal electrodes, and a control gate formed on the second insulating material. The channels have different polarity and a charge storage layer is formed inside the second insulating material. The control gate is applied with a forward bias or a reverse bias and then the bias is cut off. The voltage-current characteristics of the semiconductor device are changed according to an electrical charge created in the charge storage layer.

Abstract: Disclosed herein are an inverter and an antenna circuit. The inverter that receives control signals, inverts the control signals including a first control signal, a second control signal, and a third control signal, and outputs the inverted control signals, includes: a first MOS transistor having a gate to which a first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which a third control signal is applied and a source to which a second control signal is applied; and a third MOS transistor having a gate to which a second control signal is applied and a source to which a third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.