Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Abstract: A solid state imaging device includes: an AD conversion section having a comparing section, which receives a reference signal from a predetermined reference signal generating section and which compares the reference signal with an analog signal to be processed, and a counter section, which receives a count clock for AD conversion and performs a count operation on the basis of a comparison result of the comparing section, and acquiring digital data of the signal on the basis of output data of the counter section; a count operation period control section controlling an operation period of the counter section on the basis of the comparison result; and a driving control section controlling the reference signal generating section and the AD conversion section such that for the signal to be processed, data of upper N?M bits is acquired in first processing and data of lower M bits is acquired in second processing.

Abstract: A single-to-differential conversion circuit includes a first transistor, a second transistor, and a transforming unit. Each of the first and second transistors has first, second and third terminals. The trans forming unit has first, second, and third induction elements. The first induction element has a first inductive terminal coupled to the second terminal of the first transistor, and a second inductive terminal coupled to a voltage source. The second induction element has a first inductive terminal to be coupled to the voltage source, and a second inductive terminal coupled to the second terminal of the second transistor. The third induction element has a first inductive terminal coupled to the first terminals of the first and second transistors, and a second inductive terminal coupled to ground. The third induction element electrically couples to the first and the second induction elements according to first and second coupling parameters, respectively.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: A method of processing a signal is disclosed.

Abstract: The present invention relates to a device for generating a signal and method for controlling operation of the same. The present invention provides a device for generating a signal, which includes an electrode, if connected to an external power source, supplied with a voltage from the external power source, a signal generating unit having a plurality of terminals, the signal generating unit deciding whether to operate the device according to a size of a voltage applied to a first terminal among a plurality of the terminals, the signal generating unit outputting a prescribed signal according to the decision, and a control circuit, if the electrode is connected to a plurality of the terminals, controlling a voltage applied to a plurality of the terminals. Accordingly, the present invention is able to control whether to operate a signal generating device using an external power source.

Abstract: Data comprising a pulse signal is divided into predetermined data segments. The number of pulse-signal fluctuations in the data segment is counted. A transmitter transmits the unchanged data to a receiving portion in a case where the number of pulse-signal fluctuations does not exceed a predetermined number. On the other hand, in a case where the number of pulse-signal fluctuations exceeds the predetermined number, the pulse signal is converted so as to be unchanged at the fluctuation of the pulse signal but to be fluctuated when the pulse signal does not fluctuate. Then, the transmitter transmits the converted pulse signal to the receiving portion wherein only the converted pulse signal is converted to the original pulse signal.

Abstract: An integrated circuit device includes: a high-speed serial interface circuit including a receiver circuit that receives a differential signal through a serial bus; a first terminal into which a first signal included in the differential signal is inputted; a second terminal into which a second signal included in the differential signal is inputted; a receiver circuit power supply terminal to which a power supply voltage applied to a high-voltage side of the receiver circuit is supplied; a first terminating resistor provided between the first terminal and a first node; a second terminating resistor provided between the second terminal and a second node; and a switching element provided between the first and the second nodes. In the device, the switching element is turned on in a high-speed serial interface mode and is turned off in a parallel interface mode by using the power supply from the receiver circuit power supply terminal.

Abstract: A semiconductor device includes an element coupled between a first power supply line and a second power supply line, and a capacitor coupled between the first power supply line and the second power supply line. A capacitance value of the capacitor is estimated based on a first value that depends on a period of a change in an input signal input to the element and a change in an output signal output from the element, and a second value that depends on a voltage between the first power supply line and the second power supply line.

Abstract: An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep the ISI jitter components from an initial amount of ISI, for example, zero ISI, and continually increment the amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: An apparatus for generating a monocycle comprises an input signal source (76) for providing an input signal, and a step recovery diode (SRD) (80) for receiving the input signal and producing an impulse. A shunt inductor (102) is provided to act as a first differentiator and a capacitor (92) connected in series to the output of the step recovery diode acts as a second differentiator. The first and second differentiators are arranged to double differentiate the impulse to produce a monocycle.

Abstract: A digitalized sensor system includes a portable electronic device, a sensor unit, a transmission unit and a signal converting unit. The portable electronic device has a first connection portion. The sensor unit is configured for measuring and/or monitoring physical and/or chemical parameters of a target object to generate a digital signal. The transmission unit includes a connecting wire and a second connection portion, the connecting wire adapted to be connected with the sensor unit and the second connection portion, the second connection portion adapted to connect to the first connection portion, and the second connection portion and the first connection portion forming a pluggable interface. The signal converting unit is configured on the transmission unit and adapted for converting the digital signal into a second signal, the second signal adapted to be transmitted to the portable electronic device by the transmission unit.

Abstract: Oscillators and methods of operating the oscillators are provided, the oscillators include an oscillating unit including at least one magnetic layer having a magnetization direction that varies according to at least one selected from the group consisting of an applied current, an applied voltage and an applied magnetic field. The oscillating unit is configured to generate an oscillation signal having a set frequency. The oscillators further include an output stage that provides an output signal by differentially amplifying the oscillation signal.

Abstract: An electronic device and a telecommunication device that are locally connected and methods of utilizing those devices are described herein. The electronic device detects a pattern or duration of user interactions with a multidirectional control of the electronic device. Based on the pattern or duration and association data mapping patterns or durations to commands, the electronic device selects a command and then transmits the command to the telecommunication device. The telecommunication device enables a user to associate actions to be performed by the telecommunication device with patterns or durations of user interaction with the multidirectional control. Also, the telecommunication device receives a signal from the electronic device that is recognized as a command to perform an action, the recognition being based on association data mapping the signal to a pattern or duration of user interaction. The telecommunication device then performs the action.

Abstract: An electronic load for a semiconductor element is provided. The electronic load includes at least two slope generating circuits, each of which generates a current according to a current for the electronic load corresponding to an output voltage of a power supply. Each slope generating circuit comprises at least a first slope generating circuit that simulates a first slope when the output voltage of the power supply is between 0V to a rated voltage, and a second slope generating circuit that simulates a second slope when the output voltage of the power supply is higher than the conducting state voltage of the semiconductor element by subtracting the forward bias voltage from the output voltage of the power supply.

Abstract: There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform.

Abstract: A waveform shaping device shapes a waveform of an externally input signal and outputs the input signal with the shaped waveform as an output signal to an equalizer for compensating a distortion of a signal, and includes a nonlinear process section for generating a nonlinear process signal (i) in which positive and negative signs of a low-frequency-free signal obtained by removing at least a direct current component from frequency components of the externally input signal are retained and (ii) which broadly monotonically increases nonlinearly with respect to the low-frequency-free signal when values of the low-frequency-free signal are at least in the vicinity of 0, the nonlinear process signal being added to the low-frequency-free signal so as to generate the input signal.

Abstract: A first auxiliary switch circuit is connected to one terminal and a first terminal of a main switch circuit and generates a first auxiliary detection current. A second auxiliary switch circuit is connected to the other terminal and a second terminal of the main switch circuit and generates a second auxiliary detection current. A current adjustment detection circuit adjusts the first auxiliary detection current so that the potentials of the other terminal and the first terminal are equal and passes the first auxiliary detection current in a direction of receiving the current from the first auxiliary switch circuit and adjusts the second auxiliary detection current so that the potentials of the one terminal and the second terminal are equal and passes the second auxiliary detection current in a direction of outputting the current to the second auxiliary switch circuit, thereby generating a detection current being proportional to the output current.

Abstract: A system and a method for exchanging communication data between devices using a bi-directional communication channel are disclosed. A combiner is coupled to a source device via first bi-directional configuration channel and to a sink device via a second bi-directional configuration channel. Upon receiving data from the first bi-directional configuration channel and not receiving data from the second bi-directional configuration channel, the combiner transmits the received data to the sink device using the second bi-directional configuration channel and prevents data transmission from the sink device to the source device using the second bi-directional configuration channel.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Methods and apparatus are disclosed for estimating inter-cell interference levels for resource elements of a received Orthogonal Frequency-Division Multiplexing (OFDM) signal. In an exemplary method in a wireless receiver, a reference symbol interference levels is measured for each of a plurality of reference symbols in a received OFDM signal, and interference scaling factors are mapped to each of a plurality of resource elements of the received OFDM signal. Each interference scaling factor reflects the probability that the corresponding resource element or group of resource elements is subject to interference from an interfering OFDM signal. Interference levels for each of the resource elements are then estimated as a function of the measured reference symbol interference levels and the interference scaling factors.

Abstract: A circuit is disclosed for a power supply unit for generating a DC voltage, the power supply unit having a current transformer, a rectifier, a series circuit including a first blocking diode and a charging capacitor, an electronic switch which is in parallel with the current transformer, a comparator, a voltage reference circuit for the comparator. In at least one embodiment, the circuit includes a circuit for monitoring the voltage across the charging capacitor. The comparator is used to control the electronic switch on the basis of the voltage across the charging capacitor in relation to the voltage which is generated by the voltage reference circuit and is applied to the comparator. In at least one embodiment, provision is made of a tap which is located between the rectifier and the first blocking diode and at which the circuit for monitoring the voltage across the charging capacitor is located. The circuit is in the form of an RC combination having a second blocking diode connected in series.

Abstract: An electronic integrated-circuit device is described in which mode control commands are stored. Mode parameters are also stored in the device. One or more inputs are used according to a predetermined process as determined by the stored parameters according to the stored commands and current mode. One or more output signals are produced. In various applications an output signal may be input to a sound amplifier, a lamp, a motor, a servo, etc. One application is a variety of sensor fusion. Procedural programming is avoided. The device operates with more speed and flexibility than other available configurations. Higher level supervisory management and control is useful for setup and initialization and is optional during operation. Selected platforms include microcontrollers; field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs).

Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: A lamp with power supply detection includes a power supply unit, a control module and a lighting module. The power supply unit provides a direct current (DC) voltage. The control module is coupled to the power supply unit, receives and stores the DC power, and generates a control signal according to whether the DC power is terminated or regained. The lighting module is coupled to the power supply unit and the control module, receives the DC power and adjusts brightness of the lighting module according to the control signal.

Abstract: A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit.

Abstract: Provided is an input apparatus including an input operation section, a capacitive sensor, and an output section. The input operation section includes an operation member configured to mechanically receive an input operation, and a first detection circuit configured to detect the input operation of the operation member. The capacitive sensor includes a plurality of electrodes which are arranged around the operation member, and each of which has a capacitance variable due to an approaching of a detection target, and a second detection circuit configured to detect the capacitance of each of the plurality of electrodes. The output section is configured to output an output of the first detection circuit and an output of the second detection circuit.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.

Abstract: An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.

Abstract: A control circuit and a conversion circuit. The control circuit may be configured to generate an analog control signal in response to a digital control signal. The conversion circuit may be configured to generate a capacitance signal in response to the analog control signal.

Abstract: An embodiment of regulation and shaping circuit includes a first input terminal for receiving a first input signal with a first frequency; a second input terminal for receiving a second input signal with a second frequency higher than the first frequency; a first circuital branch coupled to the first input terminal and, through first coupling means active at the first frequency, to an output terminal for providing an output signal; a second circuital branch coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop adapted to control the output signal according to the second input signal.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minimal skip ordered set based on the skip ordered set in the data stream received by the data buffer. Each of the minimal skip ordered sets has a same number of symbols. Additionally, each buffer stores data of the data stream received by the data buffer. The receiver aligns the data among the data buffers based on the minimal skip ordered sets in the data buffers and outputs the aligned data. In this way, the receiver deskews the data in the data streams.

Abstract: The invention relates to radioelectronic engineering, in particular to AC signal converters, and can be used as an autonomous AC voltage electrical power supply source and for other purposes. The proposed AC signal converter remains functional when one or more or all but one of the DC voltage sources fails and makes it possible to increase, to an unlimited degree, the output power thereof on account of an increase in the quantity of AC signal amplification and conversion stages and DC voltage sources. Furthermore, a square-wave AC input signal is converted into a signal of, or close to, any set shape (sinusoidal, saw-tooth etc.) at the amplification and conversion stages, at an output matching element, at the output of the amplification and conversion stages, at the output of the output matching element (transformer) or output matching elements (transformers), and, for loading the proposed AC signal converter, an AC signal which is optimal for this load is supplied.

Abstract: A time-to-amplitude component having an integrated designed configured to measure a time difference between a start signal and a stop signal includes a first time-to-amplitude converter having a delay chain, a resistor network, a capacitor configured to be chargeable via the resistor network, and a respective driver. The component further includes a control device and a stabilizing device including a control circuit for generating a regulated control voltage. The first time-to-amplitude converter is configured so that the delay elements of the first time-to-amplitude converter are configured to be controlled by the regulated control voltage, a run signal is transmitted through the delay chain, and the capacitor is continuously charged via the resistor network, and the resistor network is electrically separated from the delay chain via the respective drivers so as to terminate a charging of the capacitor, and the analog voltage signal is measurable at an output of the capacitor.

Abstract: An onion waveform generator and a spread spectrum clock generator (SSCG) using the same are provided. The onion waveform generator includes a value generation unit and an accumulating unit. The value generation unit outputs a counting value. The accumulating unit accumulates the counting value to output a waveform value. The accumulating unit switches from an increasing mode to a decreasing mode if the waveform value is a third boundary value, and the accumulating unit switches from the decreasing mode to the increasing mode if the waveform value is a fourth boundary value.

Abstract: A waveform generation circuit includes: a waveform generation block configured to generate a waveform signal corresponding to a driving control signal; and a control signal generation block configured to generate a driving control signal for compensating the waveform signal for an environmental factor reflected into the waveform generation circuit.

Abstract: The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a multiplexer, at least two channels and at least two output pads. The channels are connected to the output pads via the multiplexer. The source driver is powered by a first supply voltage from the power supply. The two output pads are connected via a charge sharing switch. The method comprises the following steps. First, determine whether the first supply voltage is insufficient, and if yes, perform the following steps. Turn off the charge sharing switch. Then, disconnect the channels from the output pads by the multiplexer.

Abstract: Provided is a signal output circuit that outputs a signal, comprising an output circuit that changes a characteristic of a signal output therefrom according to a change in power supply voltage supplied thereto and a control signal supplied thereto; and a control section that changes the control signal to compensate for a change in the characteristic due to a change in the power supply voltage.

Abstract: A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is a time-shifted version of the first intermediate signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. An anticipated differential change in the output signal is determined, the anticipated differential change to occur based upon a transition in the first reference signal. A realized differential change in the output signal is measured, the realized differential change occurring based upon a transition in the first reference signal. The realized differential change in the output signal is compared to the anticipated differential change in the output signal to determine a nonlinearity indicator.

Abstract: A signal processing system distributes an input signal over a plurality of shaped signal distribution structures that are interconnected with a plurality of shaped signal pickup units. The signal distribution structures and/or the signal pickup units include delay lines. The shape of the signal distribution structures and the shape of the signal pickup units and the configuration of the interconnections between the shaped structures and the pickup units determine the type of analysis performed on the signals. The signal possessing is distributed across the shaped structures. Input information is diffracted or spread, such that statistical correlations can be found by reconverging the diffracted information. Signals propagated through the system can be a combination of analog, digital and pulse signals. Optionally, feedback is used to amplify or attenuate earlier stages, such that outputs or actions are based on the relative importance of the input signals.

Abstract: To equalize the intensity of light emitted by display elements on a display device, a plurality of current-drive circuits are connected in cascade through two terminals of each of the current-drive circuits, each comprising a reference current generation section including a reference resistor and a plurality of current drive sections. Reference current sunk by an external reference current source causes a voltage drop across the reference resistor, and the voltage drop is applied across a current adjustment resistor In response to an image signal, the current-drive circuit outputs current, determined by multiplying each of a plurality of internal reference currents by an optional factor and summing the resulting currents to the display elements. Since the magnitude of the internal reference current flowing inside the current-drive circuit can be varied by varying the value of the current adjustment resistor, gamma correction can be applied to drive current with high accuracy.

Abstract: An apparatus for modifying an output signal indicative of a downhole parameter that may include a carrier conveyable in a wellbore; a negative error compensator; and an output signal device. The negative error compensator may be configured to modify the output of the device to increase or decrease a characteristic of the output signal from the output signal device. Also, a method for modifying an output signal indicative of a downhole parameter that may include modifying a characteristic of an output signal produced by a output signal device in a wellbore using a negative error compensator.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.

Abstract: An exemplary control method includes a step of employing a look-up table to derive first waveform value data for a multi-phase reference waveform. The exemplary method also includes a step of deriving second waveform value data corresponding to modifier data for the multi-phase reference waveform. The modifier data is added into the reference waveform to produce a modified reference waveform. The exemplary method additionally includes a step of generating a plurality of control signals from the modified reference waveform and controlling one or more electronic devices based on the control signals.

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.