Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.

Abstract: Provided are methods and apparatuses for densifying a silicon carbide film using remote plasma treatment. Operations of remote plasma deposition and remote plasma treatment of the silicon carbide film alternatingly occur to control film density. A first thickness of silicon carbide film is deposited followed by a remote plasma treatment, and then a second thickness of silicon carbide film is deposited followed by another remote plasma treatment. The remote plasma treatment can flow radicals of source gas in a substantially low energy state, such as radicals of hydrogen in a ground state, towards silicon carbide film deposited on a substrate. The radicals of source gas in the substantially low energy state promote cross-linking and film densification in the silicon carbide film.

Abstract: A process for making a nanoduct includes: disposing an etchant catalyst on a semiconductor substrate including a single crystal structure; heating the semiconductor substrate to an etching temperature; introducing an oxidant; contacting the semiconductor substrate with the oxidant in a presence of the etchant catalyst; anisotropically etching the semiconductor substrate by the etchant catalyst in a presence of the oxidant in an etch direction that is coincident along a crystallographic axis of the semiconductor substrate; and forming the nanoduct as the etchant catalyst propagates along a surface of the semiconductor substrate during anisotropically etching the semiconductor substrate, the nanoduct being crystallographically aligned with the crystallographic axis of the semiconductor substrate.

Abstract: Methods for the formation of SiCN, SiCO and SiCON films comprising cyclical exposure of a substrate surface to a silicon-containing gas, a carbon-containing gas and a plasma. Some embodiments further comprise the addition of an oxidizing agent prior to at least the plasma exposure.

Abstract: Atomic layer deposition (ALD) processes for forming Te-containing thin films, such as Sb—Te, Ge—Te, Ge—Sb—Te, Bi—Te, and Zn—Te thin films are provided. ALD processes are also provided for forming Se-containing thin films, such as Sb—Se, Ge—Se, Ge—Sb—Se, Bi—Se, and Zn—Se thin films are also provided. Te and Se precursors of the formula (Te,Se)(SiR1R2R3)2 are preferably used, wherein R1, R2, and R3 are alkyl groups. Methods are also provided for synthesizing these Te and Se precursors. Methods are also provided for using the Te and Se thin films in phase change memory devices.

Abstract: A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

Abstract: In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first dielectric layer includes first openings. An epitaxial layer is grown on the semiconductor substrate by an epitaxial lateral overgrowth process. The first openings are filled by the epitaxial layer and the epitaxial layer is grown onto adjacent portions of the first dielectric layer so that part of the first dielectric layer is uncovered by the epitaxial layer and a gap forms between opposing sidewalls of the epitaxial layer over the part of the first dielectric layer that is uncovered by the epitaxial layer. The gap defines a first trench in the epitaxial layer that extends to the first dielectric layer.

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have a sigma-shaped boundary. In another embodiment, the substrate and the first semiconductor region have U-shaped boundary.

Abstract: A method for forming an interconnect structure is provided. The method includes providing a substrate with a surface; and forming a metal layer covering the surface of the substrate and with a desired grain size to reduce grain boundary scattering of the interconnect structure subsequently formed with the metal layer. The method also includes etching the metal layer to form a plurality of metal lines on the surface of the substrate and a plurality of metal pillars on each of the plurality of the metal lines of the interconnect structure; and forming a dielectric layer covering the surface of the substrate, surfaces of the metal lines, and side surfaces of the metal pillars.

Abstract: A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.

Abstract: A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, ??, varies in a substrate. The method focuses in on the difference in ?? with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in ?? with a smaller length scale (high frequency) and corrects only the difference in ?? with a greater length scale. The distribution of the difference in ?? in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in ?? with a low frequency and the difference in ?? between before and after correction, thereby revealing a part that requires correction.

Abstract: A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of times.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a structure in which first to N-th insulating layers and first to N-th metal layers are alternately provided on a substrate where N is an integer of two or more. The method further includes processing the first insulating layer. The method further includes forming a first film on a side face of the first insulating layer, the first film containing a first reaction product generated by processing the first insulating layer. The method further includes processing the first metal layer under the first insulating layer, and the second insulating layer under the first metal layer by using the first film as a mask.

Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a lower trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.

Abstract: A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench.

Abstract: Methods of fabricating micro- and nanostructures comprise top-down etching of lithographically patterned GaN layer to form an array of micro- or nanopillar structures, followed by selective growth of GaN shells over the pillar structures via selective epitaxy. Also provided are methods of forming micro- and nanodisk structures and microstructures formed from thereby.

Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.

Abstract: A pillar-shaped semiconductor memory device includes a silicon pillar, and a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, and a first conductor layer, which surround an outer periphery of the silicon pillar in that order, and a second interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer. A side surface of the second interlayer insulating layer facing a side surface of the first interlayer insulating layer is separated from the side surface of the first interlayer insulating layer with a distance therebetween, the distance being larger than a distance from the side surface of the first interlayer insulating layer to a side surface of the first conductor layer facing the side surface of the first interlayer insulating layer.

Abstract: The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that this later to be filled with SiGe material. The shape cavity comprises convex regions interfacing the substrate. There are other embodiments as well.

Abstract: In a method of manufacturing a semiconductor device, a plasma annealing and supplying a threshold voltage control gas onto a portion of a substrate is performed to form a fixed charge region including a fixed charge at a surface of the substrate. A MOS transistor is formed on the substrate including the fixed charge region. By the above processes, the threshold voltage of the MOS transistor may be easily controlled.

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of times, wherein the cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber; exhausting the precursor gas in the process chamber through an exhaust system; confining a reaction gas, which differs in chemical structure from the precursor gas, in the process chamber by supplying the reaction gas to the substrate in the process chamber while the exhaust system is closed; and exhausting the reaction gas in the process chamber through the exhaust system while the exhaust system is opened.

Abstract: A pillar-shaped semiconductor memory device includes an i-layer substrate, a silicon pillar, a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, a second interlayer insulating layer, and word-line conductor layers separated by third interlayer insulating layers. The tunnel insulating layer, the data charge storage insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer are formed so as to surround an outer peripheral portion of a side surface of the silicon pillar. The word-line conductor layers and the third interlayer insulating layers are formed so as to surround an outer peripheral portion of a side surface of the second interlayer insulating layer in a direction perpendicular to a surface of the i-layer substrate.

Abstract: A process of fabricating a nanostructure is disclosed. The process is effected by growing the nanostructure in situ within a trench formed in a substrate and having therein a metal catalyst selected for catalyzing the nanostructure growth, under the conditions in which the growth is guided by the trench. Also disclosed are nanostructure systems comprising a nanostructure, devices containing such systems and uses thereof.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a stack of alternate conductive layers and insulating layers, an opening, an oxide layer and a conductor. The stack is formed on the substrate. The opening penetrates through the stack. The oxide layer is formed on a sidewall of the opening. The conductor is filled into the opening. The conductor is separated from the sidewall of the opening by only the oxide layer.

Abstract: The invention relates to a post-activation method of dopants in a doped and activated GaN-base semiconductor layer, including the following successive steps: providing said doped and activated substrate, eliminating a part of the semiconductor material layer.

Abstract: In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating layer. A gate structure is formed over the first and second fin structures, each of which has source/drain regions, having a first width, outside of the gate structure. Portions of sidewalls of the source/drain regions are removed to form trimmed source/drain regions, each of which has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions such that the strain material formed on the first fin structure is separated from that on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material such that the contact layer wraps around the strain material.

Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

Abstract: A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench.

Abstract: A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.

Abstract: Carry out a vapor etching step of cleaning an inside of a chamber of a vapor phase growth apparatus by vapor etching using HCl gas (S1). Carry out an annealing step of sequentially annealing a predetermined number of silicon wafers, one by one, in a non-oxidizing atmosphere (S2, S3). Repeat the vapor etching step and the annealing step a prescribed number of times. After having carried out the vapor etching step and the annealing step the prescribed number of times (S4: Yes), collect contaminants on the surface of each of the wafers, and measure the Mo concentration using ICP-MS (S5). Evaluate the cleanliness of the vapor phase growth apparatus on the basis of each Mo concentration value and the relationship between the Mo concentrations (S6). Thus, provided is a method with which it is possible to measure, with high sensitivity, the contamination amount of a vapor phase growth apparatus.

Abstract: A method of manufacturing a semiconductor device including: a process of transferring a substrate into a processing chamber; a first gas supplying process of supplying a B atom-containing gas into the processing chamber; a first purging process of purging an inside of the processing chamber under an atmosphere of the B atom-containing gas supplied in the first gas supplying process; a second gas supplying process of supplying an Si atom-containing gas into the processing chamber to form a non-doped Si film on the substrate, after the first purging process; and a second purging process of purging the inside of the processing chamber under an atmosphere of the Si atom-containing gas.

Abstract: Systems and methods for providing a hybrid integrated nanostructure and nanotube substrate system are disclosed. The system includes a substrate having a plurality of nanostructures formed thereon. Interconnected to the substrate, directly or through nanostructures, are nanotubes. The nanostructures can extend for a greater distance from the surface of the substrate than the nanotubes, providing a robust structure. In addition, the structure can be highly emissive and absorptive hybrid surface.

Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.

Abstract: A method of fabricating a variable resistance memory device includes preparing a substrate having a lower electrode, forming a mold layer on the substrate, patterning the mold layer to form an opening, forming a variable resistance layer having a first portion in the opening and a second portion disposed on a top surface of the mold layer, and separating the second portion of the variable resistance layer from the first portion by irradiating the variable resistance layer to form a variable resistance element in the opening.

Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.

Abstract: A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.

Abstract: The disclosure relates to a method of making a nano-pillar array on a substrate. A carbon nanotube composite structure is provided. The carbon nanotube composite structure defines a number of openings. The carbon nanotube composite structure is placed on the substrate. The substrate is dry etched to form a patterned surface by using the first surface using the carbon nanotube composite structure as a mask. The patterned surface includes a number of strip-shaped bulges crossed with each other. The carbon nanotube composite structure is removed. A photoresist layer is applied on the patterned surface. The photoresist layer is removed and some residual photoresist remains at intersections of the number of strip-shaped bulges. The substrate is further dry etched by using the residual photoresist as a mask.

Abstract: In a method of printing a transferable component, a stamp including an elastomeric post having three-dimensional relief features protruding from a surface thereof is pressed against a component on a donor substrate with a first pressure that is sufficient to mechanically deform the relief features and a region of the post between the relief features to contact the component over a first contact area. The stamp is retracted from the donor substrate such that the component is adhered to the stamp. The stamp including the component adhered thereto is pressed against a receiving substrate with a second pressure that is less than the first pressure to contact the component over a second contact area that is smaller than the first contact area. The stamp is then retracted from the receiving substrate to delaminate the component from the stamp and print the component onto the receiving substrate. Related apparatus and stamps are also discussed.

Abstract: A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.

Abstract: The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including AlxGa(1-x)N (0<x<1) and a quantum well layer including AlyGa(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 107 to 1010/cm2.

Abstract: A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

Abstract: There is provided a nitride semiconductor epitaxial substrate having a group III nitride semiconductor layer with C-plane as a surface, grown on a substrate via a buffer layer of the group III nitride semiconductor containing Al, wherein the buffer layer has an inversion domain on the surface.

Abstract: The present invention relates to fabrication and application of compositions, devices, methods and systems for utilizing radiation more efficiently as compared to known systems. A synthesis method provides deposition of titania on a substrate without the use of an electrochemical reaction. An integrated architecture formed by the method of the present invention is comprised of vertically-oriented, one-dimensional, monocrystalline, n-type anatase nanowires in communication with a common transparent conductive substrate, and which are intercalated with a consortia of p-type quantum dots tuned for absorption of infrared and other radiation.

Abstract: A method of manufacturing a semiconductor device can enhance controllability of the diameters of grains of a film containing a predetermined element such as a silicon film when the film is formed. The method includes (a) forming a seed layer containing a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including alternately performing supplying a first source gas containing the predetermined element, an alkyl group and a halogen group to the substrate and supplying a second source gas containing the predetermined element and an amino group to the substrate, or by performing supplying the first source gas to the substrate a predetermined number of times; and (b) forming a film containing the predetermined element on the seed layer by supplying a third source gas containing the predetermined element and free of the alkyl group to the substrate.

Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. The light emitting nanostructures are respectively disposed on the exposed regions of the base layer and include a plurality of nanocores having a first conductivity type semiconductor and having side surfaces provided as the same crystal planes. The light emitting nanostructures include an active layer and a second conductivity type semiconductor layer sequentially disposed on surfaces of the nanocores. Upper surfaces of the nanocores are provided as portions of upper surfaces of the light emitting nanostructures, and the upper surfaces of the light emitting nanostructures are substantially planar with each other.