Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: The present invention concerns a joining structure and a substrate-joining method using the same. The joining structure comprises a substrate, and comprises a plurality of joining patterns which are located on the said substrate and which are spaced apart from each other. The substrate-joining method using the joining structure can comprise: a stage involving the formation of a plurality of joining patterns which are spaced apart from each other on a first substrate; and a stage of joining a second substrate on the plurality of joining patterns. When the said joining structure is employed, it is possible to reduce or prevent damage due to spreading of the joining substance during joining of the two substrates.

Abstract: An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region.

Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.

Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.

Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Abstract: Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first c

Abstract: A method can be used for the production of a coated substrate. The coating contains copper. A copper precursor and a substrate are provided. The copper precursor is a copper(I) complex which contains no fluorine. A copper-containing layer is deposited by means of atomic layer deposition (ALD) at least on partial regions of the substrate surface by using the precursor. Optionally, a reduction step is performed in which a reducing agent acts on the substrate obtained in the layer deposition step. In various embodiments, the precursor is a complex of the formula L2Cu(X?X) in which L are identical or different ?-donor-? acceptor ligands and/or identical or different ?,?-donor-? acceptor ligands and X?X is a bidentate ligand which is selected from the group consisting of ?-diketonates, ?-ketoiminates, ?-diiminates, amidinates, carboxylates and thiocarboxylates.

Abstract: A process of forming a front-grid electrode on a silicon wafer having an ARC layer, comprising the steps: (1) printing and drying a metal paste A comprising an inorganic content comprising 0.5 to 8 wt.-% of glass frit and having fire-through capability, wherein the metal paste A is printed on the ARC layer in a grid pattern which comprises (i) thin parallel finger lines forming a bottom set of finger lines and (ii) busbars intersecting the finger lines at right angle, (2) printing and drying a metal paste B comprising an inorganic content comprising 0 to 3 wt.-% of glass frit over the bottom set of finger lines to form a top set of finger lines superimposing the bottom set of finger lines, and (3) firing the double-printed silicon wafer, wherein the inorganic content of metal paste B contains less glass frit plus optionally present other inorganic additives than the inorganic content of metal paste A.

Abstract: A process of forming a front-grid electrode on a silicon wafer having an ARC layer, comprising the steps: (1) printing and drying a metal paste A comprising an inorganic content comprising 0.5 to 8 wt.-% of glass frit and having fire-through capability, wherein the metal paste A is printed on the ARC layer to form a bottom set of thin parallel finger lines, (2) printing and drying a metal paste B comprising an inorganic content comprising 0.2 to 3 wt.-% of glass frit over the bottom set of finger lines, wherein the metal paste B is printed in a grid pattern which comprises (i) thin parallel finger lines forming a top set of finger lines superimposing the bottom set of finger lines and (ii) busbars intersecting the finger lines at right angle, and (3) firing the double-printed silicon wafer, wherein the inorganic content of metal paste B contains less glass frit plus optionally present other inorganic additives than the inorganic content of metal paste A.

Abstract: A semiconductor chip and an interposer are bonded by a conductive die bonding material. Between the semiconductor chip and the interposer, an application region in which the die bonding material resides and a region in which a sealing resin resides are provided. This allows adhesivity between the semiconductor chip and the interposer to be higher than that in conventional semiconductor packages, thereby causing no detachment at the adhesive interface. As a result, it becomes possible to improve electrical property and long-term reliability as compared to conventional semiconductor packages. Moreover, it is also possible to prevent the semiconductor chip from warping.

Abstract: Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.

Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a contact pad at a first main side of the first substrate; providing a second substrate with a main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.

Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.

Abstract: A micro-electro mechanical system (MEMS) is disclosed, which comprises a substrate; at least one transistor formed on the substrate and electrically connected with a contact plug; at least one MEMS device; and a local interconnection line at the same level of the contact plug, through which the MEMS device is coupled to the transistor.

Abstract: Gold wire for connecting a semiconductor chip basically containing praseodymium in 0.0004 mass % to 0.02 mass % in range and, considering the bonding characteristics, containing beryllium or aluminum or both in limited ranges and, considering the precipitates formed in the gold wire, further containing auxiliary additive elements of calcium, lanthanum, cerium, neodymium, and samarium in limited ranges.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: Various embodiments include interconnects for semiconductor structures that can include a first conductive structure, a second conductive structure and a non-hardening liquid conductive material in contact with the first and second structure. Other embodiments include semiconductor components and imager devices using the interconnects. Further embodiments include methods of forming a semiconductor structure and focusing methods for an imager device.

Abstract: The invention relates to a method for connecting two joining surfaces, particularly in the field of semiconductors, wherein at least one joining surface is produced by depositing a layer comprising 20 to 40% gold and 80 to 60% silver onto a substrate and selectively removing the silver from the deposited layer in order to produce a nanoporous gold layer as a joining surface. The joining surface with the nanoporous gold layer and an additional joining surface are disposed one above the other and pressed together.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: An integrated circuit (IC) package assembly includes a substrate and an IC. The substrate defines a plurality of vias. Inner walls of the plurality of vias and surfaces of the substrate are coated with copper. The plurality of vias are filled with an adhesive. The copper coated on surfaces of the substrate among the plurality of vias are etched. The IC is fixed on the substrate by cohesion between the adhesive and the etched surfaces of the substrate.

Abstract: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: There is a highly reliable semiconductor module having a satisfactory bonding strength in the electrical bonded portion. In the semiconductor module 10, a semiconductor chip 11 is mounted on a circuit board 20. In the circuit board 20, on an insulating ceramic substrate 21 is formed a metal circuit plate 22 on which the semiconductor chip 11 is implemented. The semiconductor chip 11 and metal circuit plate 22 are connected with each other by an aluminum bonding wire 23. In the connected portion between the metal circuit plate 22 and bonding wire 23, a coating layer 24 for excellent conjunction therebetween is mounted. The coating layer 24, as shown in an enlarged diagram, is made up of a nickel (Ni) layer 241, a P-distributed palladium (Pd) layer 242, and an Au layer 243 in increasing order. To the P-distributed Pd layer 242 is added P (phosphorous) and, the P concentration on the Ni layer 241 is higher than that on the Au layer side 243.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

Abstract: A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer.

Abstract: A semiconductor device includes a first semiconductor chip, an electrode pad formed in an upper surface portion of the first semiconductor chip, a second semiconductor chip formed on the first semiconductor chip, and a through-via formed in the second semiconductor chip. A hollowed portion is formed in the electrode pad, and a bottom portion of the through-via is embedded in the hollowed portion.

Abstract: A nonvolatile memory device, includes: a lower side electrode aligned in a first direction; an upper side electrode positioned above the lower side electrode and aligned in a second direction intersecting the first direction; and a memory unit provided between the lower side electrode and the upper side electrode. At least one selected from the lower side electrode and the upper side electrode includes a first electrode and a second electrode, the first electrode having a forward-tapered side wall, the second electrode having a reverse-tapered side wall and being adjacent to the first electrode via an insulating layer in substantially identical plane.

Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a wire-bond of a first metallic composition, the wire-bond and the bond-pad being coated with a protection layer of a second metallic composition.

Abstract: A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.

Abstract: Electrical connections between different materials. An electrical connection system includes electrical components and an electrical connection between the electrical components. The electrical connection includes a functionally graded material. A method of making an electrical connection between different materials includes the steps of: providing an electrical component which includes a material; providing another electrical component which includes another material; and electrically connecting a functionally graded material between the electrical components. An electrical connection system includes an electrical component and a functionally graded material electrically connected to the electrical component. The functionally graded material provides a gradual transition between at least two dissimilar materials.

Abstract: Semiconductor devices, as well as stacked structures, packages, modules, and electronic apparatus including the semiconductor device, and methods of fabricating the same. The semiconductor device includes a circuit layer on a substrate, a metal interconnection layer on the circuit layer, the metal interconnection layer having a copper interconnection and a protection layer, a first and a second through silicon via plugs vertically penetrating the circuit layer, a first via pad on the first through silicon via plug, and a second via pad on the second through silicon via plug, wherein the first via pad is electrically connected to the copper interconnection, and wherein the second via pad is electrically insulated from the copper interconnection.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

Abstract: The invention includes a first step for forming a first conductive layer composed of a high melting point metal to be in contact with an insulating layer; and a second step for forming a second conductive layer by discharging a composition containing a conductive material so as to be in contact with the first conductive layer. The first conductive layer is formed prior to forming the second conductive layer by droplet discharging, and hence, adhesiveness and peel resistance of the second conductive layer are improved. Furthermore, the insulating layer is covered with the first conductive layer, thereby preventing damage or destruction of the insulating layer.

Abstract: A method of bonding two members includes forming a metal pad on a first member and a silicon pad on the second member, and coupling the pads at a temperature and pressure that will not damage features of the members, such as integrated circuitry or MEMS devices, but is sufficient to form a silicide bond. In various embodiments, the metal may be nickel and the silicon may be polysilicon.

Abstract: A porous silica precursor composition is herein provided and the precursor composition comprises an organic silane represented by the following chemical formula 1: R1m(R2—O)4?mSi (in the formula, R1 and R2 may be the same or different and each represent an alkyl group, and m is an integer ranging from 0 to 3); water; an alcohol; and a quaternary ammonium compound represented by the following chemical formula 2: R3N(R4)3X (in the formula, R3 and R4 may be the same or different and each represent an alkyl group and X represents a halogen atom). The composition is prepared by a method comprising the step of blending the foregoing components. The porous silica precursor composition is coated on a substrate and then fired to thus form a porous silica film. Also disclosed herein include a semiconductor element, an apparatus for displaying an image and a liquid crystal display, each having the foregoing porous silica film.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.

Abstract: A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided.

Abstract: A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method.

Abstract: A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided. A manufacturing method of a semiconductor device includes: a step of forming a dielectric thin film in which a plurality of pores are arranged around a skeleton mainly made of a Si—O bond, on a surface of a semiconductor substrate on which a desired element region is formed; a step of applying patterning on a surface of the dielectric thin film through a mask; and a step of bringing a gas containing at least one kind of tetramethylcyclotetrasiloxane (TMCTS), hexamethyldisilazane (HMDS) and trimethylchlorosilane (TMCS) molecules into contact with the patterned surface of the dielectric thin film.

Abstract: In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack.

Abstract: A semiconductor device includes an electrode pad formed on a pad forming surface of a semiconductor integrated circuit chip, and a step formed on the pad forming surface to surround the electrode pad. A method of manufacturing the semiconductor device includes forming a metal film on a pad forming surface of a semiconductor integrated circuit chip, forming an electrode pad on a pad forming surface by selectively etching a metal film using a first mask pattern and forming a step to surround the electrode pad by selectively etching the pad forming surface using a second mask pattern.

Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.