Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material.

Abstract: A semiconductor device according to the present invention includes a substrate, an IC chip that is fixed over the substrate, a conductor that is disposed over a surface of the substrate, a solder resist that covers the surface of the substrate and the conductor and includes an opening that exposes the conductor in a section corresponding to a fixed surface of the IC chip, and an adhesive that contacts an exposed part of the conductor, in which the exposed part is made by the opening.

Abstract: An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced apart from the TSV, and an interconnect structure formed over the semiconductor substrate and electrically connecting the TSV and the pad. The interconnect structure includes an upper portion formed on the pad and a lower portion adjacent to the pad, and the upper portion extends to electrically connect the TSV.

Abstract: A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer or a printed circuit board. The core of the bump is made of polymeric material, and coated with a conductive material. In particular, the compliant bump is disposed on the one side of the conductive contact structure that includes both the bump and the testing area, wherein the testing area allows the area to be functionality tested, so as to prevent damage of the coated conductive material over the compliant bump during a probe testing.

Abstract: Provided is a high-purity copper or high-purity copper alloy sputtering target of which the purity is 6N or higher and in which the content of the respective components of P, S, O and C is 1 ppm or less, wherein the number of nonmetal inclusions having a particle size of 0.5 ?m or more and 20 ?m or less is 30,000 inclusions/g or less. As a result of using high-purity copper or high-purity copper alloy from which harmful inclusions of P, S, C and O system have been reduced as the raw material and controlling the existence form of nonmetal inclusions, the present invention addresses a reduction in the percent defect of wirings of semiconductor device formed by sputtering a high-purity copper target so as to ensure favorable repeatability.

Abstract: A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.

Abstract: A pyridine type metal complex having a partial structure represented by the formula (I) or (I?): wherein, M is a transition metal atom; Ds, which may be the same or different, respectively represent specific conjugated chains; Rs, which may be the same or different, respectively represent a halogen atom, a hydrogen atom, or an alkyl group having 1 to 20 carbon atoms, an alkenyl or alkynyl group having 2 to 10 carbon atoms, an aryl or heteroaryl group having 6 to 10 carbon atoms or an arylalkyl or heteroarylalkyl group having 7 to 13 carbon atoms which may have a substituent group.

Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) Zn-containing additive wherein the particle size of said zinc-containing additive is in the range of 7 nanometers to less than 100 nanometers; (c) glass frit wherein said glass frit has a softening point in the range of 300 to 600° C.; dispersed in (d) organic medium. The present invention is further directed to a semiconductor device and a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition as describe above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.

Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.

Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.

Abstract: A semiconductor apparatus with a penetrating electrode having a high aspect ratio is manufactured with a low-temperature process. A first electrode 3 and a second electrode 6 of a semiconductor substrate 1 that are provided at the front and rear surface sides, respectively, are electrically connected by a conductive object 7 filled in a contact hole 4 and an extended portion 6a of the second electrode 6 extends to the contact hole 4. Even though the contact hole 4 has a high aspect ratio, film formation using the low-temperature process is enabled by using the conductive object 7, instead of forming the second electrode 6 on a bottom portion of the contact hole 4.

Abstract: In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The flexible tape substrate includes a metal layer attached to a polyimide layer without an adhesive there between. A cover is placed on the metal layer to cap a base of the hole. A metal is deposited on the cover exposed at the base of the hole, the metal being used to form a bond with the metal layer. The metal being deposited causes the hole to be plugged up to a selective height. Upon removal of the cover, the metal may also be deposited on the metal layer to increase a thickness of the metal layer.

Abstract: A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.

Abstract: Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: An interconnection structure for a semiconductor device may include lower interconnection patterns disposed in a checker board shape and upper interconnection patterns disposed in a checker board shape and connecting two adjacent lower interconnection patterns to each other.

Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract: A semiconductor device uses a carbon nanotube structure, which reduces an electric resistance and a thermal resistance by increasing a density of the carbon nanotubes. An insulation film covers a first electrically conductive material. A second electrically conductive material is provided on the insulation film. A plurality of carbon nanotubes extend through the insulation film by being filled in an opening part that exposes the first electrically conductive material. The carbon nanotubes electrically connect the first electrically conductive material and the second electrically conductive material to each other. Ends of the carbon nanotubes are fixed to a recessed part provided on a surface of the first electrically conductive material.

Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.

Abstract: Methods and compositions for preparing highly conductive electronic features are disclosed. When organoamine-stabilized silver nanoparticles are exposed to an alkaline composition, the resulting electronic feature is highly conductive. Such methods are particularly advantageous when applied to aged silver nanoparticle compositions.

Abstract: A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.

Abstract: A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.

Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes on a wafer; a step of providing a resin later as a stress relieving layer on the wafer, avoiding the electrodes; a step of forming a chromium layer as wiring from electrodes over the resin layer; and step of forming solder balls as external electrodes on the chromium layer over the resin layer; and a step of cutting the wafer into individual semiconductor chips; in the steps of forming the chromium layer and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract: A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device. More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.

Abstract: A pre-packaged structure includes a substrate with a substrate circuit, a die having a core circuit and disposed on the substrate, a passivation selectively covering the core circuit, a buffer metal layer electrically connected to the core circuit and completely covering the passivation and a copper wire bond electrically connected to the buffer metal layer and the substrate circuit.

Abstract: The bonding time of a metallic ribbon is shortened in the semiconductor device which connects a lead frame with the bonding pad of a semiconductor chip with a metallic ribbon. The bottom of the wedge tool is divided into two by the V-groove at the first branch and the second branch. In order to do bonding of the Al ribbon to the source pad of the silicon chip, and the source post of the lead frame, first, the first branch and second branch of the wedge tool are contacted by pressure to Al ribbon on the source pad, and supersonic vibration is applied to it. Subsequently, the first branch is contacted by pressure to Al ribbon on the source post, and supersonic vibration is applied to it. Here, since the width of the first branch is narrower than the width of the source post, Al ribbon is not joined at the end surface of the width direction of the source post.

Abstract: An apparatus for depositing seed layers over a substrate, which substrate includes a patterned insulating layer with at least one opening surrounded by a field, and which opening has sidewalls, bottom surfaces and top corners, includes: a CVD chamber adapted to deposit one or more CVD seed layers over the substrate; a PVD chamber adapted to deposit one or more PVD seed layers over the substrate; and a controller which includes recipe information. The recipe information includes deposition sequence and process parameters for operation of the deposition chambers.

Abstract: Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.

Abstract: The invention relates to conductive pastes including one or more acids, or acid-forming components for silicon semiconductor devices and photovoltaic cells.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.

Abstract: A semiconductor device includes a semiconductor substrate, electrodes separated from each other and extending from a first main surface in the direction of depth of the semiconductor substrate, and an interconnect portion coupling the electrodes to each other and extending from the first main surface in the direction of depth of the semiconductor substrate without passing through the semiconductor substrate. One of the electrodes is a through electrode passing through the semiconductor substrate to reach a second main surface. For semiconductor devices having through electrodes and vertically stacked on each other, the interconnect portion serves to enhance the degree of design freedom.

Abstract: An electronic device includes a power element on a first substrate and an electronic component on a second substrate. The first and second substrates are stacked so that the power element and the electronic component can be located between the first and second substrates. A first end of a first wire is connected to the power element. A second end of the first wire is connected to the first substrate. A middle portion of the first wire projects toward the second substrate. A first end of a second wire is connected to the power element. A second end of the wire extends above a top of the middle portion of the first conductive member and is connected to the second substrate.

Abstract: A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.

Abstract: A fuse of a semiconductor device includes first fuse metals formed over an underlying structure and a second fuse metal formed between the first fuse metals. Accordingly, upon blowing, the fuse metals are not migrated under conditions, such as specific temperature and specific humidity. Thus, reliability of a semiconductor device can be improved.

Abstract: A semiconductor device includes a through electrode penetrating a semiconductor substrate, a conductor pad formed on the through electrode and made of a conductor electrically connected to the through electrode, and an interconnection layer formed on a surface of the semiconductor substrate and electrically connected to the conductor pad.

Abstract: A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material.

Abstract: The present disclosure relates to methods and solutions for growing metal charge-transfer salts on a metal surface, such as a metal layer at the bottom of a via hole. The method makes use of a solution comprising a salt additive. The temperature during growth is in the range of ?100° C. to +100° C. The method allows controlled growth of the metal charge transfer salt inside via hole while limiting growth outside the via hole. The method further limits corrosion of the metallic connections at the bottom of the via hole.

Abstract: By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.

Abstract: Embodiments of the invention relate to methods and structures for fabricating semiconductor structures that include at least one bonding layer for attaching two or more elements to one another. The at least one bonding layer may be at least substantially comprised of zinc, silicon and oxygen.

Abstract: A semiconductor device wherein a semiconductor element made of Si or Si group material mounted on a substrate, the semiconductor element is mounted on the substrate and the semiconductor element is bonded to a silver bonding material via a oxide film formed on the semiconductor element. The bonding material comprising silver oxide particles having an average particle size of 1 nm to 50 nm and an organic reducing agent is used for bonding in air, which gives a high bonding strength to the oxide on the semiconductor element.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.