Abstract: An imaging device includes a plurality of first pixels, each of which outputs a first pixel signal, a plurality of second pixels, each of which outputs a second pixel signal, a ramp wave generator that outputs a ramp signal that monotonously increases or monotonously decreases over time, a phase shift pulse generator that outputs first to n-th phase shift pulse signals, a first pixel latch group that latches the first to n-th phase shift pulse signals when the first pixel signal and the ramp signal have a predetermined relationship, a second pixel latch group that latches the first to n-th phase shift pulse signals when the second pixel signal and the ramp signal have the predetermined relationship, first to n-th power source lines to supply a power source and first to n-th phase shift pulse supply lines to supply the phase shift pulses.

Abstract: A digitizer system (DS) may include one or more input channels to receive sample data, and an acquisition state machine (ASM) to organize the sample data into one or more acquisition records according to events of interest, and generate framing information corresponding to the one or more acquisition records. The events of interest may be identified by a trigger circuit in the DS, and relayed to the ASM for organizing the sample data. The DS may further include a data interface capable of receiving the one or more acquisition records and the framing information, encoding the one or more acquisition records and the framing information into encoded data, and transmitting the encoded data to an expansion module. The expansion module may receive the encoded data, decode the encoded data, and recover the sample data from the decoded data according to the framing information and the one or more acquisition records.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules.

Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.

Abstract: Disclosed is a solid-state imaging device capable of calculating the difference in charge obtained by photoelectric conversion, and capable of a high level of integration.

Abstract: Self-monitoring reset circuitry is presented for use in analog-to-digital converters and other modulator circuitry with capacitively coupled isolation barriers in which the modulator output data is monitored for inactivity by a reset circuit synchronized to the modulator clock, and extra pulses are selectively introduced into the data prior to transmission across the isolation barrier if no modulator state changes occur within a predetermined number of clock cycles to provide a predictable data output value for each end of the analog input range and to reset the output to the correct state in situations where transient noise toggles the output and the modulator output is static.

Abstract: A system and a method of generating an external parameter value for a separately excited motor controller are disclosed, the system including: a digital signal processor to convert a received analog electrical signal into a digital signal and to scale the digital signal, so as to generate a parameter value in conformity with a data format of the system; an external parameter generating module to adjust the parameter value with a calibration coefficient to obtain the external parameter value; the calibration coefficient being generated by a calibration coefficient generating module and being pre-stored in a calibration coefficient storing module; and a calibration coefficient generating module to read the parameter value generated by the digital signal processor and obtain an actual measuring value as a reference parameter value, to calculate a difference value between the parameter value from the digital signal processor and the reference parameter value, and to generate the calibration coefficient from a rat

Abstract: A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: A solid-state imaging device includes a plurality of pixels arranged in a matrix, a plurality of readout circuits provided in each column of the plurality of pixels arranged in a matrix, configured to read out for each column a signal of the plurality of pixels, a plurality of comparison units configured to compare a signal output from the plurality of readout circuits with a reference signal whose level changes with time, a counter configured to perform a count operation from when the level of the reference signal starts to change, first and second buffers each configured to buffer a count value of the counter, and a plurality of storing units connected to the plurality of comparison units, configured to store a count value of the counter when a magnitude relation between a signal output from the plurality of the readout circuits and the reference signal is inverted.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active.

Abstract: Systems and methods are operable to communicate information to a direct current (DC) powered electronic device. An exemplary embodiment receives alternating current (AC) power with an AC information signal modulated thereon, converts the received AC power to DC power, demodulates the received AC information signal to determine information, modulates the information onto the transmitted DC power as a DC information signal, transmits the DC power with the DC information signal over a DC connector to the DC powered electronic device, detects the DC information signal on the modulated DC power at the DC powered electronic device, demodulates the DC information signal from the received DC power, and determines the information at the DC powered electronic device based upon the demodulated DC information.

Abstract: In one embodiment, a method comprising sampling by a first sampling unit a first signal received via a first antenna; and sampling by a second sampling unit a second signal received via a second antenna, the sampling of the second signal commencing in synchronization with the sampling of the first signal by the first sampling unit based on an accumulated value, the first and second signal sharing common information.

Abstract: Disclosed are various embodiments of circuitry and methods for generating interpolated signals in an optical encoder. The optical encoder configurations and circuitry disclosed herein permit very high resolution reflective optical encoders in small packages to be provided. Methods of making and using such optical encoders are also disclosed. According to one embodiment, the interpolated signals are generated through the use of signal generation circuitry, peak voltage generation circuitry, reference voltage generation circuitry, slope detection circuitry, and a clocked comparator that is configured to output interpolated output pulses.

Abstract: An analog front circuit for a medical device includes an automatic gain control loop and a 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter. The automatic gain control loop is configured to implement automatic control of loop gain and output an analog signal to the 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter. The 2-order-3-bit-quantization Sigma-Delta analog-to-digital converter is configured to convert the analog signal output from the automatic gain control loop into a digital code and output the digital code to a DSP for processing.

Abstract: A solid-state image capture device including: a pixel having a photoelectric conversion element and first to fourth switch elements; a reference-signal generator that generates a reference signal; and an analog-to-digital converter that generates a digital signal corresponding to an analog signal output by the pixel, by using a comparator having first and second input terminals. The second switch element is turned on to reset a voltage of the predetermined connection point, the fourth switch element is turned on while a connection degree of the second switch element is in an intermediate state between an on state and an off state to cause the first and second input terminals to reach a same potential, and the second switch element is not turned on and at least one of the first and third switch elements is turned on to cause the analog-to-digital converter to perform conversion into a digital signal.

Abstract: An analog-digital converter includes: comparators disposed to correspond to analog signals which are converted into digital signals and configured to compare a voltage value of the analog signal, which is converted into the digital signal, with a voltage value of a predetermined reference signal; counters disposed to correspond to the comparators and configured to count a count value at the time point when the comparison process of the corresponding comparator is finished; and a determiner configured to determine a time point when all the comparators finish their comparison processes.

Abstract: In accordance with some embodiments of the present disclosure, a receiver may include a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal. The downconverter may be coupled to the ADC without an intervening filter element.

Abstract: A device monitoring unit obtains, through respective digital communication routes, a combination of a digital setting value for an analog output value to an analog communication route in a field device, a digital value of an AD converting device in an input/output unit, and one of the digital setting values stored in a memory of the input/output unit, to check the status of the communication through the analog communication route based on the values obtained.

Abstract: A direct sampling tuner includes a low noise amplifier and an optional dynamically configurable band pass filter coupled to the low noise amplifier. The optional filter is configured to pass a selected band of channels. The tuner further includes a relatively high accuracy, multi-bit analog-to-digital converter (“ADC”) coupled to the LNA or to the optional dynamically configurable band pass filter. The ADC operates at greater than about twice a frequency of a sampled signal. The ADC directly samples the spectrum of the selected channels at the Nyquist rate, thus avoiding image problems presented by conventional tuners.

Abstract: Systems and methods are operable to communicate information to a direct current (DC) powered electronic device. An exemplary embodiment receives alternating current (AC) power with an AC information signal modulated thereon, converts the received AC power to DC power, demodulates the received AC information signal to determine information, modulates the information onto the transmitted DC power as a DC information signal, transmits the DC power with the DC information signal over a DC connector to the DC powered electronic device, detects the DC information signal on the modulated DC power at the DC powered electronic device, demodulates the DC information signal from the received DC power, and determines the information at the DC powered electronic device based upon the demodulated DC information.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.

Abstract: Switching circuitry comprising a bank of actuatable switches connected in parallel between a supply terminal and a decoding terminal, each switch being connected in series with a component which, when the switch is actuated, applies to the second terminal an analog signal having a value unique to that switch.

Abstract: For detecting an error of an A/D converter, which is designed to generate at least one digital output signal, which includes a quantity of output data bits, based on at least one analog input signal, and during a conversion, to generate a thermometer code which includes a quantity T of output data values, the detection method includes: ascertaining a first parity directly for the output data bits of the output signal; making a prediction for the output data bits on the basis of the T output data values of the thermometer code; ascertaining a second parity, which is a reverse of the first parity, for the predicted output data bits; and detecting an error for the A/D converter when both the first and second parities are identical.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31).

Abstract: Certain aspects of the present disclosure relate to a method for emulating N-bits uniform quantization of a received pulse signal by using one-bit signal measurements. One method for wireless communications includes receiving a signal transmitted over a wireless channel, wherein the signal comprises a sequence of pulses, applying gain values to the pulses to obtain a binary matrix for each gain value, generating a probability vector for each gain value using the binary matrix obtained for that gain value, and generating an output signal by linearly combining the probability vectors.

Abstract: Embodiments of cognitive radio technology can recover and utilize under-utilized portions of statically-allocated radio-frequency spectrum. A plurality of sensing methods can be employed. Transmission power control can be responsive to adjacent channel measurements. Digital pre-distortion techniques can enhance performance. Embodiments of a high DNR transceiver architecture can be employed.

Abstract: In a solid-state imaging device, each of a plurality of switches is connected between a pulse output terminal of each delay unit and a pulse input terminal of the next-stage delay unit. Each of a plurality of switches is connected between the pulse output terminal and the pulse input terminal of each delay unit. A plurality of switches is turned on and a plurality of switches is turned off in conjunction with an oscillation operation, and a plurality of switches is turned off and a plurality of switches is turned on in conjunction with a holding operation.

Abstract: A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

Abstract: An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

Abstract: A hybrid analog-to-digital converter includes a plurality of converting circuits. Each converting circuit is configured to provide a digital signal based on an analog input signal by performing a successive approximation conversion to obtain, as a result of the successive approximation conversion, a first number of bits of the digital signal, and by subsequently performing a slope conversion based on a common variable reference voltage to obtain a second number of bits of the digital signal, the second number of bits corresponding to a residual between the analog input signal and the result of the successive approximation conversion. The hybrid analog-to-digital converter further includes a common variable reference voltage provider configured to provide to each converting circuit of the plurality of converting circuits the common variable reference voltage.

Abstract: A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.

Abstract: An image pickup device is provided, capable of complete correction with data of once analog-to-digital conversion, and prevention of excess use of switches and analog devices and/or erroneous correction, including: an image sensor having a plurality of analog-to-digital converters determining conversion results from a digital signal of higher order bit through separate steps of two or more times; a first correction unit which has a correction factor for correcting nonlinear errors of the plurality of analog-to-digital converters so as to adapt to the analog-to-digital converters and corrects a nonlinear error of a digital signal output from respective analog-to-digital converters based on a correction factor corresponding to respective analog-to-digital converters, characterized in that the first correction unit corrects the nonlinear errors after converting the digital signals from the plurality of analog-to-digital converters into a serial output.

Abstract: Embodiments of the present invention provide systems, devices and methods for efficiently calculating a true RMS values (either voltage or current) of an AC signal. The RMS value is generated from both high and low frequency components of the AC signal without a high speed ADC being integrated within the system. The high frequency component is processed by calculating an average current waveform of the high frequency component and approximating a corresponding RMS value using a waveform factor. The waveform factor is effectively a scalar that relates the average current waveform of the high frequency component to an appropriate RMS value.

Abstract: An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding to the ADC largely transparent to the end-user of the ADC. Therefore, multiple ADCs may be easily synchronized with each other, even if they have different group-delays, and they may further be synchronized with other types of ADCs that do not have group-delays. The data from the ADCs may also be synchronized with external events. The ADC timing engine (ATE) may be programmed with a number of parameters to set proper delays taking into account not only the group-delays corresponding to the various ADC, but delays stemming from a variety of other sources. Multiple ATEs may be synchronized with each other to ensure that data acquisition by the participating ADCs is started and/or stopped at the same point in time.

Abstract: A defect portion in a signal is processed by receiving an input signal. A location of a defect portion within the input signal and an amplitude of the defect portion is determined. An adjusted signal is generated by adjusting the amplitude of the defect portion using the determined location of the defect portion and the determined amplitude of the defect portion. Information associated with the adjusted signal is decoded.

Abstract: A circuit is disclosed that comprises a controller and an analog to digital converter (ADC) coupled to controller. The speed and/or the resolution of the ADC is configurable to provide optimum performance during the operation of the ADC. In an embodiment a wireless receiver with an adaptively configurable ADC for is provided. The speed and resolution the ADC is configurable depending on the operational mode of the receiver. Accordingly, through the use of an adaptively configurable ADC, power consumption and speed is optimized for each operational mode.

Abstract: A solid-state image sensor includes a pixel array unit including a plurality of pixels arranged in the form of an array, column signal lines adapted to transmit pixel signals output from pixels in respective columns, a noise adding unit adapted to add temporally constant and two-dimensional spatially random noise to the pixel signals transmitted via the column signal lines, and an analog-to-digital converter adapted to convert a signal level and a reference level of each pixel signal including the noise added thereto by the noise adding unit.

Abstract: An audio signal processing circuit is provided which comprises an ADC which samples an audio signal at a predetermined sampling frequency, a high-band compensation processor which compensates a signal sampled by the ADC to a frequency band which is higher than a signal band sampled by the sampling frequency, and an encoding unit which encodes a signal processed by the high-band compensation processor.

Abstract: A solid-state image sensing device reads repeatedly M times an analog signal having a black level, during a first A/D conversion period. A frequency divider frequency-divides by M a pulse train depending on the analog signal having a black level that is read repeatedly M times, and a counter circuit counts the pulses of the pulse train, which is frequency-divided by M. Thereafter, the solid-state image sensing device reads repeatedly N times an analog signal having a signal level, during a second A/D conversion period. The frequency divider frequency-divides by N a pulse train depending on the analog signal having a signal level that is read repeatedly N times, and the counter circuit counts the pulses of the pulse train, which is frequency-divided by N. M and N satisfy the relationship N?M.

Abstract: A method of providing a value for each element of a sequence of elements in a converter, the values being for a present conversion cycle in operation of the converter, wherein a pointer position identifies an element in the sequence of elements for a conversion cycle.

Abstract: A programmable processing device having a control system and a programmable reference block. The control system sends digital control signals to the programmable reference block, which in turn generates analog variable signals used as reference signals for the programming of the one or more reconfigurable data converters.

Abstract: In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.

Abstract: Provided is a test apparatus that tests a device under test, comprising a digital signal generator that outputs in parallel one or more n-bit digital test signals, where n is an integer greater than or equal to 1; a plurality of driver circuits that are connected respectively to a plurality of digital terminals of the device under test; and an analog signal generator that generates an analog test signal by converting, into an analog signal, an n×m-bit digital multi-bit signal based on the one or more digital test signals output by the digital signal generator to the plurality of driver circuits, where m is an integer greater than or equal to 2.

Abstract: A configurable field device for automation technology with a partially dynamically reconfigurable logic chip FPGA, in which function modules are dynamically configured during runtime, and to a method for operating the configurable field device.

Abstract: An analog-digital converter includes: comparators disposed to correspond to analog signals which are converted into digital signals and configured to compare a voltage value of the analog signal, which is converted into the digital signal, with a voltage value of a predetermined reference signal; counters disposed to correspond to the comparators and configured to count a count value at the time point when the comparison process of the corresponding comparator is finished; and a determiner configured to determine a time point when all the comparators finish their comparison processes.

Abstract: An active matrix array device has driver circuitry for providing address signals to the matrix elements, including digital to analogue converter circuitry. This has a voltage selector for selecting a pair of voltages based on a first set of bits of the digital matrix element signal, and a converter arrangement for providing an analogue voltage level derived from the pair of voltages and from a second set of bits of the digital matrix element signal. The converter arrangement comprises first and second digital to analogue converter circuits (30, 32) in parallel and which are adapted to provide an analogue voltage level to an output of the converter arrangement alternately. The invention provides a more efficient use of substrate area for given circuit response requirements.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other wireless device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one wireless device to receive inbound packetized audio data from the at least one wireless device and to transmit outbound packetized audio data to the at least one wireless device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.