Abstract: A signal processing apparatus includes a first signal processor which processes a first channel of signal; and a second signal processor which processes a second channel of signal independently from the processing by the first signal processor.

Abstract: Disclosed is an integrated circuit comprising a substrate having a plurality of digital signal processors, including at least one analog circuit block, and means on said substrate for programmably interconnecting said processors and said at least one analog circuit block together. Also disclosed is a programming system comprising means for converting a programmable analog array specification into one or more programs executable by one or more digital signal processors so as to perform the identical or substantially identical function or functions as the programmed analog array.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: A data transmission system for interconnecting semiconductor integrated circuit devices, and a semiconductor integrated circuit adapted to the data transmission system are disclosed. The semiconductor integrated circuit has an input circuit, an internal circuit, and an output circuit. The input circuit has an ADC for converting a multi-value current data input from the outside to a collection of binary voltage level data. The internal circuit receives the collection of binary voltage level data from the ADC, and outputs the collection of binary voltage level data. The output circuit has a DAC for converting rig the collection of binary voltage level data output from the internal circuit to multi-value current data to output the multi-value current data to the outside.

Abstract: A system and method for converting an analog voltage signal to a digital representation at high speeds, known as an analog to digital converter (A/D converter), is provided in the form of an N-bit A/D converter, made by N superconducting, preferably HTC, transmission lines. The N lines are arranged adjacently and in parallel with each other. On each line 2N−1 Josephson Junctions (JJs) are embedded in series. The JJs form a matrix over the configuration of the N superconducting transmission lines. A scanning electron beam is made to impinge on this arrangement across the lines at a high frequency, while it is deflected by the applied voltage signal along the direction of the lines. A voltage step is generated upon hitting any one of the JJs. In this manner upon each cross-scanning of the beam, an N-bit step voltage pattern is generated on the lines.

Abstract: Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.

Abstract: A digitizer for use in a measurement system. The digitizer acquires data from an external source, and includes a static random access memory (SRAM) which stores a scan list comprising entries specifying digitizer operations such as switch time, settle time, measure time, looping, and mathematical operation specifications such as scaling, adding, and averaging specifications. The looping specification may include instructions to repeatedly execute one or more entries in the scan list. The digitizer includes a programmable logic element (e.g. an FPGA) coupled to the SRAM which accesses and executes the scan list to acquire analog signals from the source. The digitizer may include an analog-to-digital converter to convert the analog signals to digital signals, as well as a multiplexer to read the analog signals from multiple channels, a signal conditioner to modify the analog signals from the multiplexer, and an amplifier to amplify the analog signals from the signal conditioner.

Abstract: Analog input module for a programmable logic controller, the analog input module having an input circuit with terminals for accepting either a single voltage range or a single current range from process control sensors. The analog input module includes an analog-to-digital converter and an input circuit with an output terminal connected to the input of the analog-to-digital converter, a voltage input terminal, a current input terminal, and a common terminal. The input circuit is configured to accept a voltage input between the voltage input terminal and the common terminal, to accept a current input between the current input terminal and the common terminal, and to provide an output voltage at the output terminal dependent upon either the voltage input or the current input, without switching or configuring between them.

Abstract: A data transmission system for interconnecting semiconductor integrated circuit devices, and a semiconductor integrated circuit adapted to the data transmission system are disclosed. The semiconductor integrated circuit has an input circuit, an internal circuit, and an output circuit. The input circuit has an ADC for converting a multi-value current data input from the outside to a collection of binary voltage level data. The internal circuit receives the collection of binary voltage level data from the ADC, and outputs the collection of binary voltage level data. The output circuit has a DAC for converting the collection of binary voltage level data output from the internal circuit to multi-value current data to output the multi-value current data to the outside.

Abstract: A system that improves acquisition fidelity in high-bandwidth interleaved acquisition systems through a process called sample-synthesis. Synthesizers are used to make data from one digitizing element appear as though it were sampled by another digitizing element. This method overcomes the Nyquist limitations imposed on a single digitizer. The topology for this system is described, and an explanation of the operation is provided. Then, details are provided for the consideration of Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter implementations of sample synthesizers.

Abstract: An improved three-order sigma-delta modulator having a feedback and a feedforward configuration.

Abstract: An analog to digital converting device has a photo-coupled switching device that is composed of a plurality of input channels, and each input channel is composed of a pair of photo relays, wherein each photo relay is controlled by an A/D converting module to be turned on/off. Since the photo relay has high impedance, the isolation between two adjacent channels is enhanced, and possible damage from an interference voltage that occurs across two adjacent channels is avoided.

Abstract: An object of the invention is to provide a wireless input apparatus capable of recognizing the end of an operation with reliability even when any trouble occurs in a wireless communication channel. When an operation of pressing a key of a wireless keyboard is carried out, the operation is detected by a key press detecting section, and a key press signal is transmitted from an infrared rays emitting section with a medium of infrared rays. When the key is kept pressed, the key press signal is transmitted at intervals of a time detected by a time detecting section. The signal received by an infrared rays receiving section of a processing unit is detected by a signal detecting section, and a timer for a threshold time is restarted by a time detecting section. The threshold time is set so as to be longer than the interval of signal reception.

Abstract: An apparatus for generating an analog signal and methods of operating the same results in a cost effective solution for an audio sound generator. The apparatus for generating an analog signal comprises an I2C interface configured to provide programming data in response to write control signals, a non-volatile memory coupled to the I2C interface configured to store the programming data, a pulse width modulator coupled to the non-volatile memory configured to receive the programming data from the non-volatile memory and provide a pulse width modulated output in response to the programming data, and a d/a converter coupled to the non-volatile memory configured to receive the programming data from the non-volatile memory and provide an analog output in response to the programming data. The pulse width modulated output can be coupled to a piezoelectric speaker to produce audible sound. The analog output provides a line out signal that can be coupled to a dynamic speaker.

Abstract: A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT.

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type which comprises at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUTI) through at least one integrative/proportional branch (120, 121, 130, 134).

Abstract: A high speed analog-to-digital converter, for converting an analog input signal (u(t)) with a maximum frequency (Fmax) to a digital output signal (x(n)) with an output sampling rate (Fs) at least double the maximum frequency (Fmax), comprises a plurality of analog narrowband filters (F0-FM−1) for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X0-XM−1), which is supplied to a corresponding plurality of analog-to-digital converter units (AD0-ADM−1). The converter also comprises sampling and summing circuitry for sampling the outputs of the analog-to-digital converter units sequentially at the predetermined sampling rate (Fs) and summing the resulting sampled signals to produce the digital output signal (x(n)).

Abstract: A digital-to-analog converter is disclosed, which includes a decoder stage having a decoder output capable of receiving input data, a level shifter stage coupled to the decoder output capable of shifting the level of the decoder output, an output stage communicatively coupled to the level shifter stage capable of responding based upon an output value of the level shifter stage, and a current mirror communicatively coupled to the level shifter and capable to shift the level of the decoder output, and further includes an output stage having switches, which are selectively turned on by an output signal from the decoder stage thus outputting a reference voltage.

Abstract: The invention is directed to a method for adapting decision levels in the conversion of a multi-level analog signal into a digital signal, and to a digital receiver. As starting condition a certain level difference between two levels and also a first logic state, which the analog signal represents at the beginning of the data transmission, are predetermined. A second logic state is recognized in that the level of the analog signal varies by more than the level difference. A decision level is then calculated continually which lies between the levels of the first and second logic state.

Abstract: A system and method for converting an analog voltage signal to a digital representation at high speeds, known as an analog to digital converter (A/D converter), is provided. The invention teaches an N-bit A/D converter, made by N superconducting, preferably HTC, transmission lines. The N lines are arranged adjacently and in parallel with each other. On each line 2N-1 JJs are imbedded in series. The JJs form a matrix over the configuration of the N superconducting transmission lines in such a manner that across the lines the JJs give N digit binary numbers, while in the length direction these N digit binary numbers fall in numerical order. A scanning electron beam is made to impinge on this arrangement. The beam is scanned across the lines at a high frequency, while it is deflected by the applied voltage signal along the direction of the lines. The beam generates a voltage step on any one of the N lines on condition of hitting any one of the JJs.

Abstract: An improved self-calibrating and self-repairing Data Acquisition System (DAS) for use in inaccessible areas, such as onboard spacecraft, and capable of autonomously performing required system health checks, failure detection. When required, self-repair is implemented utilizing a “spare parts/tool box” system. The available number of spare components primarily depends upon each component's predicted reliability which may be determined using Mean Time Between Failures (MTBF) analysis. Failing or degrading components are electronically removed and disabled to reduce power consumption, before being electronically replaced with spare components.

Abstract: In a reference-voltage-selection-type D/A converter, the channel widths of transistors of MOS switches of gradation selecting units are weighted depending on the selected gradation. Specifically, the channel width of the MOS switches Qn11, Qn12 is represented by W0, the channel width of the MOS switches Qn13, Qp11 is represented by W1, the channel width of the MOS switches Qp12, Qn14 is represented by W2, and the channel width of the MOS switches Qp13, Qp14 is represented by W3. The channel width W3 is set to a size corresponding to the maximum capacitance of a column line, and the other channel widths W0, W1, W2 are set to satisfy the relationship: W0<W1<W2<W3. With this arrangement, the frame of a display panel which incorporates the D/A converter is reduced in size.

Abstract: Differential non-linearity errors in an A/D converter are corrected by an analog system. The system produces different analog voltages which are used to correct the input voltage to the capacitor. The input voltage is changed by an amount which is effective to correct the C&Dgr;V to be the same as it would have been if the DNL error had not occurred.

Abstract: Information handling systems, disc drives, and methods for digitizing a readback waveform for testing a hard disc drive are disclosed. An information. handling system, such as a disc drive, includes a base, a disc stack rotatably attached to the base, and an actuator assembly movably attached to the base. Attached to one end of the actuator assembly is one or more transducers. Attached to the other end of the actuator is a voice coil that forms a portion of a voice coil motor. Magnets attached to the base form the other portion of the voice coil motor. An analog readback signal is reconstructed for use in testing a disc drive by digitizing a waveform generated within a read channel arrangement to produce digitized waveform data. The analog readback signal is then determined as a function of the digitized waveform data.

Abstract: A correlation modulating apparatus that is adapted to modulate high frequency data into low frequency signals. In the apparatus, a register lists in parallel a data bit stream by at least two bit using a key clock having less frequency than a data clock. A converter converts the listed at least two bit data into an analog signal. A frequency of the analog signal is lowered into below at least ½ compared with that of the data bit stream.

Abstract: Circuitry is provided to compensate for distortion introduced into the output signal of a delta sigma digital to analog converter (DAC) by the power output stage of the amplifier. Such distortion is not consistent for a given output data value or short series of data values, but must be either measured and corrected in real time or must be corrected in real time based upon a sophisticated model of the system that predicts the distortion. Correction is applied to one or more feedback loops in the delta sigma converter. Distortion caused by fluctuations in the power supply voltage may also be modeled and corrected in real time.

Abstract: A selector switch in which an input obtained from a range of continuous analog signals is used to select from one of a set of discrete selections. Each selection is assigned a specified range of analog signals. Each range is separated from an adjoining range by a guard band of signals. A determination is made as to whether the input analog signal is within one of the specified ranges of analog signals. If so, a sector indicator is set to correspond to the specified range. Otherwise, the sector indicator is not changed.

Abstract: A resistive DAC (1) comprises a digital input port (2) and an analog output port (3) on which analog resistance output values are outputted in response to corresponding digital input codes on the input port (2). A decoding and control circuit (4) selects appropriate resistors (R1) to (RN) from a resistor chain (5) for providing the analog resistance output of the analog output port (3). A register (7) stores a transfer coefficient in binary code which can be read through the input port (2) and by which each digital input code should be multiplied in order to produce an analog resistance output of predetermined value. The transfer coefficient in the register (7) takes account of variations in internal circuit parameters which causes the analog resistance outputs on the output port (3) to be less than they would in an ideal resistive DAC.

Abstract: A method and a configuration are provided for digitally processing an analog signal, especially of output quantities of an optical transducer. The analog signal is divided into a number of partial analog signals having in each case different frequency ranges. The levels of the partial signals are adapted to the dynamic ranges of downstream digitizing device by analog amplification. This results in an improved signal-to-noise ratio.

Abstract: An interface module includes a high density analog interface (HAI) for electrical interconnection between a programmable logic controller (PLC) and an analog to digital converter (ADC) or a digital to analog converter (DAC). The HAI includes a single application specific integrated circuit having a data scaling function block, a diagnostics function block configured to verify functionality of said scaling function block, a self-calibration function block configured to compensate for drift in said ADC, and a shared interface function block configured to electronically connect said module with a programmable logic controller (PLC).

Abstract: The invention relates to a digital data-transmission system, especially for transmission of digital audio data, with a transmitter (11) which receives a digital data stream to be transmitted and with a receiver which receives the transmitted digital data stream. According to the invention, it is provided that, upstream from the transmitter (11), there is connected a signal-processing circuit (12), which converts the signal shape of the digital data stream supplied thereto into a signal shape that can be transmitted loss-free by the transmitter (11).

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Abstract: A low power sample rate converter adapted for use with a telecommunications system transceiver. The sample rate converter includes a first circuit that provides an input signal characterized by a first sample rate and a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, samples in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, samples in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal providing a rate-converted version of the input signal as an output signal in response thereto.

Abstract: A pair of internal signals are generated by halving a 3-bit 5-valued input signal, neglecting the least significant bit LSB. If the input signal shows the value of an odd number, 1 is added to either of the pair of internal signals to generate first and second signals. “1” is added to either of the pair of internal signals in an alternating way each time an input signal having the value of an odd number. Signal processing circuits selects a number of output terminals corresponding to the value of the first signal or the second signal out of a plurality of output terminals. All the output terminals are selected with a same probability.

Abstract: An analog-to-digital converter is provided for converting an analog signal to a one-bit digital bit stream. The A/D converter uses a multi-bit analog delta-sigma modulator coupled to receive the analog input signal, and a one-bit digital delta-sigma modulator coupled to receive the digital output from the multi-bit analog delta-sigma modulator. The analog delta-sigma modulator uses a multi-bit quantizer having minimal quantization noise, and the digital delta-sigma modulator converts the multi-bit quantizer output into a single bit delta-sigma digital format compatible with digital audio systems which require a one-bit delta-sigma format. Thus, the present A/D converter uses the benefits of a multi-bit quantizer, yet can produce a one-bit, delta-sigma modulator output. In addition to linking with the one-bit delta-sigma modulator, the multi-bit quantizer output can be fed directly into a digital audio system which uses a multi-bit encoded delta-sigma or PCM format.

Abstract: An amplifier includes a first circuit and a second circuit. The first circuit, in a first mode of the amplifier, amplifies an input signal to produce a first output signal. The second circuit is coupled to the first circuit to cause the first circuit to, in a second mode of the amplifier, provide a second output signal that is indicative of a degree of calibration of the amplifier.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: Disclosed is a quantizer that uses optimum decision thresholds that are determined by the average of the optimum reconstruction levels of a detected signal in the presence of noise. The Lloyd-Max Quantizer is used to determine the optimum reconstruction levels yK using a minimum means squared error technique. Decision thresholds xK are therefore established at levels where influences of noise or other distortions are equally likely to occur between adjacent transmitted points. The present invention can be utilized in quadrature amplitude modulation (QAM) systems or any quantizer design that quantizes an analog signal.

Abstract: A signal processing device uses a &Dgr;&Sgr; modulator having varying effective orders to ensure an S/N ratio by selecting a high order when a 1-bit music signal is output via the &Dgr;&Sgr; modulator. The signal processing device prevents a noise during switchover by shifting to a low order just before the &Dgr;&Sgr; modulator is bypassed if this occurs. The present invention provides a digital signal processing device which can switch between an original sound signal and a &Dgr;&Sgr; modulation signal, and yield a sufficient S/N ratio for a reprocessed &Dgr;&Sgr; modulation signal. If any 1-bit original sound signal is input, little switching noise is generated.

Abstract: A/D conversion of a current input is performed with integrate-and-fire spiking neurons. Techniques that upcount or downcount the number of spikes fired by one neuron in a time period established by another neuron yield quantized estimates of analog charge residues created by the input current. Recursive application of alternate upcounting and downcounting operations yields successively finer quantization estimates that are terminated by an error-correction operation to obtain the least significant bit of the conversion. A spike-based hybrid state machine (HSM) employing both analog and digital elements is configured to create a 2-step or a successive-subranging analog-to-digital converter. The speed of the conversion is augmented in a pipelined topology. In the HSM, a spike-triggered finite state machine (FSM) controls the input currents to the spiking neurons and is in turn controlled by spikes arising from these neurons.

Abstract: A/D converter or as a D/A converter forms a data converter embedded in a digital circuit for reconfigurable use. Conversion parameters of the data converter are controlled on a bitwise basis from a bitwise converter configuration register. For instance, output locations (i.e., time slots) of the data converter are determined by a bitwise converter configuration register, as is the selection of a D/A conversion mode or A/D conversion mode of the data converter for that particular output location, and/or the output sample length are controlled by appropriate signals from the bitwise converter configuration register. The bitwise converter configuration register also preferably configures the input source to the data converter and/or to an interface, e.g., to a parallel-to-serial, serial-to-serial, or parallel-to-parallel interface device, on a bitwise basis, to provide flexibility both in the source of the channels as well as the output location of particular channels in the data frame.

Abstract: A digital filter in an oversampling converter is tuned to compensate for the non-ideal frequency response of a transducer coupled to the converter. In the A/D path, the filter coefficients of the decimation filter in a sigma-delta converter are tuned to compensate for the transducer. In the D/A path, the filter coefficients of the interpolation filter of a sigma-delta converter are tuned to compensate for the transducer. Filter coefficients may be statically defined in circuitry or programmable from values stored in a storage memory. Compensation may also be accomplished by tuning capacitor ratios in a switched capacitor filter, which is typically integral to the D/A path of an oversampling converter.

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC.

Abstract: A signal convertor comprising a pulse modulator, and means for modifying the signal input thereto in dependence upon the error in previous values of the output thereof, to reduce the effects of said error within a desired signal band.

Abstract: A digital-to-analog converter has two power supply nodes connected through a ladder-type resistor network to n-p-n bipolar transistors supplied with a reference voltages and directly supplied to n-p-n bipolar transistors responsive to a digital input signal, respectively, when a manufacturer tests the digital-to-analog converter, the tester sequentially changes the value of the digital input signal, and an ammeter measures the amount of electric current flowing through the ladder-type resistor network into the n-p-n bipolar transistors for accurately diagnosing the digital-to-analog converter on the basis of the variation of the electric current.

Abstract: An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

Abstract: A pipelined oversampling analog-to-digital converter having a first conversion block including inputs for receiving an analog input signal and an analog reference signal, and a plurality of conversion blocks following the first conversion block. Each conversion block includes means for receiving the analog input signal and the analog reference signal, and at least one analog integrator input and at least one digital decimator input from a previous conversion block; a D/A converter having at least one distinct analog output level and an analog input of the analog reference signal; at least one integrator; a quantizer that computes at least one bit as an output; means for combining the output of the quantizer with the at least one digital decimator input; and means for providing an analog output signal output, at least one analog integrator output, and at least one digital decimator output to a following conversion block.

Abstract: Serial data processor (16) includes a digital processor (106) , a memory controller (114) interconnected with digital processor (106), and dynamic serial access memory (112) interconnected with memory controller(134) . First data selection circuit (134) sends serial data either from serial-data-in terminal (94), from dynamic serial access memory (112), or from digital processor (106) to second serial-data-in terminal (138), in response to a first control signal. Second data selection circuit (144) sends serial data either from serial-data-in terminal (138), from dynamic serial access memory (132) or from the digital processor to serial-data-out terminal (96), in response to a second control signal. A third data selection circuit (120) sends serial data either from serial-data-in terminal (94) , from dynamic serial access memory (112), or from the digital processor (90) to third serial-data-in terminal (150), in response to a third control signal.

Abstract: A signal processor for 1-bit signals comprises an nth order D Sigma Modulator (DSM) having an input (4) for receiving a 1-bit signal and an output (5) at which a processed 1-bit signal is produced by a quantizer (Q). The quantizer (Q) receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier (An) coupled to the input (4), a second 1-bit multiplier (Cn) coupled to the output (5), an adder (6n) which sums the outputs of the coefficient multipliers and an integrator (7n) which integrates the output of the adder (6n). A final stage comprises a coefficient multiplier (An+1) and an adder (6n+1). The adder (6n+1) sums the output of the coefficient multiplier (An+1) and the output of the integrator of the preceding integration stage. The input signal is fed to all the stages except the final stage via a 1-bit delay. The output signal of the quantizer is fed back to the stages via a 1-bit delay.

Abstract: An optical quantizer (10) that employs a chain of optical thresholding devices (16) positioned in the propagation path of an optical input beam (12) to be quantized. Each optical thresholding device (16) saturates and turns transparent if the intensity of the optical beam (12) that impinges it is above a predetermined threshold level designed into the device (16). If the input beam (12) saturates the optical thresholding device (16), the device (16) outputs an indicator signal (22) identifying the saturation. The input beam (12) propagates through the optical thresholding device (16) with some attenuation caused by the saturation, and impinges subsequent optical thresholding devices (16) in the chain. Eventually, the attenuation of the input beam (12) caused by the multiple saturations will decrease the beam intensity below the threshold level of the next optical thresholding device (16). The number of indicator signals (22) gives an indication of the intensity of the input beam (12).