Abstract: A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element.

Abstract: A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract: Provided are semiconductor films, methods of forming the same, transistors including the semiconductor films, and methods of manufacturing the transistors. Provided are a semiconductor film including zinc (Zn), nitrogen (N), oxygen (O), and fluorine (F), and a method of forming the semiconductor film. Provided are a semiconductor film including zinc, nitrogen, and fluorine, and a method of forming the semiconductor film. Sputtering, ion implantation, plasma treatment, chemical vapor deposition (CVD), or a solution process may be used in order to form the semiconductor films. The sputtering may be performed by using a zinc target and a reactive gas including fluorine. The reactive gas may include nitrogen and fluorine, or nitrogen, oxygen, and fluorine.

Abstract: A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a first insulating section, and a second insulating section. The first semiconductor region includes silicon carbide, is of a first conductivity type and includes first and second parts. The second semiconductor region includes silicon carbide, is of a second conductivity type and is provided on the second part. The third semiconductor region includes silicon carbide, is of the first conductivity type and is provided on the second semiconductor region. The first electrode is provided on the first part and the third semiconductor region. The first insulating section is provided on the third semiconductor region and juxtaposed with the first electrode. The second insulating section is provided between the first electrode and the first part and between the first electrode and the first insulating section.

Abstract: A method of manufacturing a large area gallium nitride (GaN) substrate includes forming a buffer layer on a silicon substrate, forming an insulation layer pattern on a rim of a top surface of the buffer layer, growing a GaN layer on the buffer layer, and removing the insulation layer pattern and a portion of the GaN layer and the silicon substrate.

Abstract: Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2, and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.

Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.

Abstract: Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer.

Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).

Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips.

Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

Abstract: A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other.

Abstract: Uniformity of vapor deposited coatings on semiconductor wafers is improved by employing an apparatus having a gas distributor head below a susceptor onto which the wafer is placed, the gas distributor head directing a fan of cooling gas at the rear side of the susceptor. The ratio of the diameter of the cooled section of the susceptor to the diameter D of the wafer is preferably from 0.1 to 0.4.

Abstract: A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (10) of a rotating-disc reactor and directed downwardly onto a wafer carrier (32) and substrates (40) which are maintained at an elevated substrate temperature, typically above about 400° C. and normally about 700-1100° C. to deposit a compound such as a III-V semiconductor. The gases are introduced into the reactor at an inlet temperature desirably above about 75° C. and most preferably about 100°-350° C. The walls of the reactor may be at a temperature close to the inlet temperature. Use of an elevated inlet temperature allows the use of a lower rate of rotation of the wafer carrier, a higher operating pressure, lower flow rate, or some combination of these.

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.

Abstract: The presently claimed invention provides a barium strontium titanate/strontium titanate/gallium arsenide (BST/STO/GaAs) heterostructure comprising a gallium arsenide (GaAs) substrate, at least one strontium titanate (STO) layer, and at least one barium strontium titanate (BST) layer. The BST/STO/GaAs heterostructure of the present invention has a good temperature stability, high dielectric constant and low dielectric loss, which enable to fabricate tunable ferroelectric devices. A method for fabricating the BST/STO/GaAs heterostructure is also disclosed in the present invention, which comprises formation of at least one STO layer on the GaAs substrate by a first laser molecular beam epitaxial system, and formation of at least one BST layer on the STO layer by a second laser molecular beam epitaxial system.

Abstract: Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on one principal surface of the silicon carbide substrate; process (C) of forming on another principal surface of the silicon carbide substrate, a first metal layer; process (D) of heat treating the silicon carbide substrate after the process (C) to form an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate, and a layer of a substance (10) highly cohesive with another metal on the first metal layer; and a process (E) of removing impurities and cleaning a surface of the first metal layer (8) on the other principal surface of the silicon carbide substrate (D), are performed. The heat treatment at process (D) is executed at a temperature of 1,100 degrees C. or more.

Abstract: Semiconductor structures having insulators coatings and methods of fabricating semiconductor structures having insulators coatings are described. In an example, a method of coating a semiconductor structure involves adding a silicon-containing silica precursor species to a solution of nanocrystals. The method also involves, subsequently, forming a silica-based insulator layer on the nanocrystals from a reaction involving the silicon-containing silica precursor species. The method also involves adding additional amounts of the silicon-containing silica precursor species after initial forming of the silica-based insulator layer while continuing to form the silica-based insulator layer to finally encapsulate each of the nanocrystals.

Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.

Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.

Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.

Abstract: Objects of the present invention are to provide a method for producing a Group III nitride semiconductor single crystal, which method enables production of a Group III nitride semiconductor single crystal having a flat surface by means of a crucible having any inside diameter; to provide a self-standing substrate obtained from the Group III nitride semiconductor single crystal; and to provide a semiconductor device employing the self-standing substrate. The production method includes adding the template, a flux, and semiconductor raw materials to a crucible and growing a Group III nitride semiconductor single crystal while the crucible is rotated. In the growth of the semiconductor single crystal, the crucible having an inside diameter R (mm) is rotated at a maximum rotation speed ? (rpm) satisfying the following conditions: ?1?4????1+4; ?1=10z; and z=?0.78×log10(R)+3.1.

Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract: A CIGS film production method is provided which ensures that a CIGS film having a higher conversion efficiency can be produced at lower costs at higher reproducibility even for production of a large-area device. A CIGS solar cell production method is also provided for producing a CIGS solar cell including the CIGS film. The CIGS film production method includes: a stacking step of stacking a layer (A) containing indium, gallium and selenium and a layer (B) containing copper and selenium in a solid phase in this order over a substrate; and a heating step of heating a stacked structure including the layer (A) and the layer (B) to melt a compound of copper and selenium of the layer (B) into a liquid phase to thereby diffuse copper from the layer (B) into the layer (A) to permit crystal growth to provide a CIGS film.

Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

Abstract: The substrate is made of a compound semiconductor, and has a recess, which opens at one main surface and has side wall surfaces when viewed in a cross section along a thickness direction. The gate insulating film is disposed on and in contact with each of the side wall surfaces. The substrate includes a source region having first conductivity type and disposed to be exposed at the side wall surface; and a body region having second conductivity type and disposed in contact with the source region at a side opposite to the one main surface so as to be exposed at the side wall surface, when viewed from the source region. The recess has a closed shape when viewed in a plan view. The side wall surfaces provide an outwardly projecting shape in every direction when viewed from an arbitrary location in the recess.

Abstract: Embodiments of the invention describe a method for forming dielectric films for semiconductor devices. The method includes providing a substrate in a process chamber containing a microwave plasma source, introducing into the process chamber a non-metal-containing process gas including a deposition gas having a carbon-nitrogen intermolecular bond, forming a plasma from the process gas, and exposing the substrate to the plasma to deposit carbon-nitrogen-containing film on the substrate. In some embodiments, the carbon-nitrogen-containing film can include a CN film, a CNO film, a Si-doped CN film, or a Si-doped CNO film.

Abstract: A process for forming a single crystal layer of one material type such as III-V semiconductor) onto a substrate of a different material type such as silicon. A substrate of a first material type is provided. At least one discrete region of catalyst material is deposited onto the substrate, the discrete region defining a seed area of the substrate. A second material type such as III-V semiconductor is grown as a single crystal nanowire onto the substrate between the substrate and catalyst material, the nanowire of second material type extending upward from the substrate with lateral dimensions not substantially exceeding the seed area. After growth of the nanowire, growth conditions are changed so as to epitaxially grow the second material type laterally from the single crystal nanowire in a direction parallel to the substrate surface.

Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.

Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.

Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.

Abstract: An integrated circuit includes a first switching device including a first semiconductor region in a first section of a semiconductor portion and a second switching device including a second semiconductor region in a second section of the semiconductor portion. The first and second sections as well as electrode structures of the first and second switching devices outside the semiconductor portion are arranged along a vertical axis perpendicular to a first surface of the semiconductor portion.

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract: A photolithographic method which produces a structure in a radiation-emitting semiconductor component by providing a semiconductor wafer having a semiconductor layer sequence, applying a first photoresist layer to the semiconductor wafer, providing a mask, and arranging the mask relative to the coated semiconductor wafer, exposing the first photoresist layer and imaging the mask in the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at another position different from a first position and again exposing the first photoresist layer and imaging the mask in the first photoresist layer or applying a second photoresist layer to the first photoresist layer, arranging the mask or a different mask relative to the semiconductor wafer at a second position, and exposing the second photoresist layer and imaging the mask in the second photoresist layer, forming a patterned photoresist layer and patterning the semiconductor wafer.

Abstract: A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial layers from bulk or free-standing GaN substrates without damaging the substrate, allowing the substrate to be reused for further growth of additional epitaxial layers. The method facilitates a significant cost reduction in device production by permitting the reuse of expensive bulk or free-standing GaN substrates.

Abstract: Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.

Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

Abstract: A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material.

Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.

Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.

Abstract: A vapor deposition device includes a vapor deposition chamber, a heating chamber, a mixing chamber, a first reservoir for storing trichlorosilane gas, and a second reservoir for storing silane gas that reacts with hydrochloric acid gas. The heating chamber communicates with the first reservoir and the mixing chamber, heats the trichlorosilane gas and then supplies the heated gas to the mixing chamber. The mixing chamber communicates with the second reservoir and the vapor deposition chamber, mixes the heated gas supplied from the heating chamber and the silane gas and then supplies the mixed gas to the vapor deposition chamber. A temperature in the heating chamber is higher than a temperature in the mixing chamber.

Abstract: The present invention relates to a LED (light-emitting diode) phosphor and fabricating method thereof, and particularly relates to a LED phosphor having a light-emitting thin film (or photoluminescence thin film) made of an organic material and a zinc oxide microstructure (or nanostructure) and a method for fabricating the LED phosphor by hydrothermal method and combination of the organic material and the zinc oxide microstructure (or nanostructure). In this invention, the light-emitting thin film (or photoluminescence thin film) made of the organic material and the zinc oxide microstructure (or nanostructure) is applied instead of rare earth elements to fabricate the LED phosphor. Therefore, the cost of the LED phosphor and the white LED can be reduced and the processes for fabricating the LED phosphor and the white LED can be simplified.

Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.

Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.

Abstract: A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. Methods to form the structure are also disclosed.