Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

Abstract: The present invention discloses a method of heteroepitaxial growth enabling the successful growth of thin films of GaN and III-nitride semiconductor heterostructures of (0001) orientation with III metal-face polarity on diamond substrates being either polycrystalline or single crystal with various crystallographic orientations. The method uses a thin AlN nucleation layer on the diamond substrate with thickness equal or less than 5 nm, grown by Molecular Beam Epitaxy (MBE) using a nitrogen plasma source. The invention enables the development of very high power metal-face III-nitride devices, such as High Electron Mobility Transistors, on single crystal or polycrystalline diamond substrates. The method is also applicable for other element IV substrates with diamond crystal structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction.

Abstract: Described herein are precursors and methods for forming silicon-containing films.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.

Abstract: An apparatus comprising a plurality of solar cells that each comprise a nanowire titanium oxide core having graphene disposed thereon. By one approach this plurality of solar cells can comprise, at least in part, a titanium foil having the plurality of solar cells disposed thereon wherein at least a majority of the solar cells are aligned substantially parallel to one another and substantially perpendicular to the titanium foil. Such a plurality of solar cells can be disposed between a source of light and another modality of solar energy conversion such that both the solar cells and the another modality of solar energy conversion generate electricity using a same source of light.

Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

Abstract: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.

Abstract: A method of forming a semiconductor device including forming a dielectric material layer on a semiconductor layer, forming a gate electrode material layer on the dielectric material layer, forming mask features on the gate electrode material layer, forming a spacer layer on and at sidewalls of the mask features and on the gate electrode material layer between the mask features, removing the spacer layer from the gate electrode material layer between the mask features, and etching the gate electrode material layer and dielectric material layer using the hard mask features as an etch mask to obtain gate electrode structures. A semiconductor device including first and second gate electrode structures, each covered by a cap layer that comprises a mask material surrounded at the sidewalls thereof by a spacer material different from the mask material, and the distance between the first and second electrode structures is at most 100 nm.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer.

Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.

Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.

Abstract: The production apparatus includes a shower head electrode, a susceptor for supporting a growth substrate, a first gas supply pipe, and a second gas supply pipe. The first gas supply pipe has at least one first gas exhaust outlet and supplies an organometallic gas containing Group III metal as a first gas, and the second gas supply pipe supplies a gas containing nitrogen gas as the second gas. The distance between the shower head electrode and the susceptor is greater than the distance between the first gas exhaust outlet of the first gas supply pipe and the susceptor.

Abstract: Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal.

Abstract: A mask for forming a semiconductor layer and a semiconductor device manufactured using the same. The mask for forming a semiconductor layer includes oblique openings. Since a semiconductor layer is formed through one or more openings, it is possible to suppress generation of threading dislocation in a vertical direction from a growth surface of a heterogeneous substrate. The oblique openings are formed by stacking a growth blocking layer on the substrate, followed by dry etching the growth blocking layer, with the substrate disposed in a tilted state.

Abstract: The present invention is a process of making a germanium-antimony-tellurium alloy (GST) or germanium-bismuth-tellurium (GBT) film using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony precursor is used as a source of antimony for the alloy film. The invention is also related to making antimony alloy with other elements using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony or silylbismuth precursor is used as a source of antimony or bismuth.

Abstract: Porous and/or curved nanofiber bearing substrate materials are provided having enhanced surface area for a variety of applications including as electrical substrates, semipermeable membranes and barriers, structural lattices for tissue culturing and for composite materials, production of long unbranched nanofibers, and the like. A method of producing nanofibers is disclosed including providing a plurality of microparticles or nanoparticles such as carbon black particles having a catalyst material deposited thereon, and synthesizing a plurality of nanofibers from the catalyst material on the microparticles or nanoparticles. Compositions including carbon black particles having nanowires deposited thereon are further disclosed.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: There is provided an apparatus for producing metal chloride gas, comprising: a source vessel configured to store a metal source; a gas supply port configured to supply chlorine-containing gas into the source vessel; a gas exhaust port configured to discharge metal chloride-containing gas containing metal chloride gas produced by a reaction between the chlorine-containing gas and the metal source, to outside of the source vessel; and a partition plate configured to form a gas passage continued to the gas exhaust port from the gas supply port by dividing a space in an upper part of the metal source in the source vessel, wherein the gas passage is formed in one route from the gas supply port to the gas exhaust port, with a horizontal passage width of the gas passage set to 5 cm or less, with bent portions provided on the gas passage.

Abstract: A semiconductor wafer comprises, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in this order, wherein both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: Described herein is a method for growing InN, GaN, and AlN materials, the method comprising alternate growth of GaN and either InN or AlN to obtain a film of InxGa1?xN, AlxGa1?xN, AlxIn1?xN, or AlxInyGa1?(x+y)N

Abstract: Disclosed is an apparatus and method for processing substrate, which facilitates to prevent a substrate form being damaged, wherein the apparatus comprises a process chamber; a substrate supporter for supporting at least one of substrates, wherein the substrate supporter is provided in the bottom of the process chamber; a chamber lid confronting with the substrate supporter, the chamber lid for covering an upper side of the process chamber; and a gas distributing part provided in the chamber lid, wherein the gas distributing part distributes source gas to a source gas distribution area on the substrate supporter, distributes reactant gas to a reactant gas distribution area which is separated from the source gas distribution area, and distributes purge gas to a space between the source gas distribution area and the reactant gas distribution area.

Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film of said electronic or photonic material on said substrate; and using a fluoropolymer to protect regions of said electronic or photonic material during a patterning process.

Abstract: The present invention provides a method of fabricating a vertical type light-emitting diode and a method of separating layers from each other. Crystalline rods are provided on a lower layer or a lower substrate. The crystalline rods comprise ZnO. A layer which constitutes light-emitting diode or a light-emitting diode structure is formed on the crystalline rods, and the lower substrate is separated therefrom. The crystalline rods are dissolved during the separation. The formation of the crystalline rods is achieved by the formation of a seed layer and selective growth based on the seed layer.

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.

Abstract: A silicon carbide epitaxial layer formed by a low concentration wide band gap semiconductor of a first conductivity type is formed on the surface of a silicon carbide substrate formed by a high concentration wide band gap semiconductor of the first conductivity type. A Schottky electrode is formed on the silicon carbide epitaxial layer. The interface between the Schottky electrode and the silicon carbide epitaxial layer is used as a Schottky interface. Plural impurity regions of a second conductivity type are disposed at predetermined intervals in a lateral direction, in the silicon carbide epitaxial layer, at a position in the lower portion of the Schottky electrode in the depth direction. Because of the shape of the impurity regions, any leak current can be suppressed without raising the ON-resistance.

Abstract: A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region.

Abstract: Large-scale manufacturing of gallium nitride boules using m-plane or wedge-shaped seed crystals can be accomplished using ammonothermal growth methods. Large-area single crystal seed plates are suspended in a rack, placed in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and crystals are grown ammonothermally. The orientation of the m-plane or wedge-shaped seed crystals are chosen to provide efficient utilization of the seed plates and of the volume inside the autoclave or high pressure apparatus.

Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.

Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer sequence which comprises an active region The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.

Abstract: Provided is a semiconductor device which increases a concentration around an emitter by arranging a lightly doped region (HNMLDD). When the semiconductor device is operated in a forward bias, a maximum common-emitter current gain is obtained in a forward-active region, such that signals are amplified and an unnecessary noise is decreased at the same time. Further, the semiconductor device of the invention further includes a field plate disposed on a substrate between the emitter and a base or/and the collector and the base, and configured to change a potential distribution of junctions between each of doped regions and raise a breakdown voltage of the junctions.

Abstract: A gate line is formed on a pixel region, and a plurality of wiring layers are formed on a frame region. Next, a gate insulating layer and a semiconductor material layer are formed to cover the wiring layers and the gate line. Next, a first resist is formed to cover a portion of the semiconductor material layer over the pixel region, and second resists are formed to individually cover portions of the gate insulating layer between adjacent pairs of the wiring layers. Next, portions of the semiconductor material layer exposed from the first and second resists and are etched by dry etching to form semiconductor layers of semiconductor elements.

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

Abstract: A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr2O3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.

Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.

Abstract: The invention provides a method for manufacturing a nitride semiconductor device that grows a multilayer film of a III-V group nitride semiconductor in a reaction furnace into which a III group element raw material gas and a V group element raw material gas are introduced, the method including: growing a first nitride semiconductor layer at a first raw material gas flow rate of the V group element raw material gas and a first carrier gas flow rate; and growing a second nitride semiconductor layer at a second raw material gas flow rate of the V group element raw material gas lower than the first raw material gas flow rate and a second carrier gas flow rate higher than the first carrier gas flow rate, wherein the first nitride semiconductor layer and the second nitride semiconductor layer are stacked.

Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.

Abstract: Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of Inx1Aly1Gaz1N (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of Inx2Aly2N (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of Inx3Aly3Gaz3N (x3+y3+z3=1, z3>0).

Abstract: A semiconductor device includes a first compound semiconductor material and a second compound semiconductor material on the first compound semiconductor material. The second compound semiconductor material comprises a different material than the first compound semiconductor material such that the first compound semiconductor material has a two-dimensional electron gas (2DEG). The semiconductor device further includes a buried field plate disposed in the first compound semiconductor material and electrically connected to a terminal of the semiconductor device. The 2DEG is interposed between the buried field plate and the second compound semiconductor material.

Abstract: A method of fabricating a semiconductor device includes: forming an epitaxial layer on a semiconductor substrate; forming a capping layer having a first thickness on the epitaxial layer; and oxidizing the capping layer in an oxygen atmosphere to form a first gate dielectric layer having a second thickness.

Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.

Abstract: A P+ type region, a p-type region, and a P? type region are disposed in a surface layer of a silicon carbide substrate base and are disposed in a breakdown voltage structure portion surrounding an active region to make up an element structure of Schottky junction. The p? type region surrounds the P+ type region and the p-type region to form a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode and an electrode pad have end portions positioned on the P+ type region and the end portion of the Schottky electrode is exposed from the end portion of the electrode pad. As a result, the region of the breakdown voltage structure portion can be made smaller while the active region can be made larger, and a semiconductor device is easily fabricated.