Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.

Abstract: The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate.

Abstract: A transient voltage suppressor and its manufacturing method are provided, which can easily control voltage withstanding characteristics of a Zener diode by analogizing growth of a buried layer by forming a portion of the buried layer by performing ion implantation on a first epitaxial layer and then forming the other portion of the buried layer while depositing a second epitaxial layer having the same impurity concentration with the first epitaxial layer, and which can improve a current distribution characteristic by forming a doping region in a ring shape to increase a current pass region by increasing a PN junction area of a Zener diode in a small area.

Abstract: P+ type regions and a p-type region are selectively disposed in a surface layer of a silicon carbide substrate base. The P+ type region is disposed in a breakdown voltage structure portion surrounding an active region. The P+ type region is disposed in the active region to make up a JBS structure. The p-type region surrounds the P+ type region to make up a junction termination (JTE) structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the P+ type region and the p-type region and this overhanging portion acts as a field plate. This enables the provision of a semiconductor device configured by using a wide band gap semiconductor capable of maintaining a high breakdown voltage with high reliability, and a method of fabricating thereof.

Abstract: A method of fabricating a gallium nitride (GaN)-based semiconductor device. The method includes preparing a GaN substrate having lower and upper surfaces; growing GaN-based semiconductor layers on the upper surface of the GaN substrate to form a semiconductor stack; forming a support substrate on the semiconductor stack; and separating the GaN substrate from the semiconductor stack. The separating of the GaN substrate includes irradiating a laser from the lower surface of the GaN substrate. The laser is transmitted through the lower surface of the GaN substrate and forms a laser absorption region inside a structure consisting of the GaN substrate and the semiconductor stack.

Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The variable resistance layer is provided above the first conductive layer. The electrode layer contacts an upper surface of the variable resistance layer. The first liner layer contacts the upper surface of the electrode layer. The stopper layer contacts the upper surface of the first liner layer. The second conductive layer is provided above the stopper layer. The first liner layer is made of a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer.

Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).

Abstract: Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material.

Abstract: A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.

Abstract: A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench. The second semiconductor layer is etched by filling the at least one trench with an etchant, and applying a voltage between the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and in the first semiconductor layer. The voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space charge region when the voltage is applied.

Abstract: The present invention aims to provide a sulfide semiconductor-forming coating liquid capable of easily forming a sulfide semiconductor having a large area, the sulfide semiconductor being useful as a semiconductor material for photoelectric conversion materials. The present invention also aims to provide a sulfide semiconductor thin film produced using the sulfide semiconductor-forming coating liquid; and a thin film solar cell. The present invention provides a sulfide semiconductor-forming coating liquid, the coating liquid containing a complex containing a metal element of group 15 of the periodic table and sulfur.

Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.

Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized. AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: A method for producing gallium nitride material, comprising the steps of: a) providing a substrate and forming a metal layer over the substrate; b) forming a transition layer over the metal layer, the transition layer being compositionally graded such that the composition of the transition layer at a depth (z) thereof is an Al concentration function f(z) of that depth; and c) forming a layer of gallium nitride material over the transition layer; wherein the Al compositional grading function f(z) of the transition layer grown in step b) has a profile including two plateaux at respective depths z1 and z2 where df(z1)/dz=df(z2)/dz=0, wherein the function decreases continuously between z1 and z2 with z2>z1.

Abstract: According to an embodiment, there is provided a method of fabricating an epitaxial wafer, which includes preparing a wafer in a susceptor; and growing an epitaxial layer on the wafer, wherein the growing of the epitaxial layer on the wafer includes supplying a raw material into the susceptor; growing the epitaxial layer on the wafer at a first growth rate; and growing the epitaxial layer on the wafer at a second growth rate higher than the first growth rate. According to an embodiment, there is provided a silicon carbide epitaxial wafer which includes a silicon carbide wafer; and a silicon carbide epitaxial layer on the silicon carbide wafer wherein a surface defect formed on the silicon carbide epitaxial layer is 1 ea/cm2 or less.

Abstract: A (000-1) C-plane of an n? type silicon carbide substrate having an off-angle ? in a <11-20> direction is defined as a principal plane, and a periphery of a portion of this principal surface layer defined as an alignment mark is selectively removed to leave the convex-shaped alignment mark. The alignment mark has a cross-like plane shape such that two rectangles having longitudinal dimensions tilted by 45 degrees relative to the <11-20> direction are orthogonal to each other. When a film thickness of a p? type epitaxial layer is Y; a width of the alignment mark parallel to the principal surface of the n? type silicon carbide substrate is X; and an off-angle of the n? type silicon carbide substrate is ?, an epitaxial layer is formed on an upper surface of the alignment mark such that Y?X·tan ? is satisfied.

Abstract: The invention relates to a method for manufacturing a single crystal of nitride by epitaxial growth on a support (100) comprising a growth face (105), the method comprising the steps of formation of a sacrificial bed (101) on the support (100), formation of pillars (102) on said sacrificial bed, said pillars being made of a material compatible with GaN epitaxial growth, growth of a nitride crystal layer (103) on the pillars, under growing conditions such that the nitride crystal layer does not extend down to the support in holes (107) formed between the pillars, and removing the nitride crystal layer from the support.

Abstract: A graphene nanomesh includes a sheet of graphene having a plurality of periodically arranged apertures, wherein the plurality of apertures have a substantially uniform periodicity and substantially uniform neck width. The graphene nanomesh can open up a large band gap in a sheet of graphene to create a semiconducting thin film. The periodicity and neck width of the apertures formed in the graphene nanomesh may be tuned to alter the electrical properties of the graphene nanomesh. The graphene nanomesh is prepared with block copolymer lithography. Graphene nanomesh field-effect transistors (FETs) can support currents nearly 100 times greater than individual graphene nanoribbon devices and the on-off ratio, which is comparable with values achieved in nanoribbon devices, can be tuned by varying the neck width. The graphene nanomesh may also be incorporated into FET-type sensor devices.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.

Abstract: A method for forming a GaN-containing semiconductor structure is provided. The method comprises a substrate is provided, a nucleation layer is formed above the substrate, a diffusion blocking layer is formed above the nucleation layer, a strain relief layer is formed above the diffusion blocking layer, and a semiconductor layer is formed above the strain relief layer, in which the diffusion blocking layer is deposited on the nucleation layer such that the diffusion blocking layer can prevent the impurities out-diffusion from the substrate.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first buffer layer, a second buffer layer, a n-type transistor structure, and a p-type transistor structure. The first buffer layer having a first germanium concentration is formed on a substrate. The second buffer layer having a second germanium concentration is formed on the substrate, the second germanium concentration being larger than the first germanium concentration. The n-type transistor structure is formed on the first buffer layer, and the p-type transistor structure is formed on the second buffer layer.

Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Abstract: A nanowire device and a method of making a nanowire device are provided. The device includes a plurality of nanowires functionalized with different functionalizing compounds. The method includes functionalizing the nanowires with a functionalizing compound, dispersing the nanowires in a polar or semi-polar solvent, aligning the nanowires on a substrate such that longitudinal axes of the nanowires are oriented about perpendicular to a major surface of the substrate, and fixing the nanowires to the substrate.

Abstract: A method of manufacturing a semiconductor device includes providing a doped layer containing a first dopant of a first conductivity type and forming a counter-doped zone in the doped layer in an edge area surrounding an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of the concentration of the first dopant.

Abstract: An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR absorbers heats an on-platform junction of each of a plurality of series-connected thermoelectric devices operating in a Seebeck mode, the devices producing a voltage indicative of the received IR. Other thermoelectric devices are used to cool the platform, and a pressure sensing arrangement is used to detect loss of vacuum or pressure leaks.

Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1?xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1?yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract: A method of growing a nitride semiconductor layer includes forming a plurality of nano-structures on a substrate, forming a first buffer layer on the substrate such that upper portions of each of the nano-structures are exposed, removing the nano-structures to form voids in the first buffer layer, and growing a nitride semiconductor layer on the first buffer layer including the voids.

Abstract: A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

Abstract: There are provided a fabricating method of a carbon nanotube-based field effect transistor having an improved binding force with a substrate and a carbon nanotube-based field effect transistor fabricated by the fabricating method. The method includes forming an oxide film on a substrate, forming a photoresist pattern on the oxide film, forming a metal film on the entire surface of the oxide film having the photoresist pattern, removing the photoresist by lifting off, adsorbing carbon nanotubes on the substrate from which the photoresist is removed, performing an annealing process to the substrate to which the carbon nanotubes are adsorbed, and removing the metal film. Since an adhesive strength between a substrate and carbon nanotubes increases, stability and reliability of a field effect transistor can be improved. If the field effect transistor is applied to a liquid sensor or the like, a lifespan of the sensor can be extended and reliability of a measurement result obtained by the sensor can be improved.

Abstract: Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers.

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.

Abstract: According to a manufacturing apparatus for semiconductor device according to an embodiment of the present invention, a reaction chamber includes a gas introduction unit and a deposition reaction unit. The gas introduction unit includes a gas introduction port for introducing process gas and a buffer unit into which the process gas is introduced from the gas introduction port. In the deposition reaction unit, deposition reaction is performed on a wafer by the process gas. A rectifying plate provided under an area at least a part of which is enclosed by the buffer unit supplies the process gas introduced from a side of the buffer unit in a horizontally dispersed state to an upper surface of the wafer in a rectified state.

Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: A method of manufacturing a semiconductor device includes growing a first GaN layer on a SiC substrate, and forming a second GaN layer on the first GaN layer, the second GaN layer being grown under such conditions that a ratio of a vertical growth rate to a horizontal growth rate is lower than that in the growth of the first GaN layer.

Abstract: III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer.

Abstract: A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.

Abstract: A semiconductor structure including a body-contacted finFET device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a SOI substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region. The method may further include forming a body contact fin contemporaneously with the finFET fins that is in contact with the body contact region, through which electrical contact to the body contact region is made.