Abstract: A large surface substrate (5, 5a) is Rf vacuum plasma treated with the help of an electrode arrangement (9) consisting of an even number of electrode strips (9a, 9b). At least one of the strips is Rf supplied at least two distinct loci (P1, P2) along the central axis (A) of the addressed strip (9a).

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of Si-containing material and/or Ge-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element.

Abstract: Plasma treatment apparatus and method for treatment of a surface of a substrate. A dielectric barrier discharge electrode structure is provided having a treatment space (5) and comprising a first electrode (2) and a second electrode (3), and a power supply (11) connected to the first electrode (2) and the second electrode (3) for generating an atmospheric pressure plasma in the treatment space (5). The plasma treatment apparatus further comprises a magnetic layer (6) provided on a surface of at least the first electrode (2). The first electrode (2) is arranged to receive, in operation, the substrate (1) to be treated and a mask device (7) in contact with the substrate (1), the mask device (7) interacting with the magnetic layer (6).

Abstract: Polymer is removed from the backside of a wafer held on a support pedestal in a reactor using an arcuate side gas injection nozzle extending through the reactor side wall with a curvature matched to the wafer edge and supplied with plasma by-products from a remote plasma source.

Abstract: A method of processing a workpiece in a plasma reactor having an electrostatic chuck for supporting the workpiece within a reactor chamber, the method including circulating a coolant through a refrigeration loop that includes an evaporator inside the electrostatic chuck, while pressurizing a workpiece-to-chuck interface with a thermally conductive gas, sensing conditions in the chamber including temperature near the workpiece and simulating heat flow through the electrostatic chuck in a thermal model of the chuck based upon the conditions.

Abstract: A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.

Abstract: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier layer on at least the bottom surface, the side surface, and a part of the top surface, removing the diffusion barrier layer from at least a part of the bottom surface, depositing a seed layer on at least the part of the bottom surface and the diffusion barrier layer, and depositing an electrode layer on the seed layer.

Abstract: This invention relates to a method for conducting an etching process which uses a plasma of a process gas. This etching process is conducted on a wafer W including a substrate 101, an underlying film 102, 103 formed on the substrate, and a film 104 to be etched that is formed on the underlying film. A main etching gas formed up of a chlorine-containing gas and an oxygen-containing gas, and a nitrogen-containing gas are used as the process gas. In this etching method, etching is conducted under a condition that an N2+/N2 intensity ratio of N2+ to N2, derived from emission spectra of the plasma, is at least 0.6.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract: Gas mixtures which comprise acids like HF, HCl or HBr and other constituents, especially gas mixtures which comprise or consist of carboxylic acid fluorides, C(O)F2 or phosphorous pentafluoride and HCl and optionally HF, can be separated by ionic liquids. The process is performed reversibly. Ionic liquids are applied the anion of which corresponds to a stronger acid than the acid to be removed. Highly purified products, for example, highly purified carbonyl fluoride can be obtained.

Abstract: This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum oxide, silicon carbide and mixtures thereof. The process is related to the important applications in the cleaning or etching process for semiconductor deposition chambers and semiconductor tools, devices in a micro electro mechanical system (MEMS), and ion implantation systems. Methods of forming XeF2 by reacting Xe with a fluorine containing chemical are also provided, where the fluorine containing chemical is selected from the group consisting of F2, NF3, C2F6, CF4, C3F8, SF6, a plasma containing F atoms generated from an upstream plasma generator and mixtures thereof.

Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.

Abstract: A plasma etching method includes disposing first electrode and second electrodes; preparing a part in a processing chamber; supporting a substrate by the second electrode to face the first electrode; vacuum-evacuating the processing chamber; supplying a first processing gas containing an etchant gas into a processing space between the first electrode and the second electrode; generating a plasma of the first processing gas in the processing space by applying a radio frequency power to the first electrode or the second electrode; and etching a film on the substrate by using the plasma. Further, a resist modification process includes vacuum-evacuating the processing chamber; supplying a second processing gas into the processing space; generating a plasma; and applying a negative DC voltage to the part, the part being disposed away from the substrate in the processing chamber and injecting electrons discharged from the part into the resist pattern on the substrate.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.

Abstract: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.

Abstract: A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silicon nanostructures in the etching area; immersing the silicon substrate in a second etching solution thereby resulting in the silicon nanostructures being side-etched and detached from the silicon substrate, thus forming the silicon trench.

Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.

Abstract: To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.

Abstract: The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step.

Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.

Abstract: A method and apparatus are provided to form spacer materials adjacent substrate structures. In one embodiment, a method is provided for processing a substrate including placing a substrate having a substrate structure adjacent a substrate surface in a deposition chamber, depositing a spacer layer on the substrate structure and substrate surface, and etching the spacer layer to expose the substrate structure and a portion of the substrate surface, wherein the spacer layer is disposed adjacent the substrate structure. The spacer layer may comprise a boron nitride material. The spacer layer may comprise a base spacer layer and a liner layer, and the spacer layer may be etched in a two-step etching process.

Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.

Abstract: A liquid composition free from N-alkylpyrrolidones and hydroxyl amine and its derivatives, having a dynamic shear viscosity at 50° C. of from 1 to 10 mPas as measured by rotational viscometry and comprising based on the complete weight of the composition, (A) of from 40 to 99.95% by weight of a polar organic solvent exhibiting in the presence of dissolved tetramethylammonium hydroxide (B) a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) of from 0.05 to <0.5% of a quaternary ammonium hydroxide, and (C) <5% by weight of water; method for its preparation, a method for manufacturing electrical devices and its use for removing negative-tone and positive-tone photoresists and post etch residues in the manufacture of 3D Stacked Integrated Circuits and 3D Wafer Level Packagings by way of patterning Through Silicon Vias and/or by plating and bumping.

Abstract: A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching the protective film. Organic material containing C and F groups on the pad may be removed by heating with molecular vibration and/or microwaves, which may substantially prevent and/or minimize corrosion.

Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant and a silicon source. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during the process. In another embodiment, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. In another embodiment, a method for cleaning a process chamber is provided which includes exposing the interior surfaces with a chamber clean gas that contains an etchant and a silicon source.

Abstract: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.

Abstract: Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.

Abstract: A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier.

Abstract: Methods of forming a 3D structure in a substrate are disclosed. A layer of resist is deposited on the substrate. The layer of resist is patterned to define an edge at a predetermined location. The resist is reflowed to form a tapered region extending from the etch. Both the reflowed resist and the substrate are concurrently etched to transfer the tapered profile of the reflowed resist into the underlying substrate to form an angled surface. The etching is discontinued before all of the resist is consumed by the etching.

Abstract: The present invention provides a method for manufacturing a resistance change element that can reduce occurrence of corrosion without increasing a substrate temperature. A laminate film that includes a high melting-point metal film and a metal oxide film, is etched using a mask under a plasma atmosphere formed using any one of a mixture gas formed by adding at least one gas selected from the group consisting of Ar, He, Xe, Ne, Kr, O2, O3, N2, H2O, N2O, NO2, CO and CO2 to at least one kind of gasified compound selected from alcohol and hydrocarbon or the gas compound.

Abstract: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using an etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a dry plasma etching process formed from a process composition comprising NF3.

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract: A method of forming a damascene structure comprises preparing a film stack on the substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a first mask layer formed on the silicon oxide layer. A trench pattern is created in the first mask layer. The trench pattern in the first mask layer is transferred to the silicon oxide layer, and then the first mask layer is removed. A second mask layer is formed on the silicon oxide layer. A via pattern is formed in the second mask layer. The via pattern is transferred to the SiCOH-containing layer using a first etching process, and then the second mask layer is removed. The trench pattern is transferred to the SiCOH-containing layer using a second etching process with plasma formed from a process composition comprising NF3.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer, forming a second hard mask over the resulting substrate structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer, planarizing the second hard mask until the first pad layer is exposed, removing the first pad layer and the spacers, and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.

Abstract: The thin-film patterning method for a magnetoresistive device comprises forming a functional layer on a substrate; forming a first mask layer above the functional layer; forming a patterned resist on the first mask layer; etching the first mask layer by using the resist; removing the resist; forming a second mask layer by atomic layer deposition, the second mask layer covering a step defined by an edge of the first mask layer; dry-etching the second mask layer in a thickness direction of the substrate so as to leave the second mask layer on a side face of the step; removing the first mask layer so as to expose the functional layer under the first mask; and dry-etching the functional layer by using the second mask layer.

Abstract: A substrate (16) is machined to form, for example, a via. The substrate is in a chamber (15) within which the gaseous environment is controlled. The machining laser beam (13) is delivered with control of parameters such as pulsing parameters to achieve desired effects. The gaseous environment may be controlled to control integral development of an insulating lining for a via, thereby avoiding the need for downstream etching and oxide growth steps. Also, machining may be performed in multiple passes in order to minimize thermal damage and to achieve other desired effects such as a particular via geometry.

Abstract: The present invention fabrication method and apparatus provides a method of creating holographic configurations in a specific pattern in glass panels using a laser that does not use chemicals or chemical solutions.

Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.

Abstract: A substrate inspection method includes forming a conductive thin film on a surface of an inspection target substrate with a pattern formed thereon, generating an electron beam and irradiating the substrate having the thin film formed thereon with the electron beam, detecting at least any of secondary electrons, reflected electrons and backscattered electrons released from the surface of the substrate and outputting signals constituting an inspection image, and selecting at least any of a material, a film thickness and a configuration for the thin film, or at least any of a material, a film thickness and a configuration for the thin film and an irradiation condition with the electron beam according to an arbitrary inspection image characteristic so that an inspection image according to an inspection purpose can be obtained.

Abstract: A contact hole, after hole etching, is subjected to light etching using a process gas containing a fluorocarbon-based gas and oxygen, with the oxygen being enriched, under condition without applying bias. Then, reaction products (5) having C—F bond and adhered to an interior of a hole (3) are removed using plasma treatment. After that, deposits (4) that have been left at a hole bottom are removed by wet processing. Then, a conductive material is buried in the hole to form a contact plug (7).

Abstract: The method of fabricating semiconducting nanowires having a desired wire diameter includes providing pre-fabricated semiconducting nanowires, at least one pre-fabricated nanowire having a wire diameter larger than the desired wire diameter (d); and reducing the wire diameter of the at least one pre-fabricated nanowire by etching. The etching is induced by light which is absorbed by the at least one pre-fabricated nanowire. The spectrum of the light is chosen such that the absorption of the at least one pre-fabricated nanowire is significantly reduced when the at least one pre-fabricated nanowire reaches the desired wire diameter.

Abstract: A method to fabricate an optical scattering probe and the method includes the steps of a) depositing an conductive layer on a substrate followed by depositing a noble metal layer on top of the conductive layer and then an aluminum layer on top the noble metal layer; b) anodizing the aluminum layer to form a porous aluminum oxide layer having a plurality of pores; and c) etching the plurality of pores through the aluminum oxide layer and the noble metal layer for forming a nano-hole array. In a preferred embodiment, the step of etching the plurality of pores through the aluminum oxide layer and the noble metal layer further comprising a step of widening the pores followed by removing the aluminum oxide layer for forming a plurality of noble metal column on top of the conductive layer.

Abstract: A residue-removing solution for removing residues present on semiconductor substrates after dry etching and/or ashing, the residue-removing solution comprising a Cu surface protective agent including: at least one compound selected from compounds (1), (2) and (3) each having as a basic skeleton a five-membered or six-membered heteratomic structure as defined herein; a compound capable of forming a complex or chelate with Cu (copper); and water. Further, the residue-removing solution has a pH of 4 to 9.

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: The surface of a material is textured and by exposing the surface to pulses from an ultrafast laser. The laser treatment causes pillars to form on the treated surface. These pillars provide for greater light absorption. Texturing and crystallization can be carried out as a single step process. The crystallization of the material provides for higher electric conductivity and changes in optical and electronic properties of the material. The method may be performed in vacuum or a gaseous environment. The gaseous environment may aid in texturing and/or modifying physical and chemical properties of the surfaces. This method may be used on various material surfaces, such as semiconductors, metals and their alloys, ceramics, polymers, glasses, composites, as well as crystalline, nanocrystalline, polycrystalline, microcrystalline, and amorphous phases.

Abstract: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.

Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.