Abstract: A resist pattern is formed at an outermost peripheral end of the surface of a wafer. Thereafter, the back of the wafer is back-etched using chemicals to thin the wafer. A passivation film is left behind only at scribe lines for separating semiconductor chips located at the outermost peripheral end of the wafer surface and thereafter the wafer is back-etched.

Abstract: When an electronic device having an element including an insulating metal oxide film is manufactured, either dry cleaning or a cleaning solution containing substantially no water is used in a cleaning step conducted after a step of forming the insulating metal oxide film.

Abstract: A semiconductor wafer cleaning formulation, including 1-21% wt. fluoride source, 20-55% wt. organic amine(s), 0.5-40% wt. nitrogenous component, e.g., a nitrogen-containing carboxylic acid or an imine, 23-50% wt. water, and 0-21% wt. metal chelating agent(s). The formulations are useful to remove residue from wafers following a resist plasma ashing step, such as inorganic residue from semiconductor wafers containing delicate copper interconnecting structures.

Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.

Abstract: By exposing precursor molecules traveling in a molecular beam to a narrow bandwidth laser beam (hu) tuned to a vibrational resonance frequency of the molecules and aimed orthogonal to the molecular beam (FIG. 6A), only those molecules having velocity (va) along trajectory (A) orthogonal to the laser beam are excited, becoming several orders of magnitude more reactive, affording a high degree of control over precise locations of reactions of molecules. Controlling a reaction on a surface of a solid substrate, includes; (a) obtaining a precursor molecule that includes (or can be reacted to form) species to be reacted with the substrate; (b) creating a molecular beam (eg., supersonic) that includes the precursor molecule; (c) vibrationally exciting the molecule with the laser beam tuned to a vibrational resonance frequency of the molecule; and (d) causing the exciting molecule to impinge on the substrate, enabling reactions (deposition, etching . . . ) of the species with the substrate.

Abstract: A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.

Abstract: An apparatus for shaping and encapsulating near edge regions of a semiconductor wafer is described. A housing of the apparatus has a slot for receiving an edge of a wafer affixed on a rotatable chuck. At least one plasma source connected to the housing generates a flow of reactive gas towards the edge of the wafer. A channel in the housing directs a flow of diluent/quenching gas onto the wafer in close proximity to an exhaust channel for exhausting of the diluent/quenching gas and the reactive gas away from the wafer. The apparatus may also provide a plurality of plasma sources, for example, plasma sources for selectively etching of a polymer on the wafer, etching of silcon dioxide on the wafer and depositing an encapsulating silicon dioxide layer on the wafer.

Abstract: A structure having pores includes a first layer containing alumina, a second layer that includes at least one of Ti, Zr, Hf, Nb, Ta, Mo, W and Si, and a third layer with electrical conductivity, in this order, wherein the first and second layers have pores.

Abstract: The present invention relates to a scribing method for wafers (11), wherein a defined beam (12) is directed onto the wafer (11) by means of a beam generator means (10) so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount (31) and a beam generator means (10) by means of which at least one defined beam can be directed onto the wafer (11). The inventive method is distinguished by the by the further step of generating a first radiation pulse having a predeterminable energy density and used to create a comparatively deep pit (18) in the wafer (11). The inventive wafer scribing means is distinguished by the provision that a radiation pulse can be generated by means of which a comparatively deep pit (18) can be created in the wafer (11).

Abstract: A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

Abstract: A plasma etching method and apparatus in which a processing gas is supplied from a shower plate arranged on an electrode opposed to an electrode for generating a plasma or a sample toward the sample center, and the gas is transformed into a plasma thereby to etch the sample. RF power is applied between a sample stage and the electrode to apply the energy to charged particles in the plasma to thereby etch the sample. In the process, apart from the incidence of the charged particles to the sample, the charged particles enter also the shower plate of the electrode by application of the RF power. The charged particles entering the processing gas supply holes of the shower plate are neutralized to prevent abnormal discharge on the shower plate and consequently suppress the generation of foreign matter.

Abstract: A first interlayer insulating film (3) having low dielectric constant is formed on an underlying insulating film (2) and a second interlayer insulating film (4) is formed on the first interlayer insulating film (3). Subsequently, a photoresist (5) having a pattern with openings above regions in which copper wirings are to be formed is formed on the second interlayer insulating film (4). Using the photoresist (5) as an etching mask, the second interlayer insulating film (4) and the first interlayer insulating film (3) are etched, to form a recess (6). Next, an ashing process using oxygen gas plasma (7) is performed, to remove the photoresist (5). This ashing process is performed under a plasma forming condition that the RF power is 300 W, the chamber pressure is 30 Pa, the oxygen flow is 100 sccm and the substrate temperature is 25° C.

Abstract: A method and a suitable device for carrying out this method is proposed, for etching a substrate (10), especially a silicon element, with the aid of an inductively coupled plasma (14). For this purpose, a high frequency electromagnetic alternating field is generated, which produces an inductively coupled plasma (14) from reactive particles in a reactor (15). In this connection, the inductively coupled plasma (14) comes about by the action of the high frequency electromagnetic alternating field upon a reactive gas. Furthermore, a device, in particular a magnetic field coil (21) is provided which produces a static or timewise varying magnetic field between the substrate (10) and the ICP source (13). For this, the magnetic field is oriented in such a way that its direction is at least approximately or predominantly parallel to the direction defined by the line connecting the substrate (10) and the inductively coupled plasma (14).

Abstract: 200 mm and 300 mm wafers are processed in vacuum plasma processing chambers that are the same or have the same geometry. Substantially planar excitation coils having different geometries for the wafers of different sizes excite ionizable gas in the chamber to a plasma by supplying electromagnetic fields to the plasma through a dielectric window at the top of the chamber. Both coils include plural symmetrical, substantially circular turns coaxial with a center point of the coil and at least one turn that is asymmetrical with respect to the coil center point. Both coils include four turns, with r.f. excitation being applied to the turn that is closest to the coil center point. The turn that is third farthest from the center point is asymmetric in the coil used for 200 mm wafers. The two turns closest to the coil center point are asymmetric in the coil used for 300 mm wafers.

Abstract: A plasma processing chamber including a slip cast part having a surface thereof exposed to the interior space of the chamber. The slip cast part includes free silicon contained therein and a protective layer on the surface which protects the silicon from being attacked by plasma in the interior space of the chamber. The slip cast part can be made of slip cast silicon carbide coated with CVD silicon carbide. The slip cast part can comprise one or more parts of the chamber such as a wafer passage insert, a monolithic or tiled liner, a plasma screen, a showerhead, dielectric member, or the like. The slip cast part reduces particle contamination and reduces process drift in plasma processes such as plasma etching of dielectric materials such as silicon oxide.

Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.

Abstract: An improved method for etching a substrate that reduces the formation of pillars is provided by the present invention. In accordance with the method, the residence time of an etch gas utilized in the process is decreased and the power of an inductively coupled plasma source used to dissociate the etch gas is increased. A low bias RF voltage is provided during the etching process. The RF bias voltage is ramped between different bias levels utilized during the etch process. An inductively coupled plasma confinement ring is utilized to force the reactive species generated in the inductively coupled plasma source over the surface of the substrate. These steps reduce or eliminate the formation of pillars during the etching process.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, shutting off the power, discontinuing the N2 flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

Abstract: It is an object to provide a laser apparatus, a laser irradiating method and a manufacturing method of a semiconductor device that can perform uniform a process with a laser beam to an object uniformly. The present invention provides a laser apparatus comprising an optical system for sampling a part of a laser beam emitted from an oscillator, a sensor for generating an electric signal including fluctuation in energy of the laser beam as a data from the part of the laser beam, a means for performing signal processing to the electrical signal to grasp a state of the fluctuation in energy of the laser beam, and controlling a relative speed of an beam spot of the laser beam to an object in order to change in phase with the fluctuation in energy of the laser beam.

Abstract: A method of fabricating a semiconductor device capable of increasing the selectivity of a low dielectric constant insulator film to an etching mask layer such as an etching stopper film without increasing the thickness of the etching mask layer is obtained. This method of fabricating a semiconductor device comprises steps of forming a first insulator film including a polymer film containing C and H, forming a first etching mask layer containing Si on a prescribed region of the first insulator film and plasma-etching the first insulator film with etching gas containing nitrogen and monochromated ion energy having a narrow energy width through a mask of the first etching mask layer.

Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.

Abstract: The present invention provides a nano-structure which can be applied to various high-function devices. The nano-structure includes an anodically oxidized layer having a plurality of kinds of pores.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a mask to form in the insulating film an opening at which part of the surface of the conductive pattern is exposed; forming an antioxidant layer on the part of surface of the conductive pattern exposed while removing the resist pattern; and depositing a conductive film on the conductive pattern from which the antioxidant layer has been removed.

Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.

Abstract: To reduce the edge roll off in a semiconductor wafering process, the wafer (110) is subject to a plasma etch with an edge underetch. The edge underetch is achieved by means of a wafer holder (410) that emits gas towards the wafer (e.g. a gas vortex) to draw the wafer towards the holder's body (460). The plasma impinges on the wafer surface (110.1) opposite to the body. Some of the gas emitted by the holder wraps around the wafer edge and dilutes the etchant near the wafer edge. Consequently, the etch proceeds slower near the edge (the edge is underetched). In some embodiments, the wafer is rotated around an axis (440) passing through the wafer to increase the underetch.

Abstract: A dry processing apparatus includes a processing chamber provided with a measurement window having a reflection portion which totally reflects light on the side of an inner surface thereof and a transmission portion. When a layer is not deposited, measurement light is irradiated so that the light is totally reflected by the reflection portion. A deviation between the measurement light reflected by a surface of the deposited layer and the measurement light reflected by the reflection portion is measured to determine a thickness of the deposited layer. A quantity of light reflected by the surface of the deposited layer is compared with the light quantity in case where irregularities are not formed in the surface of the deposited layer to evaluate a state of irregularities of the surface. The thickness of the deposited layer and a state of the surface of the layer are monitored separately.

Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.

Abstract: A method for removing a carbon-containing polysilane from a semiconductor substrate without stripping the polysilane during manufacture of a semiconductor device, the method entailing the steps in the following order of coating a carbon-containing polysilane on a semiconductor substrate and coating a resist on the polysilane; patterning the resist with exposure and development; transferring the pattern from the resist to the polysilane using an etch process selective to the resist; stripping the resist; transferring the pattern from the polysilane to a hardmask using an etch selective to the hardmask; subjecting the polysilane to thermal or plasma/thermal oxidation to convert the polysilane to silicon oxide; and etching the substrate and stripping off the hardmask.

Abstract: A heterojunction structure has an AlxGa1−xAs layer (0<x≦1), on which an AlyGa1−yAs layer (0≦y≦1 and y<x) is provided and having a band gap energy smaller than that of the AlxGa1−xAs layer and a valence band energy edge higher than that of the AlxGa1−xAs layer. When the AlyGa1−yAs layer is selectively etched, an Au electrode film is formed on a surface of the AlyGa1−yAs layer outside an etching region, a resist pattern is formed covering the Au electrode film and leaving exposed the etching region, and the AlyGa1−yAs layer is selectively removed by etching while irradiating with light, using an etching solution having a Fermi level higher than that of the AlyGa1−yAs layer.

Abstract: A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).

Abstract: A method of anisotropic etching of structures in a semiconductor body, in particular of recesses in a silicon body (18) exactly defined laterally by an etching mask, by using a plasma (28) is proposed. An ion acceleration voltage induced in particular by a high-frequency AC voltage is applied to the semiconductor body at least during an etching step having a predefined duration. The duration of the etching step is further subdivided into at least two etching segments between which the ion acceleration voltage applied is modified each time. Preferably two etching segments are provided, a higher acceleration voltage being used during the first etching segment than during the second etching step. The length of the first etching segment can furthermore be determined dynamically or statically during the etching steps using a device for the detection of a polymer breakdown.

Abstract: In power supply and a semiconductor making apparatus and a semiconductor fabricating method using the same, an abnormality can be detected when an offset occurs in a part constituting a closed-loop system of high-frequency power supply or dc power supply for a semiconductor making apparatus. Power supply for receiving a power value setting signal to set strength of power and a power on/off instruction to set on or off of outputting of the power interrupts the supply of the power even in a state in which a subsequent power on/off instruction is on if a power sense signal according to a value obtained by sensing the power exceeds a predetermined value when the power on/off instruction is off.

Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.

Abstract: To provide for increased differentiation in etch rates, sonication may be used during etching. Such sonication may alter the relative etch rates of portions of a desired layer.

Abstract: Disclosed are a processing method and apparatus for removing a native oxide film from the surface of a subject to be treated. In this method and apparatus, gas generated from N2, H2 and NF3 gases is reacted with the surface of the subject to degenerate the native oxide film into a reactive film. If the subject is heated to a given temperature, the reactive film is sublimated and thus the native oxide film is removed. Plasma is generated from the N2 and H2 gases and then activated to form an activated gas species. The NF3 gas is added to the activated gas species to generate an activated gas of these three gases. In the step of forming the reactive film, the subject is cooled to not higher than a predetermined temperature by a cooling means. In the step of sublimating the reactive film, the subject is lifted up to a predetermined heating position.

Abstract: A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.

Abstract: A method of processing a substrate 30 comprises exposing the substrate 30 to an energized process gas to etch features 67 on the substrate 30 and exposing the substrate 30 to an energized cleaning gas to remove etchant residue 70 and/or remnant resist 60 from the substrate 30. To enhance the cleaning process, the substrate 30 may be treated before, during or after the cleaning process by exposing the substrate 30 to an energized treating gas comprising a halogen species.

Abstract: For allowing processing of a material into an intended three-dimensional configuration having different processed depths while suppressing an influence exerted on a processed configuration by a configuration of a transparent portion, a processing device includes an SR light source 1 for emitting SR light, an X-ray mask having a transparent portion of a predetermined configuration for passing the X-rays emitted from the SR light source 1, and exposure stage 3 for oscillating the X-ray mask and the material relatively to each other in accordance with a movement pattern determined based on the processing configuration of the processing material for moving the X-ray mask and the material relatively to each other and thereby oscillating the region where the material is irradiated with the X-ray passed through the transparent opening.

Abstract: A method is provided for surface treating where the environmental load is small. The surface treating method includes a cluster produced in a gas phase and bonded by a first molecule and a second molecule by means of an intermolecular force. At least a part of the internal energy released in producing the cluster is utilized whereby the first molecule contained in the cluster has a higher reactivity than that of the first molecule that is not bonded to the second molecule. The surface of the member to be treated is treated in a gas phase with the cluster containing the first molecule having a higher reactivity.

Abstract: The surface of a substrate having a transmission index is irradiated with a beam of atoms having a slow enough velocity to be adsorbed on the substrate. A laser beam whose frequency is detuned by 1 to 10 gigahertz from the resonant frequency of the atoms is projected onto the substrate at an angle, producing total reflection. The atom beam is reflected at regions at which an intensity of an evanescent wave emitted at this time from the substrate surface is high, and adsorbed at regions where the intensity is low, thereby achieving atomic fabrication patterns on a substrate. By using a hologram image to create the pattern, it is possible to form an atomic fabrication patterns in which the size of features correspond to the diameter of the laser beam, enabling the size to be reduced to the diffraction limit of the laser light.

Abstract: After coating a resist for silylation on the semi-conductor substrate, the resist is exposed with a pattern. Then the silylation process is performed to form a silylated layer and the silylated layer is hardened with performing an electron beam processing or a ultra-violet ray processing. After that, an etching is performed with using the hardened silylated layer as a mask and the wiring step is taken without removing the hardened silylated layer as a stopper for chemical mechanical polishing. With this embodiment, the patterning steps of an insulation film can be simplified.

Abstract: There is provided a method for preventing the deterioration of an electrode caused by the built up of deposits in openings. Gas is supplied to each of the openings 24 in order to prevent deposits from adhering to the openings before or after the etching treatment.

Abstract: A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.

Abstract: A method is described for improving the exposure focus for modern steppers used in the lithography of semiconductor substrates such as wafers. A wafer is sawed from a semiconductor ingot in a particular direction relative to a reference point on the ingot. As a result of the sawing, a series of raised and recessed formations manifest on the surface of the wafer. After various layers have been added to the wafer and the photoresist layer is ready to be removed, the wafer is aligned with the stepper so that a dynamic focus area of the stepper is aligned with the formations and/or the sawing direction. Such alignment improves the critical dimension control and reduces variability in printing small geometry features during lithography, resulting in higher yields.

Abstract: An apparatus for controlling wafer temperature in a plasma etcher during a plasma-on state and a method for using such apparatus are disclosed. In the apparatus, an additional temperature sensor for sensing the wafer backside temperature and a second flow control valve of a mass flow controller are utilized such that the second flow control valve may be opened to increase the flow of cooling gas through the wafer backside when a temperature rise is detected by the temperature sensor. When the wafer temperature detected is too high, i.e., higher than 65° C., the second flow control valve is opened to increase the flow of helium cooling gas from a nominal rate of 13 sccm by at least 50%. When the temperature of the wafer detected is below 65° C., the flow of the helium cooling gas can be reduced by closing the second flow control valve.

Abstract: A method of eliminating charging resulting from plasma processing a semiconductor wafer comprising the steps of plasma processing the semiconductor wafer in a manner that may result in topographically dependent charging and exposing, during at least a portion of a time in which the semiconductor wafer is being plasma processed, the semiconductor wafer to particles that remove charge from the semiconductor wafer and reduce topographically dependent charging.

Abstract: An apparatus and method for decontaminating chemical and biological agents using the reactive properties of both the single atomic oxygen and the hydroxyl radical for the decontamination of chemical and biological agents. The apparatus is self contained and portable and allows for the application of gas reactants directly at the required decontamination point. The system provides for the use of ultraviolet light of a specific spectral range to photolytically break down ozone into molecular oxygen and hydroxyl radicals where some of the molecular oxygen is in the first excited state. The excited molecular oxygen will combine with water vapor to produce two hydroxyl radicals.

Abstract: A method for manufacturing integrated circuits uses an atmospheric magnetic mirror plasma etching apparatus to thin a semiconductor wafer. In addition the process may, while thinning, both segregate and expose through-die vias for an integrated circuit chip. To segregate, the wafer may be partially diced. Then, the wafer may be tape laminated. Next, the backside of the wafer may be etched. As the backside material is removed, the partial dicing and through-die vias may be exposed. As such, the method reduced handling steps and increases yield. Furthermore, the method may be used in association with wafer level processing and flip chip with bump manufacturing.

Abstract: A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.