Abstract: A method for processing semiconductor wafers and similar articles has an ozone remover connected to a processing chamber. The ozone remover has a light chamber surrounded by reflectors. Ozone and other processing gases and vapors flow out of the processing chamber and into the light chamber. Ultraviolet lights in the ozone remover flood the light chamber with ultraviolet light, converting ozone into oxygen. The amount of ozone released into the environment is reduced. A recirculation line receives the gases and vapors flowing out of the ozone remover. Oxygen and any remaining ozone are separated from other gas and vapor components and are recycled back to an ozone generator, to increase the ozone generator efficiency in supplying the machine with ozone.

Abstract: A method for manufacturing a semiconductor device having a movable unit includes a step of forming an SOI substrate that includes a semiconductor substrate, an insulating layer, and a semiconductor layer such that the insulating layer is located between the semiconductor layer and the semiconductor substrate. The method further includes a step of dry etching the semiconductor layer to form a trench with a charge prevented from building up on a surface of the insulating layer that is exposed at a bottom of the trench during the dry etching. The method further includes a step of dry etching a sidewall defining the trench at a portion adjacent to the bottom of the trench to form the movable unit. The later dry etching is performed with a charge building up on the surface of the insulating layer such that etching ions strike to etch the portion of the sidewall.

Abstract: A method is provided for manufacturing an integrated circuit including a substrate with a gate layer and a gate dielectric provided on the substrate. The gate layer is formed into a gate using a process that imposes a charge in the gate dielectric. The substrate, gate, and gate dielectric are irradiated to discharge the charge across the gate dielectric.

Abstract: An oxide for use in a bolometer with an oxide thin-film formed is manufactured on an insulating substrate. Metal organic compound is dissolved in solvent to form solution during manufacturing the oxide thin-film. The solution is applied on the insulating substrate, and the applied solution is dried. A bond between carbon and oxygen is cut and decomposed by irradiating a laser ray with wavelength of 400 nm or less. A generated oxide is crystallized.

Abstract: Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photoresist in a conventional PR strip apparatus. In addition, the methods can shorten waiting time and maintain consistency in the process by performing the PR strip and cleaning at the same time in the same chamber. The resultant devices have lower via contact resistance and its deviation, as compared to the conventional PR strip and ACT wet cleaning.

Abstract: A semiconductor dry etching process that provides deep, smooth (RMS of less than approximately 5 nm), and vertical etching of InP-based materials with ICP RIE using a chlorinated plasma with the addition of hydrogen gas. Inert gases such as nitrogen, argon, or both may also be included. To produce relatively high anisotropy with exceptionally smooth surfaces, the amount of hydrogen gas added preferably exceeds the volumetric measure of chlorinated gas in standard cubic centimeter per minute (sccm); at a ratio of greater than 1:1. The present invention provides an improved dry etching process for InP-based semiconductor materials that yields deep, vertical etch profiles with improved surface smoothness (i.e., morphology) and high manufacturing etch rates.

Abstract: The present invention relates to a scribing method for wafers (11), wherein a defined beam (12) is directed onto the wafer (11) by means of a beam generator means (10) so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount (31) and a beam generator means (10) by means of which at least one defined beam can be directed onto the wafer (11).

Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.

Abstract: Disclosed is a manufacturing method of a semiconductor device which is intended to prevent occurrence of tapering of the shape of a gate electrode edge portion as has been deemed to be a problem at high-selectivity overetching process steps using a gas of HBr/O2 based gas.

Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.

Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

Abstract: A photolithographic fabrication method for a microstructure on a substrate, in particular interconnects of a DRAM, includes a first exposure with at least one alternating phase mask. Then, at least one postexposure is carried out after the first exposure with a trimming mask. The trimming mask has at least two trimming openings for producing at least one alternating phase shift. Postexposure even of very small parts of microstructures is thus possible, so that the entire microstructure can be arranged in a space-saving manner on the substrate.

Abstract: A first film is formed on a semiconductor substrate, the first film being made of material having a different etching resistance from silicon carbide. A second film of hydrogenated silicon carbide is formed on the first film. A resist film with an opening is formed on the second film. By using the resist mask as an etching mask, the second film is dry-etched by using mixture gas of fluorocarbon gas added with at least one of SF6 and NF3. The first film is etched by using the second film as a mask. A semiconductor device manufacture method is provided which utilizes a process capable of easily removing an etching stopper film or hard mask made of SiC.

Abstract: A method of creating a resist or other protective material pattern on a substrate using traversal of a focused energy beam such as a laser beam in a selected pattern over the substrate to cure a resin polymer, other resist material or other protective layer disposed over the substrate. The substrate may comprise a semiconductor wafer or other large-scale substrate comprising a large plurality of semiconductor die locations, may comprise a partial wafer or substrate, or a singulated semiconductor die.

Abstract: According to one embodiment of the invention, a method for via etching in a dielectric material includes providing a wafer (200) having a substrate (202), an etch stop layer (210) disposed outwardly from the substrate, an Organo-Silica-Glass layer (212) disposed outwardly from the etch stop layer (210), and a photoresist layer (216) disposed outwardly from the Organo-Silica-Glass layer (212), and positioning the wafer (200) within a process chamber (114). The method further includes introducing a first source gas mixture (110) into the process chamber (114) to etch a first portion of the Organo-Silica-Glass layer (212) utilizing the first source gas mixture (110), and introducing a second source gas mixture (110) into the process chamber (114) to etch, for a predetermined time period, a second portion of the Organo-Silica-Glass layer (212) down to the etch stop layer (210). The second source gas mixture (110) includes a fluorocarbon, a noble gas, carbon monoxide, and nitrogen.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: A method of patterning a metal layer that cleans the residue from a metal etch process without removing a photoresist etch mask. The method is particularly useful for the fabrication of micromirror devices, or other MEMS devices that use photoresist spacer layers. A photoresist layer is spun on to the mirror metal layer in step 906. The photoresist is patterned and developed in step 908 to form openings to the metal layer. The openings define areas where the mirror metal layer will be removed. The patterned photoresist is inspected in step 910. The mirror metal layer is etched in step 912 using the patterned photoresist layer as an etch mask. After the mirror metal has been etched, the webbing and other residues are removed in a clean up process 914 that uses photoresist developer as a solvent to remove the webbing. After the developer clean up process, the mirrors are inspected in step 916 to verify the proper gaps have been etched between the mirrors and the removal of the mirror etch residue.

Abstract: An organic film is etched by using plasma generated from an etching gas containing a first gas including a straight chain saturated hydrocarbon and a second gas including a nitrogen component.

Abstract: RIE processing chambers includes arrangements of gas outlets which force gas-flow-shadow elimination. Means are provided to control and adjust the direction of gases to the outlet to modify and control the direction of plasma flow at the wafer surface during processing. Means are provided to either move the exhaust paths for exhaust gases or to open and close exhaust paths sequentially, in a controlled manner, to modify flow directions of ions in the etching plasma. A combination of rotation/oscillation of a magnetic field imposed on the RIE chamber can be employed by rotation of permanent magnetic dipoles about the periphery of the RIE chamber or by controlling current through a coil wrapped around the periphery of the RIE process chamber to enhance the removal of the residues attributable to gas-flow-shadows formed by linear ion paths in the plasma.

Abstract: A process for etching a substrate 25 in an etching chamber 105, and simultaneously removing etch residue deposited on the surfaces of the walls 110 and components of the etching chamber 105. In one version, a two-stage method of opening a nitride mask layer on the substrate includes a first stage of providing a highly chemically reactive process gas in the chamber 105 to etch the nitride layer 32 and/or an underlying oxide layer 34, and a second stage of providing a less chemically reactive process gas in the chamber to etch the nitride layer 32 and/or the oxide layer 34 at a slower rate than the first stage. The first and second stage process gases may each comprise a fluorine containing gas, with the fluorine ratio of the first gas higher than the fluorine ratio of the second gas.

Abstract: A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Abstract: Methods for reducing contamination of semiconductor substrates after processing are provided. The methods include heating the processed substrate to remove adsorbed chemical species from the substrate surface by thermal desorption. Thermal desorption can be performed either in-situ or ex-situ. The substrate can be heated by convection, conduction, and/or radiant heating. The substrate can also be heated by treating the surface of the processed substrate with an inert plasma during which treatment ions in the plasma bombard the substrate surface raising the temperature thereof. Thermal desorption can also be performed ex-situ by applying thermal energy to the substrate during transport of the substrate from the processing chamber and/or by transporting the substrate to a transport module (e.g., a load lock) or to a second processing chamber for heating. Thermal desorption during transport can be enhanced by purging an inert gas over the substrate surface.

Abstract: A method is described for improving the exposure focus for modern steppers used in the lithography of semiconductor substrates such as wafers. A wafer is sawed from a semiconductor ingot in a particular direction relative to a reference point on the ingot. As a result of the sawing, a series of raised and recessed formations manifest on the surface of the wafer. After various layers have been added to the wafer and the photoresist layer is ready to be removed, the wafer is aligned with the stepper so that a dynamic focus area of the stepper is aligned with the formations and/or the sawing direction. Such alignment improves the critical dimension control and reduces variability in printing small geometry features during lithography, resulting in higher yields.

Abstract: The invention is directed to a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes the following steps: uniformly etching the polysilicon overfill layer; stopping the etching before the polysilicon layer is completely removed from the surface of the integrated circuit; and recess etching the polysilicon layer with microtrenching properties for forming a substantially planar recess near the top of the at least one trench.

Abstract: A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to selectively etch an organosilicate layer formed on a silicon oxide stop etch layer when fabricating a damascene structure.

Abstract: Disclosed is a method for forming contact by using the ArF lithography technology using a low-k dielectric sacrifice layer. The method comprises forming a layer to be etched on the semiconductor substrate, successively forming a low-k dielectric sacrifice layer and a hard mask on the etched layer, forming an anti-reflective layer and a photoresist pattern on the hard mask by using ArF lithography technology, selectively etching the anti-reflective layer and the hard mask and simultaneously removing the photoresist pattern when etching the hard mask, forming a contact hole exposing a surface of the semiconductor substrate by etching the low-k dielectric sacrifice layer and the layer by using the hard mask as a mask and removing the hard mask and the low-k dielectric sacrifice layer.

Abstract: As shown in FIG. 1A, a first resist film 2 comprising organic high molecules and a second resist film 3 comprising a photosensitive material are sequentially applied to a substrate 1 by the spin coat method or the spray method for forming a two-layer resist. Then, a mask 4 with which a metallic fine opening pattern 6 is formed on a mask substrate 5 comprising a dielectric, such as glass, is tightly contacted with the two-layer resist. Then, light is projected onto the back of the mask substrate to carry out exposure with near field light 7 which is effused from the opening portions of the mask 4 where no metal is formed. Then, a pattern is formed by processing the second resist layer 3 for development with a developing solution.

Abstract: A method and resultant structure of forming barrier layers in a via hole extending through an inter-level dielectric layer. A first barrier layer of TiSiN is conformally coated by chemical vapor deposition onto the bottom and sidewalls of the via holes and in the field area on top of the dielectric layer. A single plasma sputter reactor is used to perform two steps. In the first step, the wafer rather than the target is sputtered with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls. In the second step, a second barrier layer, for example of Ta/TaN, is sputter deposited onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

Abstract: A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.

Abstract: An apparatus and method for cleaning of disc-shaped objects, such as semiconductor wafers, employing a rotational fluid track. The cleaning may take place in a vertical cleaning chamber or optionally a horizontal cleaning chamber. Rotation of wafers is obtained without direct contact by motorized driver rollers that may have the potential of damaging the wafer. In preferred embodiments of the invention, a viscous shearing force is tangentially directed upon the surface of a wafer as the wafer rests upon support rollers within a cleaning chamber. Pressurized cleaning solutions are directed toward the wafer surface at an angle sufficient to impart a rotational force upon the wafer. In one embodiment of the invention, as the wafer spins within the cleaning chamber, a megasonic cleaning transducer is employed to enhance the surface cleaning process.

Abstract: A batch-type etching device and a method, which enable a stable process with high reproducibility by preventing contamination of CVD equipment by effectively removing H2O, CH3OH or CH3COOH and by-products adsorbing and remaining on the surface of a semiconductor wafer after etching is completed, are provided. The device comprises a reaction chamber, an exhaust port for evacuating the air inside the reaction chamber, a wafer-supporting boat for supporting at least one batch of semiconductor wafers inside the reaction chamber, a gas inlet port for introducing a reaction gas into the reaction chamber, and a microwave generator. The microwave generator is adapted to introduce microwaves into reaction chamber so that substances which adsorb and remain on the semiconductor wafers are desorbed and removed after etching is completed.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: Disclosed is a method for fabricating a stencil mask for use in electron beam lithography which improves resolution by effectively reducing beam blur resulting from coulomb repulsion effects in the electron beam. The disclosed method includes fabricating a first mask and a second mask that are then aligned and joined to form the final stencil mask. The structure of the second mask limits the number and controls the initial pattern of the electrons that pass through the stencil mask to limit beam blur, narrow the incident energy distribution, and improve the resolution of the final image.

Abstract: A method for fabricating a micromachined structure. The method includes forming a circuitry layer having an upper etch-resistant layer on an upper surface of a substrate, directionally etching a portion of the circuitry layer exposed by the upper etch-resistant layer, and directionally etching a portion the substrate exposed by the upper etch-resistant layer with a deep reactive ion etch.

Abstract: A method for fabricating a repair fuse box of a semiconductor device is disclosed. An etching stop polysilicon layer formed at a belt shape in edge portions of a repair fuse box is broken during a repair etching process without substantial departure from prior art methods for fabricating a repair fuse box of a semiconductor device. Thus, it is possible to improve repair yield of the semiconductor device.

Abstract: The invention relates to a method for monitoring a production process, whereby several models are used for detecting a finish point. The results of the model are subsequently compared with one another and the best model therefrom is used in other production processes to detect a finish point. The inventive method provides the advantage that process changes resulting from chamber contaminations or sensor drift are compensated for by selecting the best model, thereby ensuring reliable finish point detection even in case of unfavorable process conditions.

Abstract: An apparatus and method for gas-phase bromine trifluoride (BrF3) silicon isotropic room temperature etching system for both bulk and surface micromachining. The gas-phase BrF3 can be applied in a pulse mode and in a continuous flow mode. The etching rate in pulse mode is dependent on gas concentration, reaction pressure, pulse duration, pattern opening area and effective surface area.

Abstract: A unified process of making an electrical structure includes performing a plurality of laser etching operations on workpiece, without removing the workpiece from a laser processing system. The workpiece includes a conductive material disposed on an electrically insulating substrate, and the plurality of laser etching operations include, but are not limited to, two or more of forming a fiducial, forming thick metal traces separated by high aspect ratio spaces, cutting an alignment hole, cutting a folding line, and singulating the electrical structure. In another aspect of the invention, a database is prepared, and communicatively coupled to the laser processing system to provide control signals that direct a portion of the plurality of operations of the laser processing system, wherein each plurality of etching operations is defined with respect to a common coordinate system.

Abstract: A manufacturing method of a semiconductor device in which wire connection means is connected to an electrode formed on a surface of an IC and made of Cu or a material mainly containing Cu, comprises an oxide film removal treatment step of applying a Cu oxide film removal treatment to the electrode, and a supersonic bonding step of bonding the wire connection means with supersonic to the electrode after the oxide film removal treatment step.

Abstract: A semiconductor is cut by directing a green laser beam of high power, and subsequently directing a UV beam along the cut line. The first beam performs cutting with relatively rough edges and a high material removal rate, and the second beam completes the cut at the edges for the required finish, with a lower material quantity removal.

Abstract: Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.

Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.

Abstract: A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.

Abstract: A linear semiconductor material having a thin metal-oxide layer and a resist layer is conveyed at a constant speed by rotating rollers. An electron-beam drawing apparatus, in which micro-electron-guns are aligned circumferentially, is disposed between the rollers. The linear semiconductor material passes through a cylindrical hole of the electron-beam drawing apparatus such that a circuit pattern is formed on a surface of the linear semiconductor material by an electron beam. The linear semiconductor material is developed and etched, and divided into predetermined lengths. Thus a linear semiconductor is completed. A semiconductor device is manufactured by bundling a plurality of the linear semiconductors of predetermined length.

Abstract: The present invention provides a method for hermetically sealing a semiconductor laser element, by which the cleanness of a package can be maintained extremely satisfactorily in a stabilized state, in order to prevent organic substances from being adhered to the end faces of high output semiconductor laser elements due to photochemical actions. The method comprises the first step of introducing oxygen into a chamber of a hermetical-sealing apparatus and irradiating ultraviolet rays onto an unsealed package having a semiconductor laser element mounted, in the chamber, and the second step of purging the chamber with an inert gas and hermetically sealing an unsealed package in the inert gas atmosphere without being exposed to the outer atmosphere.

Abstract: A method and apparatus for monitoring a process by employing principal component analysis are provided. Correlated attributes are measured for the process to be monitored (the production process). Principal component analysis then is performed on the measured correlated attributes so as to generate at least one production principal component; and the at least one production principal component is compared to a principal component associated with a calibration process (a calibration principal component). The calibration principal component is obtained by measuring correlated attributes of a calibration process, and by performing principal component analysis on the measured correlated attributes so as to generate at least one principal component. A principal component having a feature indicative of at least one of a desired process state, process event and chamber state then is identified and is designated as the calibration principal component.

Abstract: An accurate dry etching technique is described that employs a flow of neutral radicals and a light beam. A dry etching apparatus 50 employs a neutral radical flow source 20 and a light beam 40 to irradiate a flow of neutral radicals 32, so that the velocity component of the neutral radicals parallel to the surface of an object to be etched 12 is reduced, and etches anisotropically the object to be etched, while the object 12 is exposed to the radical flow 32 whose parallel velocity component is decreased. The invention reduces the problem of etching parallel to the substrate while etching perpendicular to the substrate to improve anisotropic dry etching without any adverse or damage producing effect to dielectric or semiconductor layers due to ions.

Abstract: A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.

Abstract: Densely disposed patterns constituting a semiconductor integrated circuit device are divided into a first mask pattern and a second mask pattern 28B such that a phase shifter S can be disposed, and a predetermined pattern is transferred on a semiconductor substrate by multiple-exposure thereof. The second mask pattern 28B has a main light transferring pattern 26c1, a plurality of auxiliary light transferring patterns 26c2 disposed thereabout, and a phase shifter S disposed in the main light transferring pattern 26c1. The auxiliary light transferring patterns 26c2 are disposed such that respective distances from a center of each thereof to a center of the main light transferring pattern 26c1 are substantially equal. With this arrangement, a densely disposed pattern is transferred with sufficient process transfer margin.