Abstract: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating the wafer with a photoresist layer, and patterning the photoresist layer to expose at least the edge and an upper bevel region of the wafer for etching the material layers remaining after performing the first etch.

Abstract: A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.

Abstract: A method of fabricating a two dimensional nano-structure array of features comprising the steps of providing a substrate (10); forming an intermediate layer on said substrate (20), said intermediate layer having at least two selectively located regions (21, 22) of different uniform thickness; placing at least one layer of elements (30) over said intermediate layer, said elements placed in a close-packed arrangement forming an array of voids (33) between said elements; etching the intermediate layer through said voids, and so forming the array of features (51, 52) in said intermediate layer corresponding to the voids.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

Abstract: A film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a trench formed between adjacent raised surfaces. A first portion of the film is deposited over the substrate from a first gaseous mixture flowed into the process chamber by chemical-vapor deposition. Thereafter, the first portion is etched by flowing an etchant gas having a halogen precursor, a hydrogen precursor, and an oxygen precursor into the process chamber. Thereafter, a second portion of the film is deposited over the substrate from a second gaseous mixture flowed into the processing chamber by chemical-vapor deposition.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.

Abstract: A method for forming atomic layer deposition. The method includes placing a semiconductor substrate (e.g., wafer, LCD panel) including an upper surface in a chamber. The upper surface includes one or more carbon bearing species and a native oxide layer. The method includes introducing an oxidizing species into the chamber. The method includes treating the upper surface of the semiconductor substrate to remove the one or more carbon bearing species and form a particle film of silicon dioxide overlying the upper surface. The method includes introducing an inert gas into the chamber to purge the chamber of the oxidizing species and other species associated with the one or more carbon bearing species. A reducing species is introduced into the chamber to strip the particle film of silicon dioxide to create a substantially clean surface treated with hydrogen bearing species. The method includes performing another process (e.g.

Abstract: Embodiments of silicon semiconductor wafers and die having surface marks are described herein. A laser, or other marking tool, may be used to mark, substantially all of a surface of an IC wafer with surface marks, such as microdimples, that camouflage or reduce or eliminate the visibility of any surface imperfections such as smudges, scratches, or other marks that may reduce the marketability of packaged IC's where such surface imperfections are visible to the end customer. By marking the wafer prior to dicing, the entire surface of each individual die may have its entire bottom surface marked. Other embodiments are also described.

Abstract: A method of fabricating a semiconductor device includes a dry etching process of a silicon surface. The dry etching process is conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl2, Br2 and HI, wherein the dry etching process includes a first step conducted at a first temperature; and a second step conducted at a second temperature.

Abstract: A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching the protective film. Organic material containing C and F groups on the pad may be removed by heating with molecular vibration and/or microwaves, which may substantially prevent and/or minimize corrosion.

Abstract: Disclosed herein is a laser processing method for a wafer having a plurality of regions defined by streets, with the regions having a plurality of devices formed therein. The method irradiates the wafer with a laser beam along the streets, thereby forming laser processed grooves along the streets. It includes a processed groove formation step of irradiating the wafer while positioning the beam's focus spot on an irradiation surface of the wafer, thereby forming the laser processed grooves; and a processed groove finishing step of irradiating the wafer along the laser processed grooves formed by the processed groove formation step, while positioning the focus spot beyond the bottom of the laser processed grooves, thereby finishing both sides of the laser processed grooves.

Abstract: A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.

Abstract: A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas.

Abstract: A method and system for processing a substrate includes providing the substrate in a process chamber, where the substrate contains an oxide layer formed thereon, exciting a hydrogen-containing gas in a remote plasma source coupled to the process chamber, and exposing the substrate to a flow of the excited hydrogen-containing gas at a first substrate temperature lower than about 900° C. to remove the oxide layer from the substrate. The substrate is then maintained at a second temperature different than the first substrate temperature, and a silicon-containing film is formed on the substrate at the second substrate temperature.

Abstract: A method for structuring of silicon substrates for microsystem technological device elements, wherein the silicon substrate is covered with an etching mask and wherein the structures are furnished with a predetermined etching profile in the micrometer region with side walls and an etching depth At. For the generation of a predetermined positive etching profile, the side walls of the structures are furnished with the defined slope angle ? of from 60 degrees to 88 degrees relative to the etching bottom and the structures are generated with an etching depth At in the micrometer region. Initially an isotropic etching is performed such that a mask under etching u is generated, wherein the mask under etching u is formed approximately equal to the etching depth At.

Abstract: A plasma processing apparatus includes a chamber having a support for a substrate, and at least one gas inlet into the chamber. The apparatus is configured to alternately introduce an etch gas and a deposition gas into the chamber through the at least on gas inlet, and to strike a plasma into the etch gas and the deposition gas alternately introduced into the chamber. The apparatus is further equipped with an attenuation device for reducing and/or homogenizing the ion flux from the plasma substantially without affecting the neutral radical number density.

Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.

Abstract: A method of electrostatically chucking a wafer while removing heat from the wafer in a plasma reactor includes providing a polished generally continuous surface on a puck, placing the wafer on the polished surface of the puck and cooling the puck. A chucking voltage is applied to an electrode within the puck to electrostatically pull the wafer onto the surface of the puck with sufficient force to attain a selected heat transfer coefficient between contacting surfaces of the puck and wafer.

Abstract: In a polishing method of a GaN substrate according to this invention, first, while supplying a polishing solution 27 containing abrasives 23 and a lubricant 25, onto a platen 101, the GaN substrate is polished using the platen 101 and the polishing solution 27 (first polishing step). Then the GaN substrate is polished using the platen 101 in which abrasives 29 are buried, while supplying a lubricant 31 onto the platen 101 in which the abrasives 29 are buried (second polishing step).

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.

Abstract: A plasma etching apparatus includes a processing chamber in which a specimen is subjected to plasma processing, a specimen holder for holding the specimen, the specimen holder including a temperature controller for controlling temperatures at at least 2 positions of the specimen, at least two gas supply sources for supplying processing gases, at least two gas inlets for introducing the processing gases into the processing chamber, a regulator for independently controlling the compositions or the flow rates of the processing gases introduced from the at least two gas inlets and the temperatures controlled with at least two temperature controllers in the specimen holder, and an electromagnetic wave supply unit for sending an electromagnetic wave into the processing chamber, wherein the compositions or the flow rates of the processing gases introduced from the gas inlets and the temperature controlled with the temperature controllers in the specimen holder are independently controlled.

Abstract: A process and system are provided for processing at least one section of each of a plurality of semiconductor film samples. In these process and system, the irradiation beam source is controlled to emit successive irradiation beam pulses at a predetermined repetition rate. Using such emitted beam pulses, at least one section of one of the semiconductor film samples is irradiated using a first sequential lateral solidification (“SLS”) technique and/or a first uniform small grained material (“UGS”) techniques to process the such section(s) of the first sample. Upon the completion of the processing of this section of the first sample, the beam pulses are redirected to impinge at least one section of a second sample of the semiconductor film samples. Then, using the redirected beam pulses, such section(s) of the second sample are irradiated using a second SLS technique and/or a second UGS technique to process the at least one section of the second sample.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H2O plasma and the polymer is removed using H2O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Abstract: An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

Abstract: There is disclosed a plasma technique in which a plasma generation technique frequently used in various fields including a semiconductor manufacturing process is used, and generation of plasma instability (high-speed impedance change of a plasma) can efficiently be suppressed and controlled in order to manufacture stable products. In a method of disposing an object in a chamber and generating the plasma to treat the object, the chamber is sealed by a surrounding member so as to have an inner space, at least a part of the member includes a dielectric material, an RF induction coil is disposed outside the dielectric member, and a direct-current electric field is supplied into the inner space by a method of passing a direct current through the RF induction coil or another method, so that the plasma is stabilized.

Abstract: A method for manufacturing a semiconductor device includes: mounting a wafer having an exposed silicon nitride film, on an electrode received in a plasma chamber; dry-cleaning the chamber to remove reaction products accumulated on the wall and ceiling of the chamber, anisotropic-etching the silicon nitride film and an underlying silicon film for patterning; and removing the wafer from the chamber. The method repeats the treatment for a number of semiconductor wafers.

Abstract: The present invention is related to a method for fabricating an imprint mold which can be used in the field of nano-imprint lithography. Firstly, a diamond film and a photoresist film are successively formed onto a substrate; wherein the photoresist film is more capable of anticorrosion than the diamond film. Then an energy beam lithography system is provided to make the photoresist film form a photoresist mask with particularly arranged patterns. Because of the etching selectivity between the diamond film and the photoresist film, on the surface of the diamond film a pattern can be easily formed with recessions and protrusions according to the photoresist mask by dry etching method.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A method and system for facilitating etching. Specifically, the method includes incorporating a fluorescent marker in a layer of a grouping of patterned layers. Etching of the group of patterned layers is controlled based upon the fluorescent marker.

Abstract: An etching method etches an organic film by using an inorganic film as a mask at a high etch rate, in a satisfactory etch profile in a satisfactory in-plane uniformity without causing the inorganic film to peel off. An organic film formed on a workpiece is etched by using an inorganic film as a mask with a plasma produced by discharging an etching gas in a processing vessel (1). The etching method uses a mixed gas containing NH3 gas and O2 gas for etching the organic film when the organic film is to be etched in a pattern having an opening ratio of 40% or above. The etching method uses NH3 gas as an etching gas for etching the organic film when the organic film is to be etched in a pattern having an opening ratio below 40%.

Abstract: A plasma etching apparatus includes: a chamber capable of reducing pressure; a substrate support provided inside the chamber to place a substrate; a first electrode which is arranged outside and in proximity to the chamber and to which high frequency power is applied to generate plasma of an etching gas in the chamber; and a second electrode comprising a plurality of separated electrodes which are arranged between the chamber and the first electrode and to each of which high frequency power is applied independently.

Abstract: The invention relates to a device for introducing light into a waveguide, which device comprises: a light source, preferably an electro-optical converter, more preferably a VCSEL, for generating a light beam; a reflector for receiving at least a part of the light beam and for reflecting at least a part of the received part, wherein the waveguide and the material layer lie substantially mutually in line and both rest at least partially on a substantially flat substrate, wherein the light source and the reflector are positioned relative to the waveguide such that at least a part of the reflected part is introduced into the waveguide. The invention also relates to a device for emitting light from a waveguide. The invention further relates to a method for manufacturing such devices.

Abstract: An edge bead removal process is disclosed. The process includes providing a wafer having a feature layer, coating a photoresist on the feature layer, rotating the wafer, and removing an edge bead from the wafer by removing an edge bump portion from the edge bead and removing an edge region from the edge bead.

Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

Abstract: An etching process is described. A material layer having a bottom anti-reflection coating (BARC) and a patterned photoresist layer thereon is provided. An etching step is performed to the BARC using the patterned photoresist layer as a mask. A cleaning step is performed to remove the polymer formed on the surface of the patterned photoresist layer. Thereafter, another etching step is performed to the material layer using the patterned photoresist layer as a mask.

Abstract: Processes for treating a morphologically-modified surface of a silicon upper electrode of a plasma processing chamber include exposing the surface to a gas composition containing at least one gas-phase halogen fluoride. The gas composition is effective to remove silicon from the morphologically-modified surface and restore the surface state.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

Abstract: In a method of forming a semiconductor structure, a substrate comprising at least one contact pad is provided. A passivation layer is formed over the substrate. A mask which does not cover a portion of the passivation layer located over the at least one contact pad is formed over the passivation layer. An etching process adapted to remove a material of the passivation layer is performed and the mask is removed. Then, a second etching process adapted to remove residues of the passivation layer from the contact pad can be performed. The removal of the mask may be performed at a temperature of the substrate in a range from about ?20° C. to about 100° C. The second etching process can comprise exposing the substrate to a gaseous etchant comprising hydrogen and fluorine, an amount of hydrogen in the etchant being about equal to an amount of fluorine, or greater. Thus, a formation of oxides and/or fluorides on the at least one contact pad can be avoided.

Abstract: A mask forming method that can reduce manufacturing cost is disclosed. The method forms a mask on the surface of a member to be processed in order to form a desired pattern using liquid material for patterning. The method also includes applying resist to the entire surface of the member to be processed, drying the applied resist, patterning by removing the resist in a pattern-formation area using photolithography, and heating the resist.

Abstract: A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts.

Abstract: A method is provided that is capable of forming a wiring pattern having an extremely flat surface and few convexo-concave shapes on a substrate on which the wiring pattern is formed. The method to form a wiring pattern includes a bank forming process, a conductive layer forming process and a transferring process. Here, a photothermal converting layer including a photothermal converting material that converts light energy to thermal energy and a sublimation layer including a sublimable material are stacked on a first substrate in this order. In the bank forming process, a first light irradiation is performed to a fixed region on a surface of the first substrate from the sublimation layer side so as to sublimate a part of the sublimation layer, thereby forming banks made of the sublimation layer to a region excluding the region for light irradiation. In the conductive layer forming process, a conductive layer is provided between the banks.

Abstract: The present invention provides methods and apparatus for locally patterning surfaces. In one such method, an oxidizable thioether is adsorbed onto a conductive surface. The surface is then contacted with a fluid medium. A conducting stamp is then brought into contact with the fluid medium above the thioether-coated surface. Next, a potential is applied between the stamp and the surface. It is expected that the charge will be transferred through the medium to the coated surface along a shortest distance path, thereby locally oxidizing the thioether and effectively creating a negative patterned image of the conducting stamp on the surface. Remaining adsorbed thioether may then be used as a mask for standard etching or material addition procedures.

Abstract: An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

Abstract: A system and method of generating RF includes an RF generator, a variable DC power supply, and a comparator. The RF generator has an RF output coupled to an input of the transducer. The variable DC power supply has a control input and a DC output coupled to the RF generator. The comparator includes a first input coupled to a set point control signal, a second input coupled to the RF generator RF output, and a control signal output coupled to a voltage control input on the variable DC power supply.

Abstract: A method for reducing wafer damage during an etching process is provided. In one of the many embodiments, the method includes assigning a bias voltage to each of at least one etching process, and generating the assigned bias voltage before initiation of one of the at least one etching process. The method further includes applying the assigned bias voltage to an electrostatic chuck before initiation of one of the at least one etching processes. The assigned bias voltage level reduces wafer arcing.