In Hierarchically Structured Memory Systems, E.g., Virtual Memory Systems, Etc. (epo) Patents (Class 711/E12.016)

  • Publication number: 20120079165
    Abstract: Paging memory from random access memory (‘RAM’) to backing storage in a parallel computer that includes a plurality of compute nodes, including: executing a data processing application on a virtual machine operating system in a virtual machine on a first compute node; providing, by a second compute node, backing storage for the contents of RAM on the first compute node; and swapping, by the virtual machine operating system in the virtual machine on the first compute node, a page of memory from RAM on the first compute node to the backing storage on the second compute node.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Archer, Michael A. Blocksome, Todd A. Inglett, Joseph D. Ratterman, Brian E. Smith
  • Publication number: 20120072638
    Abstract: Trapping and/or processing of read/write accesses to hardware devices represented to the host through a memory mapped space may be performed without knowledge of the processor's instruction set or semantics of the processor's instructions. A single step routine may be executed to recognize page faults occurring from read/write accesses to emulated memory pages and causing the guest to retry the operation on a single step buffer. The hypervisor may perform post-operation processing on the single step buffer after the guest retries and completes the read or write access. For example, on a read request, the single step routine may place the guest value in the single step buffer for reading by the guest on a retry operation. On a write request, the single step routine may direct the guest to retry the write operation into the single step buffer.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: Unisys Corp.
    Inventors: J. Alan Grubb, John Landis, Bryan Thompson, James R. Hunter
  • Publication number: 20120072906
    Abstract: A method and system for managing direct memory access (DMA) in a computer system without a host input/output memory management unit (IOMMU). The computer system hosts virtual machines and allows memory overcommit. The computer receives, from a guest operating system that runs on a virtual machine, a request for mapping a guest address to a bus address. The computer translates the guest address to a host address and pins a memory page containing the host address to keep the memory page in host memory. The host address is then returned to the guest operating system to allow a device to use the host address as the bus address for direct memory access (DMA) to a buffer managed by the guest operating system.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: RED HAT ISRAEL, LTD.
    Inventors: Michael Tsirkin, Christopher M. Wright
  • Publication number: 20120066450
    Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.
    Type: Application
    Filed: August 11, 2011
    Publication date: March 15, 2012
    Applicant: INFINIDAT LTD.
    Inventors: Yechiel YOCHAI, Leo CORRY, Haim KOPYLOVITZ
  • Publication number: 20120060013
    Abstract: An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 8, 2012
    Applicant: International Business Machines Corporation
    Inventor: Maharaj Mukherjee
  • Publication number: 20120054456
    Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues with the processing module determining an end-of-life memory level for the memory device. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.
    Type: Application
    Filed: August 5, 2011
    Publication date: March 1, 2012
    Applicant: CLEVERSAFE, INC.
    Inventors: GARY W. GRUBE, JASON K. RESCH, TIMOTHY W. MARKISON, ILYA VOLVOVSKI, MANISH MOTWANI
  • Publication number: 20120054411
    Abstract: In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes.
    Type: Application
    Filed: August 19, 2011
    Publication date: March 1, 2012
    Applicant: VMware, Inc.
    Inventor: Ole AGESEN
  • Publication number: 20120054412
    Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Damian L. Osisek, Gustav E. Sittmann, III, Cynthia Sittmann
  • Patent number: 8127075
    Abstract: A storage device includes an interface for receiving and outputting messages for processing data units, wherein each data unit includes message input field parameters, message output field parameters, and content field parameters, a non-volatile memory for storing data units, a volatile memory, and a processor coupled to the interface, the non-volatile memory and the volatile memory, for manipulation of the parameter values in the data units, and storing the data units in at least one of the non-volatile memory and the volatile memory.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: February 28, 2012
    Assignee: Seagate Technology LLC
    Inventors: Robert Harwell Thibadeau, Kevin Arthur Gomez
  • Patent number: 8122207
    Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 21, 2012
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Michael John Smith, David T. Wang
  • Publication number: 20120042115
    Abstract: Apparatus and methods for improved efficiency in accessing meta-data in a storage controller of a virtualized storage system. Features and aspects hereof walk/retrieve meta-data for one or more other I/O requests when retrieving meta-data for a first I/O request. The meta-data may include mapping information for mapping logical addresses of the virtual volume. Meta-data may also include meta-data associated with higher level, enhanced data services provide by or in conjunction with the storage system. Enhanced data services may include features for synchronous mirroring of a volume and/or management of time-based snapshots of the content of a virtual volume.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Applicant: LSI CORPORATION
    Inventor: Howard Young
  • Publication number: 20120036324
    Abstract: A system and method for navigating or editing may include storing multiple forward or redo stacks and a single back or undo stack. The forward or undo stacks may include separate stacks for each page from which navigation occurs to a page of lower hierarchical level or for each operation for which another operation is subsequently performed. Positions of references in the forward or redo stacks may be modified in response to navigations or edits to place a last navigated page or operation at the top of the stack. The timing of such movement of references may be optimized.
    Type: Application
    Filed: August 27, 2010
    Publication date: February 9, 2012
    Inventor: Aaron Grunberger
  • Publication number: 20120036321
    Abstract: The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Applicant: LSI CORPORATION
    Inventors: Ross Zwisler, Brian McKean, Kevin Kidney
  • Publication number: 20120036325
    Abstract: Techniques are disclosed for managing memory within a virtualized system that includes a memory compression cache. Generally, the virtualized system may include a hypervisor configured to use a compression cache to temporarily store memory pages that have been compressed to conserve memory space. A “first-in touch-out” (FITO) list may be used to manage the size of the compression cache by monitoring the compressed memory pages in the compression cache. Each element in the FITO list corresponds to a compressed page in the compression cache. Each element in the FITO list records a time at which the corresponding compressed page was stored in the compression cache (i.e. an age). A size of the compression cache may be adjusted based on the ages of the pages in the compression cache.
    Type: Application
    Filed: July 13, 2011
    Publication date: February 9, 2012
    Applicant: VMWARE, INC.
    Inventors: Ali MASHTIZADEH, Irfan AHMAD
  • Publication number: 20120030405
    Abstract: According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.
    Type: Application
    Filed: March 31, 2011
    Publication date: February 2, 2012
    Inventors: Atsushi KUNIMATSU, Goh Uemura, Tsutomu Owa
  • Publication number: 20120030404
    Abstract: In the computer system, a storage system provides a storage level virtual volume based on thin provisioning technology, to a physical server on which a virtual machine is defined. The storage system releases the area of the logical volume corresponding to the storage level virtual volume accessed by a virtual machine which is specified to be deleted, on the basis of storage level virtual volume conversion information which is managed by the storage system.
    Type: Application
    Filed: February 5, 2010
    Publication date: February 2, 2012
    Inventors: Masayuki Yamamoto, Masataka Innan, Nobuhiko Ando, Takato Kusama, Nobuo Beniyama, Yoshiki Fukui, Katsutoshi Asaki
  • Publication number: 20120017065
    Abstract: A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.
    Type: Application
    Filed: November 13, 2009
    Publication date: January 19, 2012
    Inventor: Naveen Muralimanohar
  • Publication number: 20120017042
    Abstract: A storage system has multiple disk controller (DKC) units that are coupled to one another in accordance with a coupling mode that satisfies the following (a1) through (a3): (a1) One DKC inside one DKC unit and one DKC inside another DKC unit are coupled via a second type of coupling medium that differs from the internal bus of the DKC and has a longer maximum communication distance than a first type of coupling medium, which is the same type of coupling medium as the internal bus of the DKC; (a2) the one DKC unit virtualizes a logical volume of the other DKC unit and provides this virtualized logical volume to host(s) coupled to the one DKC unit; and (a3) the other DKC unit virtualizes a logical volume of the DKC unit and provides this virtualized logical volume to host(s) coupled to the other DKC unit.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: HITACHI, LTD.
    Inventors: Yuko Matsui, Hiroshi Kawano, Shigeo Homma, Masayuki Yamamoto
  • Publication number: 20120017030
    Abstract: Systems and methods for optimizing write operations to a storage device in a virtualized computing environment comprise monitoring write operations issued by an application running on a virtual machine's (VM) operating system, wherein the VM is hosted by a hypervisor providing access to a storage device in a virtualized computing environment; and causing a virtual file system (VFS) supported by the operating system to call on a first para-virtualized file system (PVFS FE) supported by the operating system to execute a write operation, in response to determining that the write operation is to write data to the storage device, wherein data that is to be written to the storage device is first written to a VM memory area allocated to the VM and accessible to the hypervisor hosting the VM.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 19, 2012
    Applicant: International Business Machines Corporation
    Inventors: Eran Borovik, Eran Rom, Avishay Traeger
  • Patent number: 8099553
    Abstract: A virtual drive data storage refactoring system includes a base drive, a plurality of virtual drives coupled to the base drive and hierachly below the base drive, wherein the virtual drives each include a plurality of data storage blocks and a virtual drive controller system. The virtual drive controller system is operable to coordinate data storage on the base drive and the plurality of virtual drives.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: January 17, 2012
    Assignee: Dell Products L.P.
    Inventor: James Craig Lowery
  • Publication number: 20120011315
    Abstract: A RAID group is not configured from a plurality of storage devices. A storage area of a storage device is provided directly to a virtual volume instead of providing a logical volume inside the RAID group to the virtual volume. The storage system, upon receiving a write request with respect to a virtual storage area, first, specifies a data redundancy configuration (the number of data partitions and the number of created parities) and a RAID level set to a virtual volume including this virtual storage area. From among storage devices selected in accordance with specified RAID level and redundancy configuration for this virtual storage area, a storage area is selected that is not allocated to any virtual storage area, and allocates this storage area to this virtual storage area. The storage system partitions the data and writes this data together with the parity to this allocated storage area.
    Type: Application
    Filed: January 14, 2010
    Publication date: January 12, 2012
    Applicant: HITACHI, LTD.
    Inventors: Taro Ishizaki, Katsuyoshi Suzuki
  • Publication number: 20120011340
    Abstract: A virtual storage layer (VSL) for a non-volatile storage device presents a large, logical address space having a logical capacity that may exceed the storage capacity of the non-volatile storage device. The VSL implements persistent storage operations within the logical address space; storage operations performed within the logical address space may be persisted on the non-volatile storage device. The VSL maintains storage metadata to allocate ranges of the logical address space to storage entities. The VSL provides for allocation of contiguous logical address ranges, which may be implemented by segmenting logical identifiers into a first portion referencing storage entities, and a second portion referencing storage entity offsets. The VSL persists data on the non-volatile storage device in a sequential, log-based format. Accordingly, storage clients, such as file systems, databases, and other applications, may delegate logical allocations, physical storage bindings, and/or crash-recovery to the VSL.
    Type: Application
    Filed: January 6, 2011
    Publication date: January 12, 2012
    Applicant: FUSION-IO, INC.
    Inventors: David Flynn, Jonathan Thatcher
  • Publication number: 20120005401
    Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, David Navarro, Bret R. Olszewski, Sergio Reyes
  • Publication number: 20120005439
    Abstract: A computer includes a memory that stores data, a cache memory that stores a copy of the data, a directory storage unit that stores directory information related to the data and includes information indicating that the data is copied to the cache memory, a directory cache storage unit that stores a copy of the directory information stored in the directory storage unit, and a control unit that controls storage of data in the directory cache storage unit, manages the data copied from the memory to the cache memory by dividing the data into an exclusive form and a shared form, and sets a priority of storage of the directory information related to the data fetched in the exclusive form in the directory cache storage unit higher than a priority of storage of the directory information related to the data fetched in the shared form in the directory cache storage unit.
    Type: Application
    Filed: September 1, 2011
    Publication date: January 5, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Megumi UKAI
  • Publication number: 20120005404
    Abstract: Data storage devices and methods are disclosed that provide a status indication when a maintenance operation is to be performed prior to completion of a write command. A method includes receiving a write command from a host device to write data to the non-volatile memory while the data storage device is operatively coupled to the host device. In response to determining that a maintenance operation is to be performed prior to the completion of the write command, an indication is sent to the host device that the write command has a status of incomplete.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: SANDISK IL LTD.
    Inventors: MOSHE RAZ, MICHAEL FONG
  • Publication number: 20110320723
    Abstract: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Inventors: Ehud Cohen, Oleg Margulis, Raanan Sade, Stanislav Shwartsman
  • Patent number: 8086808
    Abstract: A method of migrating a computer system between a virtualized environment and a non-virtualized environment comprises configuring one or more storage volumes for a migration destination in a destination environment based on a migration request containing a backup requirement specifying one or more copy groups, each copy group including storage volumes that store data for at least one of a virtualized device and a non-virtualized device; converting and migrating data from a migration source in a source environment to the one or more configured storage volumes of the migration destination based on copy group information of the one or more copy groups, one of the source environment and the destination environment being a virtualized environment, and another of the source environment and the destination environment being a non-virtualized environment; and migrating backup unit/group information by replacing copy group information in the source environment with copy group information in the destination environment
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Naoko Ichikawa
  • Patent number: 8086822
    Abstract: In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table used by the virtualization software wherein at least a portion of the guest page table and the shadow page table share computer memory.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: December 27, 2011
    Assignee: VMware, Inc.
    Inventors: Scott W. Devine, Lawrence S. Rogel, Prashanth P. Bungale, Gerald A. Fry
  • Publication number: 20110314203
    Abstract: Resource adjustment methods and systems for virtual machines (VMs) for use in at least one physical device are provided. First, a first VM having a first resource set and a second VM having a second resource set are respectively enabled to enter a suspended state. A first user space address and a second user space address are respectively obtained from a first VM memory page table corresponding to the first VM and a second VM page table corresponding to the second VM, and a first physical memory address corresponding to the first user space address in the physical device and a second physical memory address corresponding to the second user space address in the physical device are obtained from a Hypervisor. The first user space address is mapped to the second physical memory address by the Hypervisor. Then, the first VM is enabled to enter an execution state, and the second VM is stopped.
    Type: Application
    Filed: November 30, 2010
    Publication date: December 22, 2011
    Inventors: Lee-Chung CHEN, Hui-Kuang Chung, Chih-Kai Hu, Chung-Ting Kao
  • Publication number: 20110314223
    Abstract: An apparatus comprising a plurality of tag circuits, a plurality of compare circuits and a processing circuit. The plurality of tag circuits may each be configured to store memory mapping data. The plurality of compare circuits may each be configured to generate a respective compare result in response to a match between the memory mapping data of a respective one of the tag circuits and a respective one of a plurality of tag fields. The processing circuit may be configured to receive each of the compare results from the plurality of compare circuits. The processing circuit may also be configured to count occurrences of the matches. If more than one match is identified within a predetermined time, the processing circuit may invalidate the memory mapping data and the tag field. If more than one match is identified within a predetermined time, the processing circuit may also re-fetch the memory mapping data.
    Type: Application
    Filed: June 17, 2010
    Publication date: December 22, 2011
    Inventors: Yair Orbach, Nahum N. Vishne, Assaf Rachlevski, Alex Shinkar
  • Publication number: 20110314206
    Abstract: An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 22, 2011
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Hong Beom PYEON, Jin-Ki KIM, HakJune OH
  • Patent number: 8082406
    Abstract: Techniques for reducing data storage needs using continuous data protection and replication are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for reducing data storage needs using a continuous data protection and replication device comprising creating a master image of material identified by a user, generating a virtual replica of the master image on a storage area network using the continuous data protection and replication device to virtualize physical storage containing the master image, generating a copy of the virtual replica on the storage area network, and providing a virtual logical unit number to access the copy, wherein the access enables a process which requires exclusive access to content of the master image to obtain such access without requiring physical storage for an entire copy of the master image.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: December 20, 2011
    Assignee: Symantec Corporation
    Inventors: Abhay Kumar Singh, Raghu Krishnamurthy, Gopal Sharma, Deepak Tawri
  • Patent number: 8082416
    Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 20, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Gaurav Singh, Dave Hass, Daniel Chen
  • Publication number: 20110307677
    Abstract: In a device for managing data buffers in a memory space distributed over a plurality of memory elements, the memory space is allocatable by memory pages, each buffer including one or more memory pages. The buffers are usable by at least one processing unit for the execution of an application, the application being executed by a plurality of processing units executing tasks in parallel. The memory elements are accessible in parallel by the processing units. The device includes means for allocating buffers to the tasks during the execution of the application and means for managing access rights to the buffers. The means for managing the access rights to the buffers include means for managing access rights to the pages in a given buffer, to verify that writing to a given page does not modify data currently being read from the page or that reading from a given page does not access data currently being written to the page, in such a way as to share the buffer between unsynchronized tasks.
    Type: Application
    Filed: October 20, 2009
    Publication date: December 15, 2011
    Applicant: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Raphael David, Nicolas Ventroux
  • Patent number: 8078827
    Abstract: A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address to a first guest-physical memory address or an invalid entry, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address to a host-physical memory address or an invalid entry, and managing a cache page table, wherein the cache page table selectively provides a third translation from the guest-virtual memory address to the host-physical memory address, a second guest-physical memory address or an invalid entry.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: December 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Volkmar Uhlig, Leendert van Doorn
  • Publication number: 20110302373
    Abstract: An apparatus comprising first holding units each of which includes first nodes connected in series and shifts first data in each first node in a first direction, second holding units each of which includes second nodes connected in series and shifts second data in each second node in a second direction is provided. Each first node corresponds to at least one of the second nodes. The apparatus further comprises an operation unit which executes, for a node of interest which is a first node, an operation using first data in the node of interest, and second data in at least one of the second nodes to which the node of interest corresponds, and an input unit which inputs, in parallel, the first data to at least two out of the first holding units, and serially inputs the second data to at least two out of the second holding units.
    Type: Application
    Filed: May 11, 2011
    Publication date: December 8, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tadayuki Ito
  • Publication number: 20110296120
    Abstract: Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a virtual buffer interface capability between a plurality of processes/engines and a memory pool.
    Type: Application
    Filed: October 1, 2010
    Publication date: December 1, 2011
    Applicant: QUALCOMM Incorporated
    Inventor: Raheel Khan
  • Publication number: 20110283069
    Abstract: The present invention provides a method for estimating a capacity usage status of a storage unit, where the storage unit includes a plurality of sectors. The method includes: estimating capacity usage statuses of a portion of sectors; and utilizing a controller to estimate the capacity usage status of the storage unit according to the estimated capacity usage statuses of the portion of sectors in a situation of not estimating capacity usage statuses of all of the sectors of the storage unit.
    Type: Application
    Filed: August 6, 2010
    Publication date: November 17, 2011
    Inventors: Shu-Yi Lin, Kai-Lung Cheng, Yuan-Chu Yu
  • Patent number: 8055863
    Abstract: There is disclosed a data storage system used in a computer environment where there are plural host computers and plural storage array controllers. When a remote copy is made while assuring the order of writing across plural storage array controllers, one of the host computers gains copy information about all the storage array controllers associated with the remote copy as a representative. The representative one of the storage array controllers collects and stores copy statuses which are individually managed by the storage array controllers for which a remote copy is made. The host computer gains the copy statuses from the representative controller using an instruction to gain the copy statuses.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: November 8, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Maki, Masahide Sato, Katsuhisa Miyata, Kenta Ninose
  • Publication number: 20110264868
    Abstract: The statuses of an actual area are (1) a first status which indicates that [the actual area] is already initialized and can be assigned to a virtual area, (2) a second status which indicates that [the actual area] is already assigned to a virtual area, and (3) a third status which indicates that [the actual area] cannot be assigned to a virtual area and initialization which is specified data write is to be performed. The storage controller limits the total virtual volume capacity which is the total capacity of one or more virtual volumes which are associated with the pool, in accordance with whether the pool comprises an actual page in the third status or not, to the capacity of the pool or smaller.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 27, 2011
    Inventors: Yutaka Takata, Shintaro Inoue
  • Publication number: 20110264867
    Abstract: Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, and a set of controller/translator units TX1, TX2, TX3 arranged to convert respective application programs into program threads T1, T2, etc., which are executed by the processors. Each controller/translator unit sets a first mode where a single thread T1 executes on a single processor P1, orders a second mode for two or more threads T1, T2 that are forced to execute one at a time on a single processor P2 such as by setting affinity with that processor, and orders a third mode to selectively apply active memory consistency protection in relation to accesses to explicit or implicit shared memory while allowing the multiple threads T1, T2, T3, T4 to execute on the multiple processors.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kit M. WAN, Gisle DANKEL
  • Publication number: 20110264886
    Abstract: Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.
    Type: Application
    Filed: April 28, 2011
    Publication date: October 27, 2011
    Applicant: BROADCOM CORPORATION
    Inventor: Uri Elzur
  • Publication number: 20110264841
    Abstract: A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized environment. A control program in a virtual operating system is used to manage the user portions of the virtual operating system, each commonly referred to as a guest. A guest operating system runs on each guest and applications can run on each guest operating system. A memory management facility manages shared memory which includes a class cache configured to store class data. The shared memory may be mounted onto each guest using a cluster file system or accessed via an API interface thereby allowing the class cache to be shared across the guests. By sharing the class cache among the guests, multiple copies of the same class data are no longer necessary thereby optimally using the physical memory on the host.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 27, 2011
    Applicant: International Business Machines Corporation
    Inventors: Gianni S. Duimovich, Prasanna K. Kalle, Angela Lin, Andrew R. Low, Prashanth K. Nageshappa
  • Publication number: 20110252212
    Abstract: A storage system having a plurality of storage devices including a first type storage device and a second type storage device, a reliability attribute and/or a performance attribute of the first type storage device being different from a reliability attribute and/or a performance attribute of the second type storage device. The storage system also has a control unit and managing a plurality of virtual volumes. If necessary, a storage area allocated to a first portion of a virtual volume of the plurality of virtual volumes is changed from a first type storage area of the plurality of first type storage areas to a second type storage area of the plurality of second type storage areas while another first type storage area of the plurality of first type storage areas is allocated to a second portion of the virtual volume.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: HITACHI, LTD.
    Inventors: Teiko Kezuka, Akira Murotani, Seiichi Higaki
  • Publication number: 20110252204
    Abstract: A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: NVIDIA Corporation
    Inventors: Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls, Peter C. Mills
  • Publication number: 20110252198
    Abstract: A storage network system that prevents waste of a core's resources and is thereby operated efficiently, and a method for controlling such a storage network system are provided. Policy differences between a core and a plurality of edges are buffered by enabling hierarchical control of data storage on the side of the plurality of edges in cooperation with hierarchical control of data storage on the core side, and the buffered policy is applied to the hierarchical control of the data storage on the core side.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 13, 2011
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi Ogasawara, Takahiro Nakano, Hitoshi Kamei
  • Publication number: 20110252192
    Abstract: Approaches for an object store implemented, at least in part, on one or more solid state devices. The object store may store objects on a plurality of solid state devices. The object store may include a transaction model means for ensuring that the object store performs transactions in compliance with atomicity, concurrency, isolation, and durability (ACID) properties. The object store may include means for providing parallel flushing in a write cache maintained on each of the solid state devices. The object store may include means for maintaining one or more double-write buffers, for the object store, at a location other than the solid state devices. The object store may optionally comprise means for maintaining one or more circular transaction logs, for the object store, at a location other than the solid state devices. The object store may operate to minimize write operations performed on the solid state devices.
    Type: Application
    Filed: January 3, 2011
    Publication date: October 13, 2011
    Inventors: John Busch, Darpan Dinker, Darryl Ouye
  • Patent number: 8037244
    Abstract: A storage apparatus comprises a disk device and a disk controller for controlling the disk device. The disk controller provides a data volume including an actual volume and virtual volume with a volume capacity virtualization function. The virtual volume is associated with a pool volume for storing the actual data and the actual data is stored in the pool volume. In response to a write command from a host computer, the disk controller compresses write data under RAID 5 control and stores the compressed data in a storage area in the actual volume. If the entire compressed data cannot be stored in that storage area, the disk controller stores the remaining portion of the compressed data in the virtual volume.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: October 11, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Muto, Isamu Kurokawa, Ran Ogata, Kazue Jindo
  • Publication number: 20110246721
    Abstract: A method and apparatus for data backup are disclosed. Embodiments of the method comprise receiving a set of data from a local computer, caching the received data locally on the storage appliance in a buffer module, uploading the cached data to a remote computer, and accessing the set of data using the storage device. Embodiments of the apparatus comprise a network interface module for establishing connection of the storage appliance with at least one computer in a local network and at least one remote computer in a cloud network, a buffer module for receiving data to be backed up from the at least one computer; and a processor.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: SONY CORPORATION
    Inventor: ADRIAN CRISAN
  • Publication number: 20110246553
    Abstract: A method and a system provide validated internal data about a running batch application. The validated internal data may be accessed via administrative interface for batch application for monitoring and management. The system comprises a batch host to host an instance of a running batch application. The running batch application comprises an interface to a batch agent. A controller is in communication with the batch agent and requests validated internal data about the running batch application via the batch agent. The controller further receives the validated internal data about the running batch application from the batch agent.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Inventors: Mahesh K. Somani, Kumar Rethinakaleeswaran, Debashis Saha